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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

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This commit is contained in:
David Harris 2023-03-28 14:33:18 -07:00
commit 92a7e86942
6 changed files with 39 additions and 25 deletions
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2
src/cache/cachefsm.sv vendored
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@ -135,7 +135,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
end
// com back to CPU
assign CacheCommitted = CurrState != STATE_READY;
assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD);
assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) |
(CurrState == STATE_FETCH) |
(CurrState == STATE_WRITEBACK) |

5
src/ebu/ahbcacheinterface.sv
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@ -33,7 +33,8 @@ module ahbcacheinterface #(
parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
parameter AHBWLOGBWPL, // Log2 of ^
parameter LINELEN, // Number of bits in cacheline
parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
parameter LLENPOVERAHBW, // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
parameter READ_ONLY_CACHE
)(
input logic HCLK, HRESETn,
// bus interface controls
@ -115,7 +116,7 @@ module ahbcacheinterface #(
flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
buscachefsm #(BeatCountThreshold, AHBWLOGBWPL) AHBBuscachefsm(
buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST);

5
src/ebu/buscachefsm.sv
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@ -33,7 +33,8 @@
// HCLK and clk must be the same clock!
module buscachefsm #(
parameter BeatCountThreshold, // Largest beat index
parameter AHBWLOGBWPL // Log2 of BEATSPERLINE
parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE
parameter READ_ONLY_CACHE
)(
input logic HCLK,
input logic HRESETn,
@ -121,7 +122,7 @@ module buscachefsm #(
(CurrState == DATA_PHASE) |
(CurrState == CACHE_FETCH & ~HREADY) |
(CurrState == CACHE_WRITEBACK & ~HREADY);
assign BusCommitted = CurrState != ADR_PHASE;
assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY_CACHE & CurrState == MEM3);
// AHB bus interface
assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW)) & ~Flush) |

2
src/ifu/ifu.sv
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@ -251,7 +251,7 @@ module ifu (
.NextSet(PCSpillNextF[11:0]),
.PAdr(PCPF),
.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW)
ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1)
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
.HRDATA,
.Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),

2
src/lsu/lsu.sv
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@ -275,7 +275,7 @@ module lsu (
.FetchBuffer, .CacheBusRW,
.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface(
ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
.HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),

48
testbench/testbench.sv
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@ -29,9 +29,9 @@
`include "tests.vh"
`define PrintHPMCounters 1
`define BPRED_LOGGER 1
`define I_CACHE_ADDR_LOGGER 1
`define D_CACHE_ADDR_LOGGER 1
`define BPRED_LOGGER 0
`define I_CACHE_ADDR_LOGGER 0
`define D_CACHE_ADDR_LOGGER 0
module testbench;
parameter DEBUG=0;
@ -169,7 +169,8 @@ logic [3:0] dummy;
logic InitializingMemories;
integer ResetCount, ResetThreshold;
logic InReset;
logic Begin;
// instantiate device to be tested
assign GPIOIN = 0;
assign UARTSin = 1;
@ -417,7 +418,7 @@ logic [3:0] dummy;
if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
integer HPMCindex;
logic StartSampleFirst;
logic StartSampleDelayed;
logic StartSampleDelayed, BeginDelayed;
logic EndSampleFirst, EndSampleDelayed;
logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
@ -476,8 +477,11 @@ logic [3:0] dummy;
assign StartSampleFirst = InReset;
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
assign Begin = StartSampleFirst & ~ BeginDelayed;
end
always @(negedge clk) begin
@ -528,7 +532,7 @@ logic [3:0] dummy;
// initialize the branch predictor
if (`BPRED_SUPPORTED == 1) begin
if (`BPRED_SUPPORTED) begin
integer adrindex;
always @(*) begin
@ -551,55 +555,63 @@ logic [3:0] dummy;
end
if (`I_CACHE_ADDR_LOGGER == 1) begin
if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin
int file;
string LogFile;
logic resetD, resetEdge;
logic Enable;
assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset;
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
LogFile = $psprintf("ICache.log");
file = $fopen(LogFile, "w");
$fwrite(file, "BEGIN %s\n", memfilename);
end
string HitMissString;
assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : "M";
always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n");
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(~dut.core.StallD & ~dut.core.FlushD) begin
$fwrite(file, "%h R\n", dut.core.ifu.PCPF);
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
if(Enable) begin // only log i cache reads
$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
end
if(EndSample) $fwrite(file, "END %s\n", memfilename);
end
end
if (`D_CACHE_ADDR_LOGGER == 1) begin
if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin
int file;
string LogFile;
logic resetD, resetEdge;
string HitMissString;
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : "M";
initial begin
LogFile = $psprintf("DCache.log");
file = $fopen(LogFile, "w");
$fwrite(file, "BEGIN %s\n", memfilename);
end
always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n");
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin
$fwrite(file, "%h R\n", dut.core.lsu.PAdrM);
$fwrite(file, "%h R %s\n", dut.core.lsu.PAdrM, HitMissString);
end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin
$fwrite(file, "%h W\n", dut.core.lsu.PAdrM);
$fwrite(file, "%h W %s\n", dut.core.lsu.PAdrM, HitMissString);
end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change
$fwrite(file, "%h A\n", dut.core.lsu.PAdrM);
$fwrite(file, "%h A %s\n", dut.core.lsu.PAdrM, HitMissString);
end else if (dut.core.lsu.bus.dcache.FlushDCache) begin
$fwrite(file, "%h F\n", dut.core.lsu.PAdrM);
$fwrite(file, "%h F %s\n", dut.core.lsu.PAdrM, HitMissString);
end
end
if(EndSample) $fwrite(file, "END %s\n", memfilename);
end
end
if (`BPRED_SUPPORTED == 1) begin
if (`BPRED_SUPPORTED) begin
if (`BPRED_LOGGER) begin
string direction;
int file;