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Added comment to uart LCR to check reset value after updating FPGA.

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Ross Thompson 2023-06-15 15:39:51 -05:00
parent 4428babda9
commit bdc5656ef3
1 changed files with 1 additions and 1 deletions
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src/uncore/uartPC16550D.sv
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@ -138,7 +138,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
if (~PRESETn) begin // Table 3 Reset Configuration
IER <= #1 4'b0;
FCR <= #1 8'b0;
LCR <= #1 8'b11; // spec says to reset to 0, but FPGA needs to reset to 8 data bits
LCR <= #1 8'b11; // **** fpga used to require reset to 3, double check this is no longer needed.
MCR <= #1 5'b0;
LSR <= #1 8'b01100000;
MSR <= #1 4'b0;