mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
More parameterization. Copied Lim. Still no slow down.
This commit is contained in:
Ross Thompson
parent
b91b54589e
commit
052bc95966
14
src/cache/cache.sv
vendored
14
src/cache/cache.sv
vendored
@ -27,9 +27,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
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module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
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input logic clk,
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input logic reset,
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input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
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@ -40,7 +38,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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input logic FlushCache, // Flush all dirty lines back to memory
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input logic InvalidateCache, // Clear all valid bits
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input logic [11:0] NextSet, // Virtual address, but we only use the lower 12 bits.
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input logic [`PA_BITS-1:0] PAdr, // Physical address
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input logic [PA_BITS-1:0] PAdr, // Physical address
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input logic [(WORDLEN-1)/8:0] ByteMask, // Which bytes to write (D$ only)
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input logic [WORDLEN-1:0] CacheWriteData, // Data to write to cache (D$ only)
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output logic CacheCommitted, // Cache has started bus operation that shouldn't be interrupted
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@ -57,7 +55,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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input logic [LOGBWPL-1:0] BeatCount, // Beat in burst
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input logic [LINELEN-1:0] FetchBuffer, // Buffer long enough to hold entire cache line arriving from bus
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output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
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output logic [`PA_BITS-1:0] CacheBusAdr // Address for bus access
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output logic [PA_BITS-1:0] CacheBusAdr // Address for bus access
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);
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// Cache parameters
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@ -65,7 +63,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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localparam OFFSETLEN = $clog2(LINEBYTELEN); // Number of bits in offset field
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localparam SETLEN = $clog2(NUMLINES); // Number of set bits
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localparam SETTOP = SETLEN+OFFSETLEN; // Number of set plus offset bits
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localparam TAGLEN = `PA_BITS - SETTOP; // Number of tag bits
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localparam TAGLEN = PA_BITS - SETTOP; // Number of tag bits
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localparam CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
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localparam LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
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localparam FLUSHADRTHRESHOLD = NUMLINES - 1; // Used to determine when flush is complete
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@ -114,7 +112,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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AdrSelMuxSel, CacheSet);
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// Array of cache ways, along with victim, hit, dirty, and read merging logic
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
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cacheway #(PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
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.clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask,
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.SetValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
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@ -152,7 +150,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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.PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord);
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// Bus address for fetch, writeback, or flush writeback
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mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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mux3 #(PA_BITS) CacheBusAdrMux(.d0({PAdr[PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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.d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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.d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
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.s({SelFlush, SelWriteback}), .y(CacheBusAdr));
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16
src/cache/cacheway.sv
vendored
16
src/cache/cacheway.sv
vendored
@ -27,16 +27,14 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
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module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26,
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OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
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input logic clk,
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input logic reset,
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input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
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input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
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input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
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input logic [`PA_BITS-1:0] PAdr, // Physical address
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input logic [PA_BITS-1:0] PAdr, // Physical address
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input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only)
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input logic SetValid, // Set the valid bit in the selected way and set
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input logic SetDirty, // Set the dirty bit in the selected way and set
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@ -54,11 +52,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
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output logic DirtyWay, // This way is dirty
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output logic [TAGLEN-1:0] TagWay); // This way's tag if valid
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localparam WORDSPERLINE = LINELEN/`XLEN;
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localparam WORDSPERLINE = LINELEN/XLEN;
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localparam BYTESPERLINE = LINELEN/8;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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localparam LOGXLENBYTES = $clog2(`XLEN/8);
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localparam BYTESPERWORD = `XLEN/8;
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localparam LOGXLENBYTES = $clog2(XLEN/8);
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localparam BYTESPERWORD = XLEN/8;
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logic [NUMLINES-1:0] ValidBits;
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logic [NUMLINES-1:0] DirtyBits;
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@ -113,12 +111,12 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
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ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
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.addr(CacheSet), .dout(ReadTag),
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.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
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.din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
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// AND portion of distributed tag multiplexer
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assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux
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assign DirtyWay = SelTag & Dirty & ValidWay;
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assign HitWay = ValidWay & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
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assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Data Array
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@ -27,9 +27,10 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ahbcacheinterface #(
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parameter AHBW,
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parameter LLEN,
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parameter PA_BITS,
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parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
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parameter AHBWLOGBWPL, // Log2 of ^
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parameter LINELEN, // Number of bits in cacheline
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@ -44,14 +45,14 @@ module ahbcacheinterface #(
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output logic [2:0] HSIZE, // AHB transaction width
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output logic [2:0] HBURST, // AHB burst length
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// bus interface buses
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input logic [`AHBW-1:0] HRDATA, // AHB read data
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output logic [`PA_BITS-1:0] HADDR, // AHB address
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output logic [`AHBW-1:0] HWDATA, // AHB write data
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output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask
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input logic [AHBW-1:0] HRDATA, // AHB read data
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output logic [PA_BITS-1:0] HADDR, // AHB address
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output logic [AHBW-1:0] HWDATA, // AHB write data
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output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask
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// cache interface
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input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line
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input logic [`LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
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input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line
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input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
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input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
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input logic Cacheable, // Memory operation is cachable
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input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
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@ -61,8 +62,8 @@ module ahbcacheinterface #(
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output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
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// uncached interface
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input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
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input logic [`LLEN-1:0] WriteDataM, // IEU write data for uncached store
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input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
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input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store
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input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
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input logic [2:0] Funct3, // Size of uncached memory operation
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@ -74,11 +75,11 @@ module ahbcacheinterface #(
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localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
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logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
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logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
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logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
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logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
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logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
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logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
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logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
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logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data
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genvar index;
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@ -86,35 +87,35 @@ module ahbcacheinterface #(
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for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
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logic [BEATSPERLINE-1:0] CaptureBeat;
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assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
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flopen #(`AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
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.q(FetchBuffer[(index+1)*`AHBW-1:index*`AHBW]));
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flopen #(AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
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.q(FetchBuffer[(index+1)*AHBW-1:index*AHBW]));
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end
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mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
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assign HADDR = ({{`PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(`AHBW/8)) + LocalHADDR;
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mux2 #(PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
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assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR;
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mux2 #(3) sizemux(.d0(Funct3), .d1(`AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
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mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
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// When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
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logic [`AHBW-1:0] CacheReadDataWordAHB;
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logic [AHBW-1:0] CacheReadDataWordAHB;
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if(LLENPOVERAHBW > 1) begin
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logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0];
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logic [AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0];
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genvar index;
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for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
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assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)];
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assign AHBWordSets[index] = CacheReadDataWordM[(index*AHBW)+AHBW-1: (index*AHBW)];
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end
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assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
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end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];
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end else assign CacheReadDataWordAHB = CacheReadDataWordM[AHBW-1:0];
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mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
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mux2 #(AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[AHBW-1:0]),
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.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
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flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
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flopen #(AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
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// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
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// probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
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swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
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swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
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flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
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flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB);
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buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
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.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
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@ -30,6 +30,7 @@
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`include "wally-config.vh"
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module ahbinterface #(
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parameter XLEN,
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parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
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)(
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input logic HCLK, HRESETn,
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@ -27,7 +27,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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`define BURST_EN 1 // Enables burst mode. Disable to show the lost performance.
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// HCLK and clk must be the same clock!
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@ -27,8 +27,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module forward(
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// Detect hazards
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input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, // Source and destination registers
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@ -31,7 +31,7 @@
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`include "wally-config.vh"
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module decompress (
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module decompress #(parameter XLEN)(
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input logic [31:0] InstrRawD, // 32-bit instruction or raw compressed 16-bit instruction in bottom half
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output logic [31:0] InstrD, // Decompressed instruction
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output logic IllegalCompInstrD // Invalid decompressed instruction
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@ -214,7 +214,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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logic IROMce;
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assign IROMce = ~GatedStallD | reset;
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assign IFURWF = 2'b10;
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irom irom(.clk, .ce(IROMce), .Adr(PCSpillNextF[P.XLEN-1:0]), .IROMInstrF);
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irom #(P) irom(.clk, .ce(IROMce), .Adr(PCSpillNextF[P.XLEN-1:0]), .IROMInstrF);
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end else begin
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assign IFURWF = 2'b10;
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end
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@ -232,7 +232,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
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assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
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cache #(.LINELEN(P.ICACHE_LINELENINBITS),
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cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
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.NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
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.NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
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icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
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@ -249,7 +249,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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.NextSet(PCSpillNextF[11:0]),
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.PAdr(PCPF),
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.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
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ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1)
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ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1)
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ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
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.HRDATA,
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.Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
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@ -269,7 +269,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
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assign IFUHSIZE = 3'b010;
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ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY),
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ahbinterface #(P.XLEN, 0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY),
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.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
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.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
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.Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
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@ -351,7 +351,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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// expand 16-bit compressed instructions to 32 bits
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if (P.C_SUPPORTED) begin
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logic IllegalCompInstrD;
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decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
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decompress #(P.XLEN) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
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assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
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end else begin
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assign InstrD = InstrRawD;
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@ -24,27 +24,25 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module irom(
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module irom import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic ce, // Chip Enable. 0: Holds IROMInstrF constant
|
||||
input logic [`XLEN-1:0] Adr, // PCNextFSpill
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||||
input logic [P.XLEN-1:0] Adr, // PCNextFSpill
|
||||
output logic [31:0] IROMInstrF // Instruction read data
|
||||
);
|
||||
|
||||
localparam XLENBYTES = `XLEN/8;
|
||||
localparam ADDR_WDITH = $clog2(`IROM_RANGE/XLENBYTES);
|
||||
localparam XLENBYTES = {{P.PA_BITS-32{1'b0}}, P.XLEN/8}; // XLEN/8, adjusted for width
|
||||
localparam ADDR_WDITH = $clog2(P.IROM_RANGE[P.PA_BITS-1:0]/XLENBYTES);
|
||||
localparam OFFSET = $clog2(XLENBYTES);
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||||
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||||
logic [`XLEN-1:0] IROMInstrFFull;
|
||||
logic [P.XLEN-1:0] IROMInstrFFull;
|
||||
logic [31:0] RawIROMInstrF;
|
||||
|
||||
logic [1:0] AdrD;
|
||||
flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
|
||||
|
||||
rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
|
||||
if (`XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
|
||||
rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
|
||||
if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
|
||||
else begin
|
||||
// IROM is aligned to XLEN words, but instructions are 32 bits. Select between the two
|
||||
// haves. Adr is the Next PCF not PCF so we delay 1 cycle.
|
||||
|
||||
@ -263,7 +263,7 @@ module lsu (
|
||||
assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0;
|
||||
assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW);
|
||||
|
||||
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
|
||||
cache #(.PA_BITS(`PA_BITS), .XLEN(`XLEN), .LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
|
||||
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .READ_ONLY_CACHE(0)) dcache(
|
||||
.clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
|
||||
.FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM),
|
||||
@ -275,7 +275,7 @@ module lsu (
|
||||
.FetchBuffer, .CacheBusRW,
|
||||
.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
|
||||
|
||||
ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
|
||||
ahbcacheinterface #(.AHBW(`AHBW), .LLEN(`LLEN), .PA_BITS(`PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
|
||||
.HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
|
||||
.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
|
||||
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
|
||||
@ -300,7 +300,7 @@ module lsu (
|
||||
assign LSUHADDR = PAdrM;
|
||||
assign LSUHSIZE = LSUFunct3M;
|
||||
|
||||
ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
|
||||
ahbinterface #(`XLEN, 1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
|
||||
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
|
||||
.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
|
||||
.Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user