Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic.

src/ieu/controller.sv

@@ -62,7 +62,8 @@ module controller(
   output logic [2:0]  Funct3M,                 // Instruction's funct3 field
   output logic        RegWriteM,               // Instruction writes a register (needed for Hazard unit)
   output logic        InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
-  output logic        InstrValidM,             // Instruction is valid
+  output logic        InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
+
   output logic        FWriteIntM,              // FPU controller writes integer register file
   // Writeback stage control signals
   input  logic        StallW, FlushW,          // Stall, flush Writeback stage
@@ -96,7 +97,6 @@ module controller(
   logic        FenceXD;                        // Fence instruction
   logic        InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
   logic        CSRWriteD, CSRWriteE;           // CSR write
-  logic        InstrValidD, InstrValidE;       // Instruction is valid
   logic        PrivilegedD, PrivilegedE;       // Privileged instruction
   logic        InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
   logic [`CTRLW-1:0] ControlsD;                // Main Instruction Decoder control signals

src/ieu/ieu.sv

@@ -54,7 +54,7 @@ module ieu (
   output logic [4:0]        RdM,                             // Destination register
   input  logic [`XLEN-1:0]  FIntResM,                        // Integer result from FPU (fmv, fclass, fcmp)
   output logic              InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
-  output logic 		          InstrValidM,                     // Instruction is valid
+  output logic              InstrValidD, InstrValidE, InstrValidM,// Instruction is valid
   // Writeback stage signals
   input  logic [`XLEN-1:0]  FIntDivResultW,                  // Integer divide result from FPU fdivsqrt)
   input  logic [`XLEN-1:0]  CSRReadValW,                     // CSR read value, 
@@ -97,7 +97,7 @@ module ieu (
     .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, 
     .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
     .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
-    .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM,
+    .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
 
   datapath   dp(

src/ifu/bpred/bpred.sv

@@ -51,6 +51,7 @@ module bpred (
   input logic [31:0]       PostSpillInstrRawF,        // Instruction
 
   // Branch and jump outcome
+  input logic              InstrValidD, InstrValidE,
   input logic              PCSrcE,                    // Executation stage branch is taken
   input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
   input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
@@ -220,8 +221,8 @@ module bpred (
   assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
   assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
   
-  // Finally indicate if the branch predictor was wrong
-  assign BPPredWrongE = PredictionPCWrongE & (|InstrClassE | AnyWrongPredInstrClassE);
+  // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
+  assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
 
   // Output the predicted PC or corrected PC on miss-predict.
   // Selects the BP or PC+2/4.
@@ -236,7 +237,6 @@ module bpred (
   if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
   else	assign NextValidPCE = PCE;
 
-
   // performance counters
   // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)                    // Correct now
   // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)

src/ifu/ifu.sv

@@ -35,6 +35,7 @@ module ifu (
   // Command from CPU
   input  logic              InvalidateICacheM,                        // Clears all instruction cache valid bits
   input  logic         	    CSRWriteFenceM,                           // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
+  input  logic              InstrValidD, InstrValidE, InstrValidM,
 	// Bus interface
   output logic [`PA_BITS-1:0] IFUHADDR,      // Bus address from IFU to EBU
   input  logic [`XLEN-1:0] 	HRDATA,           // Bus read data from IFU to EBU
@@ -322,7 +323,7 @@ module ifu (
   if (`BPRED_SUPPORTED) begin : bpred
     bpred bpred(.clk, .reset,
                 .StallF, .StallD, .StallE, .StallM, .StallW,
-                .FlushD, .FlushE, .FlushM, .FlushW,
+                .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
                 .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
                 .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);

src/wally/wallypipelinedcore.sv

@@ -68,7 +68,7 @@ module wallypipelinedcore (
   logic [`XLEN-1:0]               CSRReadValW, MDUResultW;
   logic [`XLEN-1:0]               UnalignedPCNextF, PCNext2F;
   logic [1:0] 					 MemRWM;
-  logic 						 InstrValidM;
+  logic 						 InstrValidD, InstrValidE, InstrValidM;
   logic                          InstrMisalignedFaultM;
   logic                          IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
   logic                          InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
@@ -166,6 +166,7 @@ module wallypipelinedcore (
   // instruction fetch unit: PC, branch prediction, instruction cache
   ifu ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    .InstrValidM, .InstrValidE, .InstrValidD,
     // Fetch
     .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F,
     .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
@@ -201,7 +202,7 @@ module wallypipelinedcore (
      .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
      // Writeback stage
      .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
-     .InstrValidM, .FCvtIntResW, .FCvtIntW,
+     .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
      // hazards
      .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
      .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,