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https://github.com/openhwgroup/cvw
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Fixed formatting
This commit is contained in:
Harshini Srinath
GitHub
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acbbe7941a
@ -28,46 +28,46 @@
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module round import cvw::*; #(parameter cvw_t P) (
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input logic [P.FMTBITS-1:0] OutFmt, // output format
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input logic [2:0] Frm, // rounding mode
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input logic [1:0] PostProcSel, // select the postprocessor output
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input logic Ms, // normalized sign
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input logic [2:0] Frm, // rounding mode
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input logic [1:0] PostProcSel, // select the postprocessor output
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input logic Ms, // normalized sign
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input logic [P.CORRSHIFTSZ-1:0] Mf, // normalized fraction
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// fma
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input logic FmaOp, // is an fma opperation being done?
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input logic FmaOp, // is an fma opperation being done?
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input logic [P.NE+1:0] FmaMe, // exponent of the normalized sum for fma
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input logic FmaASticky, // addend's sticky bit
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input logic FmaASticky, // addend's sticky bit
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// divsqrt
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input logic DivOp, // is a division opperation being done
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input logic DivSticky, // divsqrt sticky bit
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input logic DivOp, // is a division opperation being done
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input logic DivSticky, // divsqrt sticky bit
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input logic [P.NE+1:0] Qe, // the divsqrt calculated expoent
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// cvt
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input logic CvtOp, // is a convert opperation being done
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input logic ToInt, // is the cvt op a cvt to integer
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input logic CvtResSubnormUf, // is the cvt result subnormal or underflow
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input logic CvtResUf, // does the cvt result underflow
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input logic CvtOp, // is a convert opperation being done
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input logic ToInt, // is the cvt op a cvt to integer
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input logic CvtResSubnormUf, // is the cvt result subnormal or underflow
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input logic CvtResUf, // does the cvt result underflow
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input logic [P.NE:0] CvtCe, // the cvt calculated expoent
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// outputs
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output logic [P.NE+1:0] Me, // normalied fraction
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output logic UfPlus1, // do you add one to the result if given an unbounded exponent
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output logic UfPlus1, // do you add one to the result if given an unbounded exponent
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output logic [P.NE+1:0] FullRe, // Re with bits to determine sign and overflow
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output logic [P.NE-1:0] Re, // Result exponent
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output logic [P.NF-1:0] Rf, // Result fractionNormS
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output logic Sticky, // sticky bit
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output logic Plus1, // do you add one to the final result
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output logic Round, Guard // bits needed to calculate rounding
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output logic Sticky, // sticky bit
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output logic Plus1, // do you add one to the final result
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output logic Round, Guard // bits needed to calculate rounding
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);
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logic UfCalcPlus1; // calculated plus one for unbounded exponent
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logic NormSticky; // normalized sum's sticky bit
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logic [P.NF-1:0] RoundFrac; // rounded fraction
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logic FpRes; // is the result a floating point
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logic IntRes; // is the result an integer
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logic FpGuard, FpRound; // floating point round/guard bits
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logic FpLsbRes; // least significant bit of floating point result
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logic LsbRes; // lsb of result
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logic CalcPlus1; // calculated plus1
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logic FpPlus1; // do you add one to the fp result
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logic [P.FLEN:0] RoundAdd; // how much to add to the result
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logic UfCalcPlus1; // calculated plus one for unbounded exponent
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logic NormSticky; // normalized sum's sticky bit
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logic [P.NF-1:0] RoundFrac; // rounded fraction
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logic FpRes; // is the result a floating point
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logic IntRes; // is the result an integer
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logic FpGuard, FpRound; // floating point round/guard bits
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logic FpLsbRes; // least significant bit of floating point result
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logic LsbRes; // lsb of result
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logic CalcPlus1; // calculated plus1
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logic FpPlus1; // do you add one to the fp result
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logic [P.FLEN:0] RoundAdd; // how much to add to the result
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// what position is XLEN in?
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// options:
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@ -86,7 +86,7 @@ module round import cvw::*; #(parameter cvw_t P) (
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// {Round, Sticky}
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// 0x - do nothing
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// 10 - tie - Plus1 if result is odd (LSBNormSum = 1)
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// - don't add 1 if a small number was supposed to be subtracted
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// - don't add 1 if a small number was supposed to be subtracted
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// 11 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number)
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// - plus 1 otherwise
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@ -104,14 +104,13 @@ module round import cvw::*; #(parameter cvw_t P) (
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// {Guard, Round, Sticky}
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// 0x - do nothing
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// 10 - tie - Plus1
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// - don't add 1 if a small number was supposed to be subtracted
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// - don't add 1 if a small number was supposed to be subtracted
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// 11 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number)
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// - Plus 1 otherwise
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// determine what format the final result is in: int or fp
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assign IntRes = ToInt;
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assign FpRes = ~IntRes;
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assign FpRes = ~IntRes;
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// sticky bit calculation
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if (P.FPSIZES == 1) begin
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@ -121,7 +120,7 @@ module round import cvw::*; #(parameter cvw_t P) (
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// | NF |1|1|
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// ^ ^ if floating point result
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// ^ if not an FMA result
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if (XLENPOS == 1)assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
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if (XLENPOS == 1)assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
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(|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
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// 2: NF > XLEN
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if (XLENPOS == 2)assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&IntRes) |
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@ -178,113 +177,104 @@ module round import cvw::*; #(parameter cvw_t P) (
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(|Mf[P.CORRSHIFTSZ-P.Q_NF-2:0]);
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end
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// only add the Addend sticky if doing an FMA opperation
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// - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits)
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assign Sticky = FmaASticky&FmaOp | NormSticky | CvtResUf&CvtOp | FmaMe[P.NE+1]&FmaOp | DivSticky&DivOp;
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// determine round and LSB of the rounded value
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// - underflow round bit is used to determint the underflow flag
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if (P.FPSIZES == 1) begin
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assign FpGuard = Mf[P.CORRSHIFTSZ-P.NF-1];
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assign FpGuard = Mf[P.CORRSHIFTSZ-P.NF-1];
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assign FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF];
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assign FpRound = Mf[P.CORRSHIFTSZ-P.NF-2];
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assign FpRound = Mf[P.CORRSHIFTSZ-P.NF-2];
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end else if (P.FPSIZES == 2) begin
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assign FpGuard = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-1] : Mf[P.CORRSHIFTSZ-P.NF1-1];
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assign FpGuard = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-1] : Mf[P.CORRSHIFTSZ-P.NF1-1];
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assign FpLsbRes = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF] : Mf[P.CORRSHIFTSZ-P.NF1];
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assign FpRound = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-2] : Mf[P.CORRSHIFTSZ-P.NF1-2];
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assign FpRound = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-2] : Mf[P.CORRSHIFTSZ-P.NF1-2];
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end else if (P.FPSIZES == 3) begin
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always_comb
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case (OutFmt)
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P.FMT: begin
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FpGuard = Mf[P.CORRSHIFTSZ-P.NF-1];
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FpGuard = Mf[P.CORRSHIFTSZ-P.NF-1];
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FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF];
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FpRound = Mf[P.CORRSHIFTSZ-P.NF-2];
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FpRound = Mf[P.CORRSHIFTSZ-P.NF-2];
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end
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P.FMT1: begin
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FpGuard = Mf[P.CORRSHIFTSZ-P.NF1-1];
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FpGuard = Mf[P.CORRSHIFTSZ-P.NF1-1];
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FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF1];
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FpRound = Mf[P.CORRSHIFTSZ-P.NF1-2];
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FpRound = Mf[P.CORRSHIFTSZ-P.NF1-2];
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end
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P.FMT2: begin
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FpGuard = Mf[P.CORRSHIFTSZ-P.NF2-1];
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FpGuard = Mf[P.CORRSHIFTSZ-P.NF2-1];
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FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF2];
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FpRound = Mf[P.CORRSHIFTSZ-P.NF2-2];
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FpRound = Mf[P.CORRSHIFTSZ-P.NF2-2];
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end
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default: begin
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FpGuard = 1'bx;
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FpGuard = 1'bx;
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FpLsbRes = 1'bx;
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FpRound = 1'bx;
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FpRound = 1'bx;
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end
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endcase
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end else if (P.FPSIZES == 4) begin
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always_comb
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case (OutFmt)
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2'h3: begin
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FpGuard = Mf[P.CORRSHIFTSZ-P.Q_NF-1];
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FpGuard = Mf[P.CORRSHIFTSZ-P.Q_NF-1];
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FpLsbRes = Mf[P.CORRSHIFTSZ-P.Q_NF];
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FpRound = Mf[P.CORRSHIFTSZ-P.Q_NF-2];
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FpRound = Mf[P.CORRSHIFTSZ-P.Q_NF-2];
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end
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2'h1: begin
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FpGuard = Mf[P.CORRSHIFTSZ-P.D_NF-1];
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FpGuard = Mf[P.CORRSHIFTSZ-P.D_NF-1];
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FpLsbRes = Mf[P.CORRSHIFTSZ-P.D_NF];
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FpRound = Mf[P.CORRSHIFTSZ-P.D_NF-2];
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FpRound = Mf[P.CORRSHIFTSZ-P.D_NF-2];
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end
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2'h0: begin
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FpGuard = Mf[P.CORRSHIFTSZ-P.S_NF-1];
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FpGuard = Mf[P.CORRSHIFTSZ-P.S_NF-1];
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FpLsbRes = Mf[P.CORRSHIFTSZ-P.S_NF];
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FpRound = Mf[P.CORRSHIFTSZ-P.S_NF-2];
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FpRound = Mf[P.CORRSHIFTSZ-P.S_NF-2];
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end
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2'h2: begin
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FpGuard = Mf[P.CORRSHIFTSZ-P.H_NF-1];
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FpGuard = Mf[P.CORRSHIFTSZ-P.H_NF-1];
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FpLsbRes = Mf[P.CORRSHIFTSZ-P.H_NF];
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FpRound = Mf[P.CORRSHIFTSZ-P.H_NF-2];
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FpRound = Mf[P.CORRSHIFTSZ-P.H_NF-2];
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end
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endcase
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end
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assign Guard = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN-1] : FpGuard;
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assign Guard = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN-1] : FpGuard;
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assign LsbRes = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN] : FpLsbRes;
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assign Round = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN-2] : FpRound;
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assign Round = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN-2] : FpRound;
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always_comb begin
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// Determine if you add 1
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case (Frm)
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3'b000: CalcPlus1 = Guard & (Round|Sticky|LsbRes);//round to nearest even
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3'b001: CalcPlus1 = 0;//round to zero
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3'b010: CalcPlus1 = Ms;//round down
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3'b011: CalcPlus1 = ~Ms;//round up
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3'b100: CalcPlus1 = Guard;//round to nearest max magnitude
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3'b000: CalcPlus1 = Guard & (Round|Sticky|LsbRes);//round to nearest even
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3'b001: CalcPlus1 = 0;//round to zero
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3'b010: CalcPlus1 = Ms;//round down
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3'b011: CalcPlus1 = ~Ms;//round up
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3'b100: CalcPlus1 = Guard;//round to nearest max magnitude
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default: CalcPlus1 = 1'bx;
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endcase
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// Determine if you add 1 (for underflow flag)
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case (Frm)
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3'b000: UfCalcPlus1 = Round & (Sticky|Guard);//round to nearest even
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3'b001: UfCalcPlus1 = 0;//round to zero
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3'b010: UfCalcPlus1 = Ms;//round down
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3'b011: UfCalcPlus1 = ~Ms;//round up
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3'b100: UfCalcPlus1 = Round;//round to nearest max magnitude
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3'b000: UfCalcPlus1 = Round & (Sticky|Guard);//round to nearest even
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3'b001: UfCalcPlus1 = 0;//round to zero
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3'b010: UfCalcPlus1 = Ms;//round down
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3'b011: UfCalcPlus1 = ~Ms;//round up
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3'b100: UfCalcPlus1 = Round;//round to nearest max magnitude
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default: UfCalcPlus1 = 1'bx;
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endcase
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end
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// If an answer is exact don't round
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assign Plus1 = CalcPlus1 & (Sticky|Round|Guard);
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assign Plus1 = CalcPlus1 & (Sticky|Round|Guard);
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assign FpPlus1 = Plus1&~(ToInt&CvtOp);
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assign UfPlus1 = UfCalcPlus1 & (Sticky|Round);
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// place Plus1 into the proper position for the format
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if (P.FPSIZES == 1) begin
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assign RoundAdd = {{P.FLEN{1'b0}}, FpPlus1};
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@ -302,21 +292,17 @@ module round import cvw::*; #(parameter cvw_t P) (
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end else if (P.FPSIZES == 4)
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assign RoundAdd = {(P.Q_NE+1+P.H_NF)'(0), FpPlus1&(OutFmt==P.H_FMT), (P.S_NF-P.H_NF-1)'(0), FpPlus1&(OutFmt==P.S_FMT), (P.D_NF-P.S_NF-1)'(0), FpPlus1&(OutFmt==P.D_FMT), (P.Q_NF-P.D_NF-1)'(0), FpPlus1&(OutFmt==P.Q_FMT)};
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// trim unneeded bits from fraction
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assign RoundFrac = Mf[P.CORRSHIFTSZ-1:P.CORRSHIFTSZ-P.NF];
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// select the exponent
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always_comb
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case(PostProcSel)
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2'b10: Me = FmaMe; // fma
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2'b00: Me = {CvtCe[P.NE], CvtCe}&{P.NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt
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2'b10: Me = FmaMe; // fma
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2'b00: Me = {CvtCe[P.NE], CvtCe}&{P.NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt
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// 2'b01: Me = DivDone ? Qe : '0; // divide
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2'b01: Me = Qe; // divide
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default: Me = '0;
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2'b01: Me = Qe; // divide
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default: Me = '0;
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endcase
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@ -324,7 +310,6 @@ module round import cvw::*; #(parameter cvw_t P) (
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// round the result
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// - if the fraction overflows one should be added to the exponent
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assign {FullRe, Rf} = {Me, RoundFrac} + RoundAdd;
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assign Re = FullRe[P.NE-1:0];
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assign Re = FullRe[P.NE-1:0];
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endmodule
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