Added N and PBMT bits to MMU PTE

config/buildroot/config.vh

@@ -47,6 +47,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 1;
 
 // LSU microarchitectural Features

config/fpga/config.vh

@@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 1;
 
 // LSU microarchitectural Features

config/rv32e/config.vh

@@ -48,6 +48,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
 
 // LSU microarchitectural Features

config/rv32gc/config.vh

@@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 1;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 1;
 
 // LSU microarchitectural Features

config/rv32i/config.vh

@@ -48,6 +48,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
 
 // LSU microarchitectural Features

config/rv32imc/config.vh

@@ -47,6 +47,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
 
 // LSU microarchitectural Features

config/rv64fpquad/config.vh

@@ -48,6 +48,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 1;
 
 // LSU microarchitectural Features

config/rv64gc/config.vh

@@ -51,6 +51,7 @@ localparam ZICBOM_SUPPORTED = 1;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 1;
 
 // LSU microarchitectural Features

config/rv64i/config.vh

@@ -48,6 +48,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
 
 // LSU microarchitectural Features

config/shared/config-shared.vh

@@ -101,10 +101,10 @@ localparam FPDUR       = ((DIVN+1+(LOGR*DIVCOPIES))/(LOGR*DIVCOPIES)+(RADIX/4));
 localparam DURLEN      = ($clog2(FPDUR+1));
 localparam DIVb        = (FPDUR*LOGR*DIVCOPIES-1); // canonical fdiv size (b)
 localparam DIVBLEN     = ($clog2(DIVb+1)-1);
-localparam DIVa        = (DIVb+1-XLEN); // used for idiv on fpu
+localparam DIVa        = (DIVb+1-XLEN); // used for idiv on fpu: Shift residual right by b - (XLEN-1) to put remainder in lsbs of integer result
 
 // largest length in IEU/FPU
-localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF));
+localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF));  // max(XLEN, NF)
 localparam LLEN = (($unsigned(FLEN)<$unsigned(XLEN)) ? ($unsigned(XLEN)) : ($unsigned(FLEN)));
 localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
 localparam NORMSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6)));

config/shared/parameter-defs.vh

@@ -25,6 +25,7 @@ parameter cvw_t P = '{
   ZICBOZ_SUPPORTED :     ZICBOZ_SUPPORTED,
   ZICBOP_SUPPORTED :     ZICBOP_SUPPORTED,
   SVPBMT_SUPPORTED :     SVPBMT_SUPPORTED,
+  SVNAPOT_SUPPORTED :    SVNAPOT_SUPPORTED,
   SVINVAL_SUPPORTED :    SVINVAL_SUPPORTED,
   BUS_SUPPORTED :        BUS_SUPPORTED,
   DCACHE_SUPPORTED :     DCACHE_SUPPORTED,

src/cvw.sv

@@ -60,6 +60,7 @@ typedef struct packed {
   logic         ZICBOZ_SUPPORTED;
   logic         ZICBOP_SUPPORTED;
   logic         SVPBMT_SUPPORTED;
+  logic         SVNAPOT_SUPPORTED;
   logic         SVINVAL_SUPPORTED;
 
   // Microarchitectural Features

src/mmu/tlb/tlb.sv

@@ -79,7 +79,7 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   logic [P.VPN_BITS-1:0]          VPN;
   logic [P.PPN_BITS-1:0]          PPN;
   // Sections of the page table entry
-  logic [7:0]                     PTEAccessBits;
+  logic [10:0]                    PTEAccessBits;
   logic [1:0]                     HitPageType;
   logic                           CAMHit;
   logic                           SV39Mode;

src/mmu/tlb/tlbcontrol.sv

@@ -29,27 +29,28 @@
 module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   input  logic [P.SVMODE_BITS-1:0] SATP_MODE,
   input  logic [P.XLEN-1:0]        VAdr,
-  input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-  input  logic [1:0]              STATUS_MPP,
-  input  logic [1:0]              PrivilegeModeW, // Current privilege level of the processeor
-  input  logic                    ReadAccess, WriteAccess,
-  input  logic                    DisableTranslation,
-  input  logic                    TLBFlush, // Invalidate all TLB entries
-  input  logic [7:0]              PTEAccessBits,
-  input  logic                    CAMHit,
-  input  logic                    Misaligned,
-  output logic                    TLBMiss,
-  output logic                    TLBHit,
-  output logic                    TLBPageFault,
-  output logic                    UpdateDA,
-  output logic                    SV39Mode,
-  output logic                    Translate
+  input  logic                     STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+  input  logic [1:0]               STATUS_MPP,
+  input  logic [1:0]               PrivilegeModeW, // Current privilege level of the processeor
+  input  logic                     ReadAccess, WriteAccess,
+  input  logic                     DisableTranslation,
+  input  logic                     TLBFlush, // Invalidate all TLB entries
+  input  logic [10:0]              PTEAccessBits,
+  input  logic                     CAMHit,
+  input  logic                     Misaligned,
+  output logic                     TLBMiss,
+  output logic                     TLBHit,
+  output logic                     TLBPageFault,
+  output logic                     UpdateDA,
+  output logic                     SV39Mode,
+  output logic                     Translate
 );
 
   // Sections of the page table entry
   logic [1:0]                     EffectivePrivilegeMode;
 
-  logic                           PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits
+  logic                           PTE_N, PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits
+  logic [1:0]                     PTE_PBMT;
   logic                           UpperBitsUnequal;
   logic                           TLBAccess;
   logic                           ImproperPrivilege;
@@ -65,6 +66,8 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   vm64check #(P) vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequal);
 
   // unswizzle useful PTE bits
+  assign PTE_N = PTEAccessBits[10] & P.SVNAPOT_SUPPORTED;
+  assign PTE_PBMT = PTEAccessBits[9:8] & {2{P.SVPBMT_SUPPORTED}};
   assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
   assign {PTE_U, PTE_X, PTE_W, PTE_R, PTE_V} = PTEAccessBits[4:0];
  

src/mmu/tlb/tlbram.sv

@@ -32,23 +32,23 @@
 module tlbram import cvw::*;  #(parameter cvw_t P, 
                                 parameter TLB_ENTRIES = 8) (
   input  logic                      clk, reset,
-  input  logic [P.XLEN-1:0]          PTE,
+  input  logic [P.XLEN-1:0]         PTE,
   input  logic [TLB_ENTRIES-1:0]    Matches, WriteEnables,
-  output logic [P.PPN_BITS-1:0]      PPN,
-  output logic [7:0]                PTEAccessBits,
+  output logic [P.PPN_BITS-1:0]     PPN,
+  output logic [10:0]               PTEAccessBits,
   output logic [TLB_ENTRIES-1:0]    PTE_Gs
 );
 
-  logic [P.PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0];
-  logic [P.PPN_BITS+9:0] PageTableEntry;
+  logic [P.XLEN-1:0] RamRead[TLB_ENTRIES-1:0]; // stores the page table entries
+  logic [P.XLEN-1:0] PageTableEntry;
 
   // RAM implemented with array of flops and AND/OR read logic
-  tlbramline #(P.PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0]
+  tlbramline #(P.XLEN) tlbramline[TLB_ENTRIES-1:0]
      (.clk, .reset, .re(Matches), .we(WriteEnables), 
-      .d(PTE[P.PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs));
-  or_rows #(TLB_ENTRIES, P.PPN_BITS+10) PTEOr(RamRead, PageTableEntry);
+      .d(PTE), .q(RamRead), .PTE_G(PTE_Gs));
+  or_rows #(TLB_ENTRIES, P.XLEN) PTEOr(RamRead, PageTableEntry);
 
   // Rename the bits read from the TLB RAM
-  assign PTEAccessBits = PageTableEntry[7:0];
+  assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-3], PageTableEntry[7:0]}; // include N and PBMT bits 
   assign PPN = PageTableEntry[P.PPN_BITS+9:10];
 endmodule

src/privileged/csrs.sv

@@ -90,7 +90,7 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
   assign WriteSTVALM      = STrapM | (CSRSWriteM & (CSRAdrM == STVAL));
   if(P.XLEN == 64) begin
     logic LegalSatpModeM;
-    assign LegalSatpModeM = P.VIRTMEM_SUPPORTED & (CSRWriteValM[63:60] == 0 | CSRWriteValM[63:60] == 8 | CSRWriteValM[63:60] == 9); // supports SV39 and 48
+    assign LegalSatpModeM = P.VIRTMEM_SUPPORTED & (CSRWriteValM[63:60] == 0 | CSRWriteValM[63:60] == P.SV39 | CSRWriteValM[63:60] == P.SV48); // supports SV39 and 48
     assign WriteSATPM     = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM) & LegalSatpModeM;
   end else  // RV32
     assign WriteSATPM     = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM) & P.VIRTMEM_SUPPORTED;

testbench/common/riscvassertions.sv

@@ -58,9 +58,11 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
     assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
     assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
     assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
-    assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOM required DCACHE_SUPPORTED");
-    assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOZ required DCACHE_SUPPORTED");
-    assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP required DCACHE_SUPPORTED");
+    assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOM requires DCACHE_SUPPORTED");
+    assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOZ requires DCACHE_SUPPORTED");
+    assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP requires DCACHE_SUPPORTED");
+    assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVPBMT requires VIRTMEM_SUPPORTED and RV64");
+    assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
   end
 
 endmodule