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https://github.com/openhwgroup/cvw
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Update lsu.sv
Program clean up
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Harshini Srinath
GitHub
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commit
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170
src/lsu/lsu.sv
170
src/lsu/lsu.sv
@ -30,63 +30,63 @@
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/////////////////////////////////////////////////////////////////////////////////////////////////////////
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module lsu import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
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// connected to cpu (controls)
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input logic [1:0] MemRWM, // Read/Write control
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [6:0] Funct7M, // Atomic memory operation function
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic FlushDCacheM, // Flush D cache to next level of memory
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic DCacheMiss, // D cache miss for performance counters
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output logic DCacheAccess, // D cache memory access for performance counters
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input logic [1:0] MemRWM, // Read/Write control
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [6:0] Funct7M, // Atomic memory operation function
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic FlushDCacheM, // Flush D cache to next level of memory
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic DCacheMiss, // D cache miss for performance counters
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output logic DCacheAccess, // D cache memory access for performance counters
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// address and write data
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input logic [P.XLEN-1:0] IEUAdrE, // Execution stage memory address
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output logic [P.XLEN-1:0] IEUAdrM, // Memory stage memory address
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input logic [P.XLEN-1:0] WriteDataM, // Write data from IEU
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output logic [P.LLEN-1:0] ReadDataW, // Read data to IEU or FPU
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input logic [P.XLEN-1:0] IEUAdrE, // Execution stage memory address
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output logic [P.XLEN-1:0] IEUAdrM, // Memory stage memory address
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input logic [P.XLEN-1:0] WriteDataM, // Write data from IEU
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output logic [P.LLEN-1:0] ReadDataW, // Read data to IEU or FPU
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// cpu privilege
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic BigEndianM, // Swap byte order to big endian
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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output logic DCacheStallM, // D$ busy with multicycle operation
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic BigEndianM, // Swap byte order to big endian
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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output logic DCacheStallM, // D$ busy with multicycle operation
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// fpu
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input logic [P.FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic FpLoadStoreM, // Selects FPU as store for write data
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input logic [P.FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic FpLoadStoreM, // Selects FPU as store for write data
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions
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output logic LoadMisalignedFaultM, // Load address misaligned fault
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output logic LoadAccessFaultM, // Load access fault (PMA)
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output logic HPTWInstrAccessFaultF, // HPTW generated access fault during instruction fetch
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output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions
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output logic LoadMisalignedFaultM, // Load address misaligned fault
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output logic LoadAccessFaultM, // Load access fault (PMA)
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output logic HPTWInstrAccessFaultF, // HPTW generated access fault during instruction fetch
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// cpu hazard unit (trap)
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output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
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output logic StoreAmoAccessFaultM, // Store or AMO access fault
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output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
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output logic StoreAmoAccessFaultM, // Store or AMO access fault
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// connect to ahb
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output logic [P.PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
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input logic [P.XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
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output logic [P.XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
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input logic LSUHREADY, // Bus ready from LSU to EBU
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output logic LSUHWRITE, // Bus write operation from LSU to EBU
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output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
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output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
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output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
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output logic [P.XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
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output logic [P.PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
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input logic [P.XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
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output logic [P.XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
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input logic LSUHREADY, // Bus ready from LSU to EBU
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output logic LSUHWRITE, // Bus write operation from LSU to EBU
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output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
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output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
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output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
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output logic [P.XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
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// page table walker
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input logic [P.XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
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input logic [1:0] STATUS_MPP, // Machine previous privilege mode
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input logic [P.XLEN-1:0] PCSpillF, // Fetch PC
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input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
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output logic [P.XLEN-1:0] PTE, // Page table entry write to ITLB
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output logic [1:0] PageType, // Type of page table entry to write to ITLB
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output logic ITLBWriteF, // Write PTE to ITLB
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output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE
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input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit
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input logic [P.XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
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input logic [1:0] STATUS_MPP, // Machine previous privilege mode
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input logic [P.XLEN-1:0] PCSpillF, // Fetch PC
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input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
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output logic [P.XLEN-1:0] PTE, // Page table entry write to ITLB
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output logic [1:0] PageType, // Type of page table entry to write to ITLB
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output logic ITLBWriteF, // Write PTE to ITLB
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output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE
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input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit
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);
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logic [P.XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
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@ -94,20 +94,20 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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logic [P.PA_BITS-1:0] PAdrM; // Physical memory address
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logic [P.XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address
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logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal
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logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC
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logic [2:0] LSUFunct3M; // IEU or HPTW memory operation size
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logic [6:0] LSUFunct7M; // AMO function gated by HPTW
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logic [1:0] LSUAtomicM; // AMO signal gated by HPTW
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logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal
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logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC
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logic [2:0] LSUFunct3M; // IEU or HPTW memory operation size
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logic [6:0] LSUFunct7M; // AMO function gated by HPTW
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logic [1:0] LSUAtomicM; // AMO signal gated by HPTW
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logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1
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logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1
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logic BusStall; // Bus interface busy with multicycle operation
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logic HPTWStall; // HPTW busy with multicycle operation
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logic BusStall; // Bus interface busy with multicycle operation
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logic HPTWStall; // HPTW busy with multicycle operation
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logic CacheableM; // PMA indicates memory address is cacheable
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logic BusCommittedM; // Bus memory operation in flight, delay interrupts
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logic DCacheCommittedM; // D$ memory operation started, delay interrupts
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logic CacheableM; // PMA indicates memory address is cacheable
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logic BusCommittedM; // Bus memory operation in flight, delay interrupts
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logic DCacheCommittedM; // D$ memory operation started, delay interrupts
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logic [P.LLEN-1:0] DTIMReadDataWordM; // DTIM read data
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logic [P.LLEN-1:0] DCacheReadDataWordM; // D$ read data
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@ -123,16 +123,15 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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logic [P.LLEN-1:0] LSUWriteDataM; // Final write data
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logic [(P.LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
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logic SelDTIM; // Select DTIM rather than bus or D$
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
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logic SelDTIM; // Select DTIM rather than bus or D$
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Pipeline for IEUAdr E to M
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// Zero-extend address to 34 bits for XLEN=32
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@ -222,7 +221,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if (P.DTIM_SUPPORTED) begin : dtim
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logic [P.PA_BITS-1:0] DTIMAdr;
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logic [1:0] DTIMMemRWM;
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logic [1:0] DTIMMemRWM;
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// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
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mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr);
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@ -237,23 +236,23 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if (P.BUS_SUPPORTED) begin : bus
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if(P.DCACHE_SUPPORTED) begin : dcache
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localparam LLENWORDSPERLINE = P.DCACHE_LINELENINBITS/P.LLEN; // Number of LLEN words in cacheline
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localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^
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localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^
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localparam BEATSPERLINE = P.DCACHE_LINELENINBITS/P.AHBW; // Number of AHBW words (beats) in cacheline
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localparam AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^
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localparam LINELEN = P.DCACHE_LINELENINBITS; // Number of bits in cacheline
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localparam AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^
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localparam LINELEN = P.DCACHE_LINELENINBITS; // Number of bits in cacheline
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localparam LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
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logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline
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logic [P.PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback.
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logic [AHBWLOGBWPL-1:0] BeatCount; // Position within a cacheline. ahbcacheinterface to cache
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logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback
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logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount
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logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface
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logic [1:0] BusRW; // Uncached bus memory access
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logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush
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logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11)
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logic [1:0] CacheAtomicM; // Cache AMO
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logic FlushDCache; // Suppress d cache flush if there is an ITLB miss.
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logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline
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logic [P.PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback.
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logic [AHBWLOGBWPL-1:0] BeatCount; // Position within a cacheline. ahbcacheinterface to cache
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logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback
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logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount
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logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface
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logic [1:0] BusRW; // Uncached bus memory access
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logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush
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logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11)
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logic [1:0] CacheAtomicM; // Cache AMO
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logic FlushDCache; // Suppress d cache flush if there is an ITLB miss.
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assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
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assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
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@ -320,6 +319,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Atomic operations
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/////////////////////////////////////////////////////////////////////////////////////////////
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if (P.A_SUPPORTED) begin:atomic
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atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM,
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.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
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@ -335,6 +335,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Subword Accesses
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/////////////////////////////////////////////////////////////////////////////////////////////
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subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
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@ -361,5 +362,4 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign LSUWriteDataM = LittleEndianWriteDataM;
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assign LittleEndianReadDataWordM = ReadDataWordMuxM;
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end
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endmodule
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