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https://github.com/openhwgroup/cvw
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Limnanthes Serafini
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53847269da
@ -38,27 +38,27 @@ module ahbcacheinterface #(
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)(
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input logic HCLK, HRESETn,
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// bus interface controls
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input logic HREADY, // AHB peripheral ready
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input logic HREADY, // AHB peripheral ready
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output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic HWRITE, // AHB 0: Read operation 1: Write operation
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output logic [2:0] HSIZE, // AHB transaction width
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output logic [2:0] HBURST, // AHB burst length
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// bus interface buses
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input logic [`AHBW-1:0] HRDATA, // AHB read data
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input logic [`AHBW-1:0] HRDATA, // AHB read data
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output logic [`PA_BITS-1:0] HADDR, // AHB address
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output logic [`AHBW-1:0] HWDATA, // AHB write data
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output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask
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// cache interface
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input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line
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input logic [`LLEN-1:0] CacheReadDataWordM, // one word of cache line during a writeback
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input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
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input logic Cacheable, // Memory operation is cachable
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input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
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output logic CacheBusAck, // Handshack to $ indicating bus transaction completed
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output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus
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output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
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output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
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input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line
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input logic [`LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
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input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
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input logic Cacheable, // Memory operation is cachable
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input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
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output logic CacheBusAck, // Handshake to $ indicating bus transaction completed
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output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus
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output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
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output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
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// uncached interface
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input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
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@ -77,7 +77,7 @@ module ahbcacheinterface #(
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logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
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logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
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logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
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logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
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logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
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logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
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genvar index;
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@ -107,7 +107,7 @@ module ahbcacheinterface #(
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end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];
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mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
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.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
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.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
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flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
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// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
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@ -119,5 +119,5 @@ module ahbcacheinterface #(
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buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
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.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
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.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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endmodule
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@ -32,21 +32,21 @@
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module ahbinterface #(
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parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
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)(
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input logic HCLK, HRESETn,
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input logic HCLK, HRESETn,
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// bus interface
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input logic HREADY, // AHB peripheral ready
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input logic HREADY, // AHB peripheral ready
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output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic HWRITE, // AHB 0: Read operation 1: Write operation
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input logic [`XLEN-1:0] HRDATA, // AHB read data
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input logic [`XLEN-1:0] HRDATA, // AHB read data
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output logic [`XLEN-1:0] HWDATA, // AHB write data
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output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask
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// lsu/ifu interface
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input logic Stall, // Core pipeline is stalled
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input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
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input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
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input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word
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input logic [`XLEN-1:0] WriteData, // IEU write data for a store
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input logic Stall, // Core pipeline is stalled
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input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
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input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
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input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word
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input logic [`XLEN-1:0] WriteData, // IEU write data for a store
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output logic BusStall, // Bus is busy with an in flight memory operation
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output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
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output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus
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@ -40,29 +40,29 @@ module buscachefsm #(
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input logic HRESETn,
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// IEU interface
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input logic Stall, // Core pipeline is stalled
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input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
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input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
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output logic BusStall, // Bus is busy with an in flight memory operation
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output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
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input logic Stall, // Core pipeline is stalled
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input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
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input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
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output logic BusStall, // Bus is busy with an in flight memory operation
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output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
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// ahb cache interface locals.
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output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA
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output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA
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// cache interface
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input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
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output logic CacheBusAck, // Handshack to $ indicating bus transaction completed
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input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
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output logic CacheBusAck, // Handshack to $ indicating bus transaction completed
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// lsu interface
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output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
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output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage
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output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
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output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
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// BUS interface
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input logic HREADY, // AHB peripheral ready
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output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic HWRITE, // AHB 0: Read operation 1: Write operation
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output logic [2:0] HBURST // AHB burst length
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input logic HREADY, // AHB peripheral ready
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output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic HWRITE, // AHB 0: Read operation 1: Write operation
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output logic [2:0] HBURST // AHB burst length
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);
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typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;
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@ -78,8 +78,8 @@ module buscachefsm #(
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logic CacheAccess;
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always_ff @(posedge HCLK)
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if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
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else CurrState <= #1 NextState;
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if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
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else CurrState <= #1 NextState;
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always_comb begin
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case(CurrState)
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// controller input stage
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// controllerinput.sv
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Created: August 31, 2022
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@ -36,26 +36,26 @@
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module controllerinput #(
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parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs
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)(
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input logic HCLK,
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input logic HRESETn,
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input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs
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input logic Restore, // Restore a saved manager inputs when it is finally granted
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input logic Disable, // Supress HREADY to the non-granted manager
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input logic HCLK,
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input logic HRESETn,
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input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs
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input logic Restore, // Restore a saved manager inputs when it is finally granted
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input logic Disable, // Suppress HREADY to the non-granted manager
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output logic Request, // This manager is making a request
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// controller input
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input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation
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input logic [2:0] HSIZEIn, // Manager input. AHB transaction width
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input logic [2:0] HBURSTIn, // Manager input. AHB burst length
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input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address
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output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority
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input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation
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input logic [2:0] HSIZEIn, // Manager input. AHB transaction width
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input logic [2:0] HBURSTIn, // Manager input. AHB burst length
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input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address
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output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
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// controller output
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output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation
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output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width
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output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length
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output logic [`PA_BITS-1:0] HADDROut, // Aribrated manager transaction. AHB address
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input logic HREADYIn // Peripherial ready
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output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation
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output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width
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output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length
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output logic [`PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address
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input logic HREADYIn // Peripheral ready
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);
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logic HWRITESave;
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// ebufsmarb
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// ebufsmarb.sv
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Created: 23 January 2023
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@ -55,7 +55,7 @@ module ebufsmarb (
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logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration
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logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst
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logic BeatCntEn;
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logic [3:0] BeatCount; // Position within a burst transfer
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logic [3:0] BeatCount; // Position within a burst transfer
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logic BeatCntReset;
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logic [3:0] Threshold; // Number of beats derived from HBURST
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@ -86,7 +86,7 @@ module ebufsmarb (
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// Controller 1 (LSU)
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// When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
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// Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining
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// priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request.
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// priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request.
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// This is necessary because the pipeline is stalled for the entire duration of both transactions,
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// and the LSU memory request will stil be active.
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flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD);
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// fdivsqrtpreproc.sv
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// fdivsqrtexpcalc.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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@ -30,11 +30,11 @@
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module fdivsqrtexpcalc(
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input logic [`FMTBITS-1:0] Fmt,
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input logic [`NE-1:0] Xe, Ye,
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input logic Sqrt,
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input logic XZero,
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input logic [`DIVBLEN:0] ell, m,
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output logic [`NE+1:0] Qe
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input logic [`NE-1:0] Xe, Ye,
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input logic Sqrt,
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input logic XZero,
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input logic [`DIVBLEN:0] ell, m,
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output logic [`NE+1:0] Qe
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);
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logic [`NE-2:0] Bias;
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logic [`NE+1:0] SXExp;
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@ -42,28 +42,28 @@ module fdivsqrtexpcalc(
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logic [`NE+1:0] DExp;
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if (`FPSIZES == 1) begin
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assign Bias = (`NE-1)'(`BIAS);
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assign Bias = (`NE-1)'(`BIAS);
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end else if (`FPSIZES == 2) begin
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assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1);
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assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1);
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end else if (`FPSIZES == 3) begin
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always_comb
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case (Fmt)
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`FMT: Bias = (`NE-1)'(`BIAS);
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`FMT1: Bias = (`NE-1)'(`BIAS1);
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`FMT2: Bias = (`NE-1)'(`BIAS2);
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default: Bias = 'x;
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endcase
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always_comb
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case (Fmt)
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`FMT: Bias = (`NE-1)'(`BIAS);
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`FMT1: Bias = (`NE-1)'(`BIAS1);
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`FMT2: Bias = (`NE-1)'(`BIAS2);
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default: Bias = 'x;
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endcase
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end else if (`FPSIZES == 4) begin
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always_comb
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case (Fmt)
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2'h3: Bias = (`NE-1)'(`Q_BIAS);
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2'h1: Bias = (`NE-1)'(`D_BIAS);
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2'h0: Bias = (`NE-1)'(`S_BIAS);
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2'h2: Bias = (`NE-1)'(`H_BIAS);
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endcase
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always_comb
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case (Fmt)
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2'h3: Bias = (`NE-1)'(`Q_BIAS);
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2'h1: Bias = (`NE-1)'(`D_BIAS);
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2'h0: Bias = (`NE-1)'(`S_BIAS);
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2'h2: Bias = (`NE-1)'(`H_BIAS);
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endcase
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end
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assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
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assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
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