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Zero/Sign extend mux in Shifter, Zero extend mux in Bitmanip alu

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This commit is contained in:
Kevin Kim 2023-03-24 11:52:51 -07:00
parent 6640e9956b
commit b70ab0fa5a
3 changed files with 28 additions and 33 deletions
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11
src/ieu/alu.sv
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@ -52,19 +52,12 @@ module alu #(parameter WIDTH=32) (
logic LT, LTU; // Less than, Less than unsigned
logic Asign, Bsign; // Sign bits of A, B
// *** explain this part better; possibly move into shifter and BMU?
if (WIDTH == 64) begin
mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
end else begin
assign CondExtA = A;
end
// Addition
assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
// Shifts (configurable for rotation)
shifter sh(.A(CondExtA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
// Condition code flags are based on subtraction output Sum = A-B.
// Overflow occurs when the numbers being subtracted have the opposite sign
@ -97,7 +90,7 @@ module alu #(parameter WIDTH=32) (
// Final Result B instruction select mux
if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
.Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult,
.Funct3, .CompFlags, .BALUControl, .ALUResult, .FullResult,
.CondMaskB, .CondShiftA, .Result);
end else begin
assign Result = ALUResult;

7
src/ieu/bmu/bitmanipalu.sv
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@ -37,7 +37,6 @@ module bitmanipalu #(parameter WIDTH=32) (
input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
input logic [1:0] CompFlags, // Comparator flags
input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
input logic [WIDTH-1:0] CondExtA, // A Conditional Extend Intermediary Signal
input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals
output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions
@ -50,6 +49,7 @@ module bitmanipalu #(parameter WIDTH=32) (
logic Mask; // Indicates if it is ZBS instruction
logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction
logic [1:0] PreShiftAmt; // Amount to Pre-Shift A
logic [WIDTH-1:0] CondZextA; // A Conditional Extend Intermediary Signal
// Extract control signals from bitmanip ALUControl.
assign {Mask, PreShift} = BALUControl[1:0];
@ -62,8 +62,11 @@ module bitmanipalu #(parameter WIDTH=32) (
// 0-3 bit Pre-Shift Mux
if (`ZBA_SUPPORTED) begin: zbapreshift
if (WIDTH == 64) begin
mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA);
end else assign CondZextA = A;
assign PreShiftAmt = Funct3[2:1] & {2{PreShift}};
assign CondShiftA = CondExtA << (PreShiftAmt);
assign CondShiftA = CondZextA << (PreShiftAmt);
end else begin
assign PreShiftAmt = 2'b0;
assign CondShiftA = A;

43
src/ieu/shifter.sv
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@ -40,42 +40,41 @@ module shifter (
logic Sign; // Sign bit for sign extension
assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension
if (`ZBB_SUPPORTED) begin: rotfunnel
if (`XLEN==32) begin // rv32 with rotates
if (`XLEN==32) begin // rv32
if (`ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
always_comb // funnel mux
case({Right, Rotate})
2'b00: z = {A[31:0], 31'b0};
2'b01: z = {A[31:0], A[31:1]};
2'b10: z = {{31{Sign}}, A[31:0]};
2'b11: z = {A[30:0], A};
2'b11: z = {A[30:0], A[31:0]};
endcase
assign amttrunc = Amt; // shift amount
end else begin // rv64 with rotates
end else begin: norotfunnel32 //rv32 shifter without rotates
always_comb // funnel mux
if (Right) z = {{31{Sign}}, A[31:0]};
else z = {A[31:0], 31'b0};
end
assign amttrunc = Amt; // shift amount
end else begin // rv64
logic [`XLEN-1:0] A64;
mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
if (`ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
// shifter rotate source select mux
logic [`XLEN-1:0] RotA; // rotate source
mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
always_comb // funnel mux
case ({Right, Rotate})
2'b00: z = {A[63:0],{63'b0}};
2'b01: z = {RotA, RotA[63:1]};
2'b10: z = {{63{Sign}}, A[63:0]};
2'b11: z = {RotA[62:0], RotA};
2'b00: z = {A64[63:0],{63'b0}};
2'b01: z = {RotA[63:0], RotA[63:1]};
2'b10: z = {{63{Sign}}, A64[63:0]};
2'b11: z = {RotA[62:0], RotA[63:0]};
endcase
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
end
end else begin: norotfunnel
if (`XLEN==32) begin:shifter // RV32
end else begin: norotfunnel64 // rv64 shifter without rotates
always_comb // funnel mux
if (Right) z = {{31{Sign}}, A[31:0]};
else z = {A[31:0], 31'b0};
assign amttrunc = Amt; // shift amount
end else begin:shifter // RV64
always_comb // funnel mux
if (Right) z = {{63{Sign}}, A[63:0]};
else z = {A[63:0], {63'b0}};
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
if (Right) z = {{63{Sign}}, A64[63:0]};
else z = {A64[63:0], {63'b0}};
end
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
end
// Opposite offset for right shifts