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Renamed intdivrestoring to div
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David Harris
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718844012e
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df9ce03252
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///////////////////////////////////////////
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// intdivrestoring.sv
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//
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// Written: David_Harris@hmc.edu 12 September 2021
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// Modified:
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//
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// Purpose: Restoring integer division using a shift register and subtractor
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//
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// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module intdivrestoring(
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input logic clk,
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input logic reset,
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input logic StallM,
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input logic FlushE,
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input logic IntDivE, // integer division/remainder instruction of any type
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input logic DivSignedE, // signed division
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input logic W64E, // W-type instructions (divw, divuw, remw, remuw)
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Forwarding mux outputs for Source A and B
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output logic DivBusyE, // Divide is busy - stall pipeline
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output logic [`XLEN-1:0] QuotM, RemM // Quotient and remainder outputs
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);
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localparam STEPBITS = $clog2(`XLEN/`IDIV_BITSPERCYCLE); // Number of steps
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typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype; // division FSM state
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statetype state;
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logic [`XLEN-1:0] W[`IDIV_BITSPERCYCLE:0]; // Residual for each of k steps
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logic [`XLEN-1:0] XQ[`IDIV_BITSPERCYCLE:0]; // dividend/quotient for each of k steps
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logic [`XLEN-1:0] WNext, XQNext; // initialized W and XQ going into registers
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logic [`XLEN-1:0] DinE, XinE; // divisor & dividend, possibly truncated to 32 bits
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logic [`XLEN-1:0] DnE; // DnE = ~DinE
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logic [`XLEN-1:0] DAbsBE; // absolute value of D
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logic [`XLEN-1:0] DAbsB; // registered absolute value of D, constant during division
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logic [`XLEN-1:0] XnE; // DXnE = ~XinE
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logic [`XLEN-1:0] XInitE; // |X|, or original X for divide by 0
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logic [`XLEN-1:0] WnM, XQnM; // negated residual W and quotient XQ for postprocessing sign correction
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logic [STEPBITS:0] step; // division step
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logic Div0E, Div0M; // divide by 0
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logic DivStartE; // start integer division
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logic SignXE, SignDE; // sign of dividend and divisor
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logic NegQE, NegWM, NegQM; // negate quotient or residual during postprocessing
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//////////////////////////////
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// Execute Stage: prepare for division calculation with control logic, W logic and absolute values, initialize W and XQ
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//////////////////////////////
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// Divider control signals
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assign DivStartE = IntDivE & (state == IDLE) & ~StallM;
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assign DivBusyE = (state == BUSY) | DivStartE;
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// Handle sign extension for W-type instructions
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if (`XLEN == 64) begin:rv64 // RV64 has W-type instructions
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mux2 #(`XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE);
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mux2 #(`XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE);
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end else begin // RV32 has no W-type instructions
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assign XinE = ForwardedSrcAE;
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assign DinE = ForwardedSrcBE;
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end
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// Extract sign bits and check fo division by zero
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assign SignDE = DivSignedE & DinE[`XLEN-1];
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assign SignXE = DivSignedE & XinE[`XLEN-1];
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assign NegQE = SignDE ^ SignXE;
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assign Div0E = (DinE == 0);
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// Take absolute value for signed operations, and negate D to handle subtraction in divider stages
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neg #(`XLEN) negd(DinE, DnE);
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mux2 #(`XLEN) dabsmux(DnE, DinE, SignDE, DAbsBE); // take absolute value for signed operations, and negate for subtraction setp
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neg #(`XLEN) negx(XinE, XnE);
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mux3 #(`XLEN) xabsmux(XinE, XnE, ForwardedSrcAE, {Div0E, SignXE}, XInitE); // take absolute value for signed operations, or keep original value for divide by 0
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//////////////////////////////
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// Division Iterations (effectively stalled execute stage, no suffix)
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//////////////////////////////
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// initialization multiplexers on first cycle of operation
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mux2 #(`XLEN) wmux(W[`IDIV_BITSPERCYCLE], {`XLEN{1'b0}}, DivStartE, WNext);
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mux2 #(`XLEN) xmux(XQ[`IDIV_BITSPERCYCLE], XInitE, DivStartE, XQNext);
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// registers before division steps
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flopen #(`XLEN) wreg(clk, DivBusyE, WNext, W[0]);
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flopen #(`XLEN) xreg(clk, DivBusyE, XQNext, XQ[0]);
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flopen #(`XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsB);
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// one copy of divstep for each bit produced per cycle
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genvar i;
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for (i=0; i<`IDIV_BITSPERCYCLE; i = i+1)
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intdivrestoringstep divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
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//////////////////////////////
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// Memory Stage: output sign correction and special cases
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//////////////////////////////
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flopen #(3) Div0eMReg(clk, DivStartE, {Div0E, NegQE, SignXE}, {Div0M, NegQM, NegWM});
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// On final setp of signed operations, negate outputs as needed to get correct sign
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neg #(`XLEN) qneg(XQ[0], XQnM);
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neg #(`XLEN) wneg(W[0], WnM);
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// Select appropriate output: normal, negated, or for divide by zero
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mux3 #(`XLEN) qmux(XQ[0], XQnM, {`XLEN{1'b1}}, {Div0M, NegQM}, QuotM); // Q taken from XQ register, negated if necessary, or all 1s when dividing by zero
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mux3 #(`XLEN) remmux(W[0], WnM, XQ[0], {Div0M, NegWM}, RemM); // REM taken from W register, negated if necessary, or from X when dividing by zero
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//////////////////////////////
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// Divider FSM to sequence Busy and Done
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//////////////////////////////
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always_ff @(posedge clk)
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if (reset | FlushE) begin
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state <= IDLE;
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end else if (DivStartE) begin
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step <= 1;
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if (Div0E) state <= DONE;
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else state <= BUSY;
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end else if (state == BUSY) begin // pause one cycle at beginning of signed operations for absolute value
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if (step[STEPBITS] | (`XLEN==64) & W64E & step[STEPBITS-1]) begin // complete in half the time for W-type instructions
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state <= DONE;
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end
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step <= step + 1;
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end else if (state == DONE) begin
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if (StallM) state <= DONE;
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else state <= IDLE;
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end
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endmodule
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@ -1,51 +0,0 @@
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///////////////////////////////////////////
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// intdivrestoringstep.sv
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//
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// Written: David_Harris@hmc.edu 2 October 2021
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// Modified:
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//
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// Purpose: Restoring integer division step. k steps are used in intdivrestoring
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//
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// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_off UNOPTFLAT */
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module intdivrestoringstep(
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input logic [`XLEN-1:0] W, // Residual in
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input logic [`XLEN-1:0] XQ, // bits of dividend X and quotient Q in
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input logic [`XLEN-1:0] DAbsB, // complement of absolute value of divisor D (for subtraction)
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output logic [`XLEN-1:0] WOut, // Residual out
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output logic [`XLEN-1:0] XQOut // bits of dividend and quotient out: discard one bit of X, append one bit of Q
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);
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logic [`XLEN-1:0] WShift; // Shift W left by one bit, bringing in most significant bit of X
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logic [`XLEN-1:0] WPrime; // WShift - D, for comparison and possible result
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logic qi, qib; // Quotient digit and its complement
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assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi}; // shift W and X/Q left, insert quotient bit at bottom
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adder #(`XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime}); // effective subtractor, carry out determines quotient bit
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assign qi = ~qib;
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mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
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endmodule
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/* verilator lint_on UNOPTFLAT */
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