Sydeny 17d41b4d52 Merge branch 'main' of https://github.com/openhwgroup/cvw into main		2023-04-03 01:54:27 -07:00
..
cache	Possible fix for issue 148.	2023-03-28 14:47:08 -05:00
ebu	Possible fix for issue 148.	2023-03-28 14:47:08 -05:00
fpu	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2023-04-03 01:54:27 -07:00
generic	Fixed all tap/space issue in RTL.	2023-03-24 17:32:25 -05:00
hazard	Book updates.	2023-03-14 13:09:50 -05:00
ieu	only pass in relevant comparator flag to ALU	2023-03-30 19:15:33 -07:00
ifu	expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions.	2023-04-02 23:51:34 -07:00
lsu	Possible fix for issue 148.	2023-03-28 14:47:08 -05:00
mdu	Fixed all tap/space issue in RTL.	2023-03-24 17:32:25 -05:00
mmu	Fixed RV32 tests after PMP fix	2023-03-28 08:35:23 -07:00
privileged	Refactored InstrValidNotFlushed into CSR Write signals	2023-03-30 17:06:09 -07:00
uncore	Modified plic and uart to remove async reset. This removes vivado critical warning.	2023-03-24 20:37:48 -05:00
wally	Updated GPIO signal names to reflect book.	2023-03-24 18:55:43 -05:00