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https://github.com/openhwgroup/cvw
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Cleanup parameterization for verilator 5.010.
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@ -28,7 +28,8 @@
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`define RAM_LATENCY 0
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module ram_ahb import cvw::*; #(parameter cvw_t P, BASE=0, RANGE = 65535) (
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module ram_ahb import cvw::*; #(parameter cvw_t P,
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parameter BASE=0, RANGE = 65535) (
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input logic HCLK, HRESETn,
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input logic HSELRam,
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input logic [P.PA_BITS-1:0] HADDR,
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@ -26,7 +26,8 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rom_ahb import cvw::*; #(parameter cvw_t P, BASE=0, RANGE = 65535) (
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module rom_ahb import cvw::*; #(parameter cvw_t P,
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parameter BASE=0, RANGE = 65535) (
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input logic HCLK, HRESETn,
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input logic HSELRom,
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input logic [P.PA_BITS-1:0] HADDR,
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