Ross Thompson 42e6364b3d Merge branch 'main' of github.com:ross144/cvw		2023-07-17 15:52:27 -05:00
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cache	Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.	2023-07-14 16:31:44 -05:00
ebu	Update controllerinput.sv	2023-06-10 18:26:06 -07:00
fpu	RTL changes for Xcelium.	2023-07-11 10:51:02 -05:00
generic	Updated the FPGA zero stage bootloader.	2023-07-17 15:52:13 -05:00
hazard	MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.	2023-05-24 15:01:35 -05:00
ieu	Fixed the privilege decoder bug which prevented the fpga linux boot.	2023-07-10 17:00:06 -05:00
ifu	Merge branch 'testbench-params2'	2023-06-15 15:31:13 -05:00
lsu	Added prefetch instructions; sent cbo instructions to LSU	2023-07-02 10:55:35 -07:00
mdu	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 15:38:38 -05:00
mmu	RTL changes for Xcelium.	2023-07-11 10:51:02 -05:00
privileged	Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.	2023-07-14 16:31:44 -05:00
uncore	Updated comments.	2023-07-06 15:24:26 -05:00
wally	Added prefetch instructions; sent cbo instructions to LSU	2023-07-02 10:55:35 -07:00
cvw.sv	Clean up privilege rs1 decoding and implement svinval as sfence.vma	2023-07-13 02:41:17 -07:00