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https://github.com/openhwgroup/cvw
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Partial improvement.
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@ -220,9 +220,7 @@ module bpred (
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end else begin
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assign PredInstrClassF = BTBPredInstrClassF;
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assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) |
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PredInstrClassF[2] |
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(PredInstrClassF[1] & PredValidF) |
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(PredInstrClassF[3] & PredValidF);
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PredInstrClassF[1] & PredValidF;
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end
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// Part 3 RAS
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@ -232,17 +230,18 @@ module bpred (
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assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
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/* -----\/----- EXCLUDED -----\/-----
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assign InstrClassD[0] = BranchD;
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assign InstrClassD[1] = JumpD ;
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assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5
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assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
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assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
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assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
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(InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
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assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
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-----/\----- EXCLUDED -----/\----- */
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@ -274,7 +273,7 @@ module bpred (
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assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
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// branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
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assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | (AnyWrongPredInstrClassE & ~|InstrClassE);
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assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE));
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//assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
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// Output the predicted PC or corrected PC on miss-predict.
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