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Fixed formatting

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Harshini Srinath 2023-07-30 18:00:39 -07:00 committed by GitHub
parent 41555b149e
commit 1badc8a8c5
1 changed files with 7 additions and 7 deletions
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14
src/fpu/postproc/negateintres.sv
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@ -27,20 +27,20 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module negateintres import cvw::*; #(parameter cvw_t P) (
input logic Signed, // is the integer input signed
input logic Int64, // is the integer input 64-bits
input logic Plus1, // should one be added for rounding?
input logic Xs, // X sign
input logic Signed, // is the integer input signed
input logic Int64, // is the integer input 64-bits
input logic Plus1, // should one be added for rounding?
input logic Xs, // X sign
input logic [P.NORMSHIFTSZ-1:0] Shifted, // output from normalization shifter
output logic [1:0] CvtNegResMsbs, // most signigficant bits of possibly negated result
output logic [1:0] CvtNegResMsbs, // most signigficant bits of possibly negated result
output logic [P.XLEN+1:0] CvtNegRes // possibly negated integer result
);
logic [P.XLEN+1:0] CvtPreRes; // integer result with rounding
logic [2:0] CvtNegResMsbs3; // first three msbs of possibly negated result
logic [2:0] CvtNegResMsbs3; // first three msbs of possibly negated result
// round and negate the positive res if needed
assign CvtPreRes = {2'b0, Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.XLEN]}+{{P.XLEN+1{1'b0}}, Plus1};
assign CvtPreRes = {2'b0, Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.XLEN]}+{{P.XLEN+1{1'b0}}, Plus1};
mux2 #(P.XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
// select 2 most significant bits