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https://github.com/openhwgroup/cvw
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Update privileged.sv
Program clean up
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Harshini Srinath
GitHub
parent
d2a41a6422
commit
63a7649179
@ -28,91 +28,90 @@
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///////////////////////////////////////////
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module privileged import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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input logic clk, reset,
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input logic StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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// CSR Reads and Writes, and values needed for traps
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input logic CSRReadM, CSRWriteM, // Read or write CSRs
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input logic CSRReadM, CSRWriteM, // Read or write CSRs
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input logic [P.XLEN-1:0] SrcAM, // GPR register to write
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input logic [31:0] InstrM, // Instruction
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input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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input logic [31:0] InstrM, // Instruction
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input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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input logic [P.XLEN-1:0] IEUAdrM, // address from IEU
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input logic [P.XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return PC logic
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// control signals
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input logic InstrValidM, // Current instruction is valid (not flushed)
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input logic CommittedM, CommittedF, // current instruction is using bus; don't interrupt
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input logic PrivilegedM, // privileged instruction
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input logic InstrValidM, // Current instruction is valid (not flushed)
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input logic CommittedM, CommittedF, // current instruction is using bus; don't interrupt
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input logic PrivilegedM, // privileged instruction
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// processor events for performance counter logging
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input logic FRegWriteM, // instruction will write floating-point registers
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input logic LoadStallD, // load instruction is stalling
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input logic StoreStallD, // store instruction is stalling
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input logic ICacheStallF, // I cache stalled
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input logic DCacheStallM, // D cache stalled
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input logic BPDirPredWrongM, // branch predictor guessed wrong direction
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input logic BTAWrongM, // branch predictor guessed wrong target
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input logic RASPredPCWrongM, // return adddress stack guessed wrong target
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input logic IClassWrongM, // branch predictor guessed wrong instruction class
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input logic BPWrongM, // branch predictor is wrong
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input logic [3:0] InstrClassM, // actual instruction class
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input logic DCacheMiss, // data cache miss
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input logic DCacheAccess, // data cache accessed (hit or miss)
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input logic ICacheMiss, // instruction cache miss
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input logic ICacheAccess, // instruction cache access
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input logic DivBusyE, // integer divide busy
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input logic FDivBusyE, // floating point divide busy
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input logic FRegWriteM, // instruction will write floating-point registers
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input logic LoadStallD, // load instruction is stalling
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input logic StoreStallD, // store instruction is stalling
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input logic ICacheStallF, // I cache stalled
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input logic DCacheStallM, // D cache stalled
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input logic BPDirPredWrongM, // branch predictor guessed wrong direction
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input logic BTAWrongM, // branch predictor guessed wrong target
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input logic RASPredPCWrongM, // return adddress stack guessed wrong target
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input logic IClassWrongM, // branch predictor guessed wrong instruction class
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input logic BPWrongM, // branch predictor is wrong
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input logic [3:0] InstrClassM, // actual instruction class
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input logic DCacheMiss, // data cache miss
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input logic DCacheAccess, // data cache accessed (hit or miss)
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input logic ICacheMiss, // instruction cache miss
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input logic ICacheAccess, // instruction cache access
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input logic DivBusyE, // integer divide busy
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input logic FDivBusyE, // floating point divide busy
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// fault sources
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input logic InstrAccessFaultF, // instruction access fault
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input logic LoadAccessFaultM, StoreAmoAccessFaultM, // load or store access fault
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input logic HPTWInstrAccessFaultF, // hardware page table access fault while fetching instruction PTE
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input logic InstrPageFaultF, // page faults
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input logic LoadPageFaultM, StoreAmoPageFaultM, // page faults
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input logic InstrMisalignedFaultM, // misaligned instruction fault
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input logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned data fault
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input logic IllegalIEUFPUInstrD, // illegal instruction from IEU or FPU
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input logic MTimerInt, MExtInt, SExtInt, MSwInt, // interrupt sources
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input logic [63:0] MTIME_CLINT, // timer value from CLINT
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input logic [4:0] SetFflagsM, // set FCSR flags from FPU
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input logic SelHPTW, // HPTW in use. Causes system to use S-mode endianness for accesses
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input logic InstrAccessFaultF, // instruction access fault
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input logic LoadAccessFaultM, StoreAmoAccessFaultM, // load or store access fault
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input logic HPTWInstrAccessFaultF, // hardware page table access fault while fetching instruction PTE
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input logic InstrPageFaultF, // page faults
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input logic LoadPageFaultM, StoreAmoPageFaultM, // page faults
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input logic InstrMisalignedFaultM, // misaligned instruction fault
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input logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned data fault
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input logic IllegalIEUFPUInstrD, // illegal instruction from IEU or FPU
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input logic MTimerInt, MExtInt, SExtInt, MSwInt, // interrupt sources
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input logic [63:0] MTIME_CLINT, // timer value from CLINT
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input logic [4:0] SetFflagsM, // set FCSR flags from FPU
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input logic SelHPTW, // HPTW in use. Causes system to use S-mode endianness for accesses
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// CSR outputs
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output logic [P.XLEN-1:0] CSRReadValW, // Value read from CSR
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output logic [1:0] PrivilegeModeW, // current privilege mode
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output logic [1:0] PrivilegeModeW, // current privilege mode
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output logic [P.XLEN-1:0] SATP_REGW, // supervisor address translation register
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // status register bits
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output logic [1:0] STATUS_MPP, STATUS_FS, // status register bits
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output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration entries to MMU
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output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0], // PMP address entries to MMU
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output logic [2:0] FRM_REGW, // FPU rounding mode
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // status register bits
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output logic [1:0] STATUS_MPP, STATUS_FS, // status register bits
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output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration entries to MMU
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output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0], // PMP address entries to MMU
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output logic [2:0] FRM_REGW, // FPU rounding mode
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// PC logic output in privileged unit
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output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic
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// control outputs
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output logic RetM, TrapM, // return instruction, or trap
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output logic sfencevmaM, // sfence.vma instruction
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input logic InvalidateICacheM, // fence instruction
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output logic BigEndianM, // Use big endian in current privilege mode
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output logic RetM, TrapM, // return instruction, or trap
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output logic sfencevmaM, // sfence.vma instruction
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input logic InvalidateICacheM, // fence instruction
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output logic BigEndianM, // Use big endian in current privilege mode
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// Fault outputs
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output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire
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output logic wfiM, IntPendingM // Stall in Memory stage for WFI until interrupt pending or timeout
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output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire
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output logic wfiM, IntPendingM // Stall in Memory stage for WFI until interrupt pending or timeout
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);
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logic [3:0] CauseM; // trap cause
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logic [15:0] MEDELEG_REGW; // exception delegation CSR
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logic [11:0] MIDELEG_REGW; // interrupt delegation CSR
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logic sretM, mretM; // supervisor / machine return instruction
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logic IllegalCSRAccessM; // Illegal access to CSR
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logic IllegalIEUFPUInstrM; // Illegal IEU or FPU instruction, delayed to Mem stage
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logic InstrPageFaultM; // Instruction page fault, delayed to Mem stage
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logic InstrAccessFaultM; // Instruction access fault, delayed to Mem stages
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logic IllegalInstrFaultM; // Illegal instruction fault
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logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; // Status bits needed within privileged unit
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logic STATUS_MIE, STATUS_SIE; // status bits: interrupt enables
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logic [11:0] MIP_REGW, MIE_REGW; // interrupt pending and enable bits
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logic [1:0] NextPrivilegeModeM; // next privilege mode based on trap or return
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logic DelegateM; // trap should be delegated
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logic InterruptM; // interrupt occuring
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logic ExceptionM; // Memory stage instruction caused a fault
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logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE
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logic [3:0] CauseM; // trap cause
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logic [15:0] MEDELEG_REGW; // exception delegation CSR
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logic [11:0] MIDELEG_REGW; // interrupt delegation CSR
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logic sretM, mretM; // supervisor / machine return instruction
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logic IllegalCSRAccessM; // Illegal access to CSR
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logic IllegalIEUFPUInstrM; // Illegal IEU or FPU instruction, delayed to Mem stage
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logic InstrPageFaultM; // Instruction page fault, delayed to Mem stage
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logic InstrAccessFaultM; // Instruction access fault, delayed to Mem stages
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logic IllegalInstrFaultM; // Illegal instruction fault
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logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; // Status bits needed within privileged unit
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logic STATUS_MIE, STATUS_SIE; // status bits: interrupt enables
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logic [11:0] MIP_REGW, MIE_REGW; // interrupt pending and enable bits
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logic [1:0] NextPrivilegeModeM; // next privilege mode based on trap or return
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logic DelegateM; // trap should be delegated
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logic InterruptM; // interrupt occuring
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logic ExceptionM; // Memory stage instruction caused a fault
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logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE
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// track the current privilege level
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privmode #(P) privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
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.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
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@ -156,8 +155,3 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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.InstrValidM, .CommittedM, .CommittedF,
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.TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
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endmodule
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