mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge remote-tracking branch 'upstream/main' into main
This commit is contained in:
Kip Macsai-Goren
commit
d668c563f4
24
CONTRIBUTING.md
Normal file
24
CONTRIBUTING.md
Normal file
@ -0,0 +1,24 @@
|
||||
<!---
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
--->
|
||||
# Contributing
|
||||
New Contributors are always welcome.
|
||||
|
||||
## Contributor Agreement
|
||||
Most Contributors are [members](https://www.openhwgroup.org/membership/) of the
|
||||
OpenHW Group and participate in one or more [Technical Task Groups](https://www.openhwgroup.org/working-groups/).
|
||||
Membership is strongly encouraged, but not required. Contributors must be
|
||||
covered by the terms of the [Eclipse Contributor Agreement](https://www.eclipse.org/legal/ECA.php)
|
||||
(for individuals) **or** the [Eclipse Member Committer and Contributor Agreement](https://www.eclipse.org/legal/committer_process/EclipseMemberCommitterAgreement.pdf)
|
||||
(for employees of Member companies). The ECA/MCCA provides a legal
|
||||
framework for a Contributor's technical contributions to the OpenHW Group,
|
||||
including provisions for grant of copyright license and a Developer
|
||||
Certificate of Origin on contributions merged into OpenHW Group repositories.
|
||||
|
||||
## The Mechanics
|
||||
1. [Fork](https://help.github.com/articles/fork-a-repo/) the [cvw](https://github.com/openhwgroup/cvw) repository
|
||||
2. Clone repository: `git clone https://github.com/[your_github_username]/cvw`
|
||||
3. Create your feature branch: `git checkout -b <my_branch>.`<br> Please uniquify your branch name. See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md) for a useful nominclature.
|
||||
5. Commit your changes: `git commit -m 'Add some feature'`
|
||||
6. Push feature branch: `git push origin <my_branch>`
|
||||
7. Submit a [pull request](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/creating-a-pull-request-from-a-fork).
|
||||
@ -150,7 +150,6 @@ if(sys.argv[1] == '-b'):
|
||||
if(sys.argv[2] == '-s'):
|
||||
summery = 1
|
||||
sys.argv = sys.argv[1::]
|
||||
print('summery = %d' % summery)
|
||||
for config in sys.argv[2::]:
|
||||
benchmarks = ProcessFile(config)
|
||||
ComputeAverage(benchmarks)
|
||||
@ -163,7 +162,16 @@ if(sys.argv[1] == '-b'):
|
||||
print(config)
|
||||
for benchmark in benchmarks:
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
print("BENCHMARK")
|
||||
print(nameString)
|
||||
print(opt)
|
||||
print(dataDict)
|
||||
benchmarkAll.append((nameString, opt, config, dataDict))
|
||||
print('ALL!!!!!!!!!!')
|
||||
#for bench in benchmarkAll:
|
||||
# print('BENCHMARK')
|
||||
# print(bench)
|
||||
#print('ALL!!!!!!!!!!')
|
||||
|
||||
# now extract all branch prediction direction miss rates for each
|
||||
# namestring + opt, config
|
||||
@ -177,7 +185,6 @@ if(sys.argv[1] == '-b'):
|
||||
|
||||
size = len(benchmarkDict)
|
||||
index = 1
|
||||
print('summery = %d' % summery)
|
||||
if(summery == 0):
|
||||
print('Number of plots', size)
|
||||
for benchmarkName in benchmarkDict:
|
||||
|
||||
@ -42,7 +42,7 @@
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 1
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
@ -130,8 +130,9 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 1
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define SSTC_SUPPORTED 1
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
@ -139,8 +139,9 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
|
||||
`define BPRED_SIZE 10
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 12
|
||||
`define BTB_SIZE 10
|
||||
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 1
|
||||
|
||||
@ -134,8 +134,9 @@
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
|
||||
@ -133,8 +133,9 @@
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
|
||||
@ -134,8 +134,9 @@
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
|
||||
@ -68,7 +68,7 @@
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_BITSPERCYCLE 2
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
@ -133,8 +133,9 @@
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
|
||||
@ -136,8 +136,9 @@
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
|
||||
@ -136,8 +136,9 @@
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
|
||||
@ -136,8 +136,9 @@
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
|
||||
@ -117,7 +117,7 @@
|
||||
|
||||
// largest length in IEU/FPU
|
||||
`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
|
||||
`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
|
||||
`define LLEN (($unsigned(`FLEN)<$unsigned(`XLEN)) ? ($unsigned(`XLEN)) : ($unsigned(`FLEN)))
|
||||
`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
|
||||
`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
|
||||
`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
|
||||
|
||||
49
setup.csh
Executable file
49
setup.csh
Executable file
@ -0,0 +1,49 @@
|
||||
#!/bin/sh
|
||||
|
||||
# setup.csh
|
||||
# james.stine@okstate.edu 18 February 2023
|
||||
|
||||
echo "Executing Wally setup.csh"
|
||||
|
||||
# Path to Wally repository
|
||||
set WALLY = $PWD
|
||||
echo '$WALLY set to ' ${WALLY}
|
||||
|
||||
# Extend alias which makes extending PATH much easier.
|
||||
alias extend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 ${\!:1}:\!:2;echo Added \!:2 to \!:1'
|
||||
alias prepend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 "\!:2":${\!:1};echo Added \!:2 to \!:1'
|
||||
|
||||
# License servers and commercial CAD tool paths
|
||||
# Must edit these based on your local environment. Ask your sysadmin.
|
||||
setenv MGLS_LICENSE_FILE 27002@zircon.eng.hmc.edu # Change this to your Siemens license server
|
||||
setenv SNPSLMD_LICENSE_FILE 27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
|
||||
setenv QUESTAPATH /cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa
|
||||
setenv SNPSPATH /cad/synopsys/SYN/bin # Change this for your path to Design Compiler
|
||||
|
||||
# Path to RISC-V Tools
|
||||
setenv RISCV /opt/riscv # change this if you installed the tools in a different location
|
||||
|
||||
# Tools
|
||||
# Questa and Synopsys
|
||||
extend PATH $QUESTAPATH
|
||||
extend PATH $SNPSPATH
|
||||
# GCC
|
||||
prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/lib
|
||||
prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
|
||||
extend PATH $RISCV/riscv-gnu-toolchain/bin # GCC tools
|
||||
extend PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools
|
||||
# Spike
|
||||
extend LD_LIBRARY_PATH $RISCV/lib
|
||||
extend PATH $RISCV/bin
|
||||
# utility functions in Wally repository
|
||||
extend PATH $WALLY/bin
|
||||
# Verilator
|
||||
extend PATH /usr/local/bin/verilator # Change this for your path to Verilator
|
||||
# ModelSim/Questa (vsim)
|
||||
# Note: 2022.1 complains on cache/sram1p1r1w about StoredData cannot be driven by multiple always_ff blocks. Ues 2021.2 for now
|
||||
|
||||
# Imperas; put this in if you are using it
|
||||
#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path)
|
||||
#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
|
||||
|
||||
echo "setup done"
|
||||
@ -43,7 +43,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
|
||||
vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691 -fatal 7
|
||||
vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7
|
||||
|
||||
run -all
|
||||
run -all
|
||||
@ -52,7 +52,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=1 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
|
||||
|
||||
#-- Run the Simulation
|
||||
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
|
||||
@ -63,7 +63,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
exec ./slack-notifier/slack-notifier.py
|
||||
|
||||
} elseif {$2 eq "ahb"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
|
||||
@ -77,7 +77,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
run -all
|
||||
# power off -r /dut/core/*
|
||||
} else {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
|
||||
|
||||
10
sim/wally.do
10
sim/wally.do
@ -36,7 +36,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
|
||||
|
||||
#-- Run the Simulation
|
||||
#run -all
|
||||
@ -50,7 +50,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
|
||||
|
||||
#-- Run the Simulation
|
||||
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
|
||||
@ -68,7 +68,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
|
||||
} elseif {$2 eq "fpga"} {
|
||||
echo "hello"
|
||||
vlog -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063
|
||||
vlog -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
|
||||
vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt
|
||||
vsim workopt +nowarn3829 -fatal 7
|
||||
|
||||
@ -78,10 +78,10 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
|
||||
} else {
|
||||
if {$2 eq "ahb"} {
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
} else {
|
||||
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
|
||||
}
|
||||
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
|
||||
|
||||
|
||||
514
sim/wave.do
514
sim/wave.do
@ -37,17 +37,17 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
|
||||
add wave -noupdate -expand -group PCS /testbench/PCW
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCM
|
||||
add wave -noupdate -group PCS /testbench/PCW
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
|
||||
@ -91,18 +91,16 @@ add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
|
||||
add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
|
||||
@ -181,210 +179,205 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
|
||||
add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
|
||||
add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
|
||||
add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
|
||||
@ -563,21 +556,21 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
|
||||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
|
||||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
|
||||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
|
||||
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||
add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
|
||||
@ -608,25 +601,7 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions
|
||||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
|
||||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
|
||||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RepairD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
|
||||
add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
|
||||
add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
|
||||
add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
|
||||
@ -640,31 +615,28 @@ add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/c
|
||||
add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
|
||||
add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
|
||||
add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
|
||||
add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
|
||||
add wave -noupdate /testbench/dut/core/ifu/CSRWriteFenceM
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/NextFFLAGSM
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/WriteFFLAGSM
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/InstrValidNotFlushedM
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRUWriteM
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRAdrM
|
||||
add wave -noupdate /testbench/dut/core/ifu/PCLinkE
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheAccess
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheMiss
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheAccess
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMiss
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {497341 ns} 0}
|
||||
quietly wave cursor active 5
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {368581 ns} 0} {{Cursor 5} {394987 ns} 1}
|
||||
quietly wave cursor active 4
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 194
|
||||
configure wave -justifyvalue left
|
||||
@ -679,4 +651,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {497212 ns} {497470 ns}
|
||||
WaveRestoreZoom {368125 ns} {368797 ns}
|
||||
|
||||
@ -60,14 +60,13 @@ module fctrl (
|
||||
output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input
|
||||
output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input
|
||||
// other control signals
|
||||
output logic IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
|
||||
output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
|
||||
output logic FDivStartE, IDivStartE // Start division or squareroot
|
||||
);
|
||||
|
||||
`define FCTRLW 12
|
||||
|
||||
logic [`FCTRLW-1:0] ControlsD; // control signals
|
||||
logic IllegalFPUInstrD, IllegalFPUInstrE; // is the intruction an illegal fpu instruction
|
||||
logic FRegWriteD; // FP register write enable
|
||||
logic FDivStartD; // start division/sqrt
|
||||
logic FWriteIntD; // integer register write enable
|
||||
@ -280,9 +279,9 @@ module fctrl (
|
||||
assign Adr3D = InstrD[31:27];
|
||||
|
||||
// D/E pipleine register
|
||||
flopenrc #(14+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE,
|
||||
{FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, IllegalFPUInstrD, FCvtIntD},
|
||||
{FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE});
|
||||
flopenrc #(13+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE,
|
||||
{FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD},
|
||||
{FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE});
|
||||
flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {Adr1D, Adr2D, Adr3D}, {Adr1E, Adr2E, Adr3E});
|
||||
flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
|
||||
flopenrc #(3) DEEnReg(clk, reset, FlushE, ~StallE, {XEnD, YEnD, ZEnD}, {XEnE, YEnE, ZEnE});
|
||||
@ -292,9 +291,9 @@ module fctrl (
|
||||
else assign IDivStartE = 0;
|
||||
|
||||
// E/M pipleine register
|
||||
flopenrc #(14+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
|
||||
{FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE},
|
||||
{FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, IllegalFPUInstrM, FCvtIntM});
|
||||
flopenrc #(13+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
|
||||
{FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE},
|
||||
{FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, FCvtIntM});
|
||||
|
||||
// renameing for readability
|
||||
assign FpLoadStoreM = FResSelM[1];
|
||||
|
||||
@ -129,7 +129,6 @@ module fdivsqrtpreproc (
|
||||
|
||||
// pipeline registers
|
||||
flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM);
|
||||
flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
|
||||
flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
|
||||
flopen #(1) negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
|
||||
flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
|
||||
@ -137,6 +136,8 @@ module fdivsqrtpreproc (
|
||||
flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
|
||||
flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
|
||||
flopen #(`XLEN) srcareg(clk, IFDivStartE, AE, AM);
|
||||
if (`XLEN==64)
|
||||
flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
|
||||
|
||||
end else begin // Int not supported
|
||||
assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}};
|
||||
|
||||
@ -55,7 +55,7 @@ module fpu (
|
||||
output logic FpLoadStoreM, // Fp load instruction? (to LSU)
|
||||
output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU)
|
||||
output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU)
|
||||
output logic IllegalFPUInstrM, // Is the instruction an illegal fpu instruction (to privileged unit)
|
||||
output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU)
|
||||
output logic [4:0] SetFflagsM, // FPU flags (to privileged unit)
|
||||
// Writeback stage
|
||||
input logic [4:0] RdW, // which FP register to write to (from IEU)
|
||||
@ -160,6 +160,7 @@ module fpu (
|
||||
logic [`FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed
|
||||
logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
|
||||
logic [`FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer
|
||||
logic mvsgn; // sign bit for extending move
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Decode Stage: fctrl decoder, read register file
|
||||
@ -171,7 +172,7 @@ module fpu (
|
||||
.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
|
||||
.reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
|
||||
.FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
|
||||
.IllegalFPUInstrM, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
|
||||
.IllegalFPUInstrD, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
|
||||
.FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW,
|
||||
.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E);
|
||||
|
||||
@ -278,21 +279,25 @@ module fpu (
|
||||
mux3 #(`FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
|
||||
assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
|
||||
|
||||
// select the result that may be written to the integer register - to IEU
|
||||
if(`FPSIZES == 1)
|
||||
// select the result that may be written to the integer register with fmv - to IEU
|
||||
if(`FPSIZES == 1) begin
|
||||
assign mvsgn = XE[`FLEN-1];
|
||||
assign SgnExtXE = XE;
|
||||
else if(`FPSIZES == 2)
|
||||
mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{XsE}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
|
||||
else if(`FPSIZES == 3 | `FPSIZES == 4)
|
||||
mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{XsE}}, XE[`H_LEN-1:0]},
|
||||
{{`FLEN-`S_LEN{XsE}}, XE[`S_LEN-1:0]},
|
||||
{{`FLEN-`D_LEN{XsE}}, XE[`D_LEN-1:0]},
|
||||
end else if(`FPSIZES == 2) begin
|
||||
mux2 #(1) sgnmux (XE[`LEN1-1], XE[`FLEN-1],FmtE, mvsgn);
|
||||
mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{mvsgn}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
|
||||
end else if(`FPSIZES == 3 | `FPSIZES == 4) begin
|
||||
mux4 #(1) sgnmux (XE[`H_LEN-1], XE[`S_LEN-1], XE[`D_LEN-1], XE[`LLEN-1], FmtE, mvsgn);
|
||||
mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{mvsgn}}, XE[`H_LEN-1:0]},
|
||||
{{`FLEN-`S_LEN{mvsgn}}, XE[`S_LEN-1:0]},
|
||||
{{`FLEN-`D_LEN{mvsgn}}, XE[`D_LEN-1:0]},
|
||||
XE, FmtE, SgnExtXE);
|
||||
end
|
||||
|
||||
if (`FLEN>`XLEN)
|
||||
assign IntSrcXE = SgnExtXE[`XLEN-1:0];
|
||||
else
|
||||
assign IntSrcXE = {{`XLEN-`FLEN{XsE}}, SgnExtXE};
|
||||
assign IntSrcXE = {{`XLEN-`FLEN{mvsgn}}, SgnExtXE};
|
||||
mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
|
||||
|
||||
// E/M pipe registers
|
||||
|
||||
50
src/generic/mem/ram2p1r1wbe_128x64.sv
Normal file
50
src/generic/mem/ram2p1r1wbe_128x64.sv
Normal file
@ -0,0 +1,50 @@
|
||||
///////////////////////////////////////////
|
||||
// ram2p1rwbe_128x64.sv
|
||||
//
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: RAM wrapper for instantiating RAM IP
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ram2p1r1wbe_128x64(
|
||||
input logic CLKA,
|
||||
input logic CLKB,
|
||||
input logic CEBA,
|
||||
input logic CEBB,
|
||||
input logic WEBA,
|
||||
input logic WEBB,
|
||||
input logic [6:0] AA,
|
||||
input logic [6:0] AB,
|
||||
input logic [63:0] DA,
|
||||
input logic [63:0] DB,
|
||||
input logic [63:0] BWEBA,
|
||||
input logic [63:0] BWEBB,
|
||||
output logic [63:0] QA,
|
||||
output logic [63:0] QB
|
||||
);
|
||||
|
||||
// replace "generic128x64RAM" with "TSDN..128X64.." module from your memory vendor
|
||||
TSDN28HPCPA128X64M4FW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
|
||||
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
|
||||
// generic128x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
|
||||
// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
|
||||
|
||||
endmodule
|
||||
50
src/generic/mem/ram2p1r1wbe_512x64.sv
Normal file
50
src/generic/mem/ram2p1r1wbe_512x64.sv
Normal file
@ -0,0 +1,50 @@
|
||||
///////////////////////////////////////////
|
||||
// ram2p1rwbe_2048x64.sv
|
||||
//
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: RAM wrapper for instantiating RAM IP
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ram2p1r1wbe_2048x64(
|
||||
input logic CLKA,
|
||||
input logic CLKB,
|
||||
input logic CEBA,
|
||||
input logic CEBB,
|
||||
input logic WEBA,
|
||||
input logic WEBB,
|
||||
input logic [8:0] AA,
|
||||
input logic [8:0] AB,
|
||||
input logic [63:0] DA,
|
||||
input logic [63:0] DB,
|
||||
input logic [63:0] BWEBA,
|
||||
input logic [63:0] BWEBB,
|
||||
output logic [63:0] QA,
|
||||
output logic [63:0] QB
|
||||
);
|
||||
|
||||
// replace "generic2048x64RAM" with "TSDN..2048X64.." module from your memory vendor
|
||||
TSDN28HPCPA2048X64MMFW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
|
||||
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
|
||||
// generic2048x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
|
||||
// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
|
||||
|
||||
endmodule
|
||||
@ -38,19 +38,19 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
|
||||
|
||||
// Core Memory
|
||||
logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
|
||||
if ((`USE_SRAM == 1) & (DATA_WIDTH == 64)) begin
|
||||
/* if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 64)) begin
|
||||
rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
|
||||
|
||||
end if ((`USE_SRAM == 1) & (DATA_WIDTH == 32)) begin
|
||||
end if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 32)) begin
|
||||
rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
|
||||
|
||||
end else begin
|
||||
always @ (posedge clk) begin
|
||||
end else begin */
|
||||
always @ (posedge clk) begin
|
||||
if(ce) dout <= ROM[addr];
|
||||
end
|
||||
end
|
||||
|
||||
// for FPGA, initialize with zero-stage bootloader
|
||||
if(PRELOAD_ENABLED) begin
|
||||
if(PRELOAD_ENABLED)
|
||||
initial begin
|
||||
ROM[0] = 64'h9581819300002197;
|
||||
ROM[1] = 64'h4281420141014081;
|
||||
@ -96,7 +96,5 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
|
||||
ROM[41] = 64'h40a7853b4015551b;
|
||||
ROM[42] = 64'h808210a7a02367c9;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -32,6 +32,7 @@ module rom1p1r_128x64(
|
||||
);
|
||||
|
||||
// replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor
|
||||
generic64x128ROM romIP (.CLK, .CEB, .A, .Q);
|
||||
ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q);
|
||||
// generic64x128ROM romIP (.CLK, .CEB, .A, .Q);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -36,8 +36,8 @@ module controller(
|
||||
input logic StallD, FlushD, // Stall, flush Decode stage
|
||||
input logic [31:0] InstrD, // Instruction in Decode stage
|
||||
output logic [2:0] ImmSrcD, // Type of immediate extension
|
||||
input logic IllegalIEUInstrFaultD, // Illegal IEU instruction
|
||||
output logic IllegalBaseInstrFaultD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
|
||||
input logic IllegalIEUFPUInstrD, // Illegal IEU and FPU instruction
|
||||
output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
|
||||
// Execute stage control signals
|
||||
input logic StallE, FlushE, // Stall, flush Execute stage
|
||||
input logic [1:0] FlagsE, // Comparison flags ({eq, lt})
|
||||
@ -135,7 +135,7 @@ module controller(
|
||||
// RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal
|
||||
7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction
|
||||
7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw
|
||||
7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // flw - only legal if FP supported
|
||||
7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported
|
||||
7'b0001111: if (`ZIFENCEI_SUPPORTED)
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
|
||||
else
|
||||
@ -147,7 +147,7 @@ module controller(
|
||||
else
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
|
||||
7'b0100011: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // sw
|
||||
7'b0100111: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // fsw - only legal if FP supported
|
||||
7'b0100111: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_1; // fsw - only legal if FP supported
|
||||
7'b0101111: if (`A_SUPPORTED) begin
|
||||
if (InstrD[31:27] == 5'b00010)
|
||||
ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr
|
||||
@ -187,10 +187,10 @@ module controller(
|
||||
// Squash control signals if coming from an illegal compressed instruction
|
||||
// On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them.
|
||||
assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11];
|
||||
assign IllegalBaseInstrFaultD = ControlsD[0] | IllegalERegAdrD;
|
||||
assign IllegalBaseInstrD = ControlsD[0] | IllegalERegAdrD;
|
||||
assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
|
||||
ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD,
|
||||
PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD;
|
||||
PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
|
||||
|
||||
|
||||
assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
|
||||
|
||||
@ -32,8 +32,8 @@ module ieu (
|
||||
input logic clk, reset,
|
||||
// Decode stage signals
|
||||
input logic [31:0] InstrD, // Instruction
|
||||
input logic IllegalIEUInstrFaultD, // Illegal instruction
|
||||
output logic IllegalBaseInstrFaultD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
|
||||
input logic IllegalIEUFPUInstrD, // Illegal instruction
|
||||
output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
|
||||
// Execute stage signals
|
||||
input logic [`XLEN-1:0] PCE, // PC
|
||||
input logic [`XLEN-1:0] PCLinkE, // PC + 4
|
||||
@ -96,9 +96,9 @@ module ieu (
|
||||
|
||||
controller c(
|
||||
.clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
|
||||
.IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
|
||||
.PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .ZBBSelectE, .MemReadE, .CSRReadE,
|
||||
.Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
|
||||
.IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
|
||||
.PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE,
|
||||
.Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
|
||||
.CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
|
||||
.RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
|
||||
.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
|
||||
|
||||
@ -54,6 +54,7 @@ module bpred (
|
||||
input logic InstrValidD, InstrValidE,
|
||||
input logic PCSrcE, // Executation stage branch is taken
|
||||
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
|
||||
input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address
|
||||
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
|
||||
output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
|
||||
output logic JumpOrTakenBranchM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
|
||||
@ -67,7 +68,6 @@ module bpred (
|
||||
output logic PredictionInstrClassWrongM // Class prediction is wrong
|
||||
);
|
||||
|
||||
logic PredValidF;
|
||||
logic [1:0] DirPredictionF;
|
||||
|
||||
logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD;
|
||||
@ -91,16 +91,29 @@ module bpred (
|
||||
|
||||
// Part 1 branch direction prediction
|
||||
// look into the 2 port Sram model. something is wrong.
|
||||
if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor
|
||||
if (`BPRED_TYPE == "BP_TWOBIT") begin:Predictor
|
||||
twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
|
||||
|
||||
end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
|
||||
globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
end else if (`BPRED_TYPE == "BP_GSHARE") begin:Predictor
|
||||
gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
|
||||
.PCSrcE);
|
||||
|
||||
end else if (`BPRED_TYPE == "BP_GLOBAL") begin:Predictor
|
||||
gshare #(`BPRED_SIZE, "global") DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
|
||||
.PCSrcE);
|
||||
|
||||
end else if (`BPRED_TYPE == "BP_GSHARE_BASIC") begin:Predictor
|
||||
gsharebasic #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
|
||||
|
||||
<<<<<<< HEAD
|
||||
end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
|
||||
speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.DirPredictionF, .DirPredictionWrongE,
|
||||
@ -116,6 +129,13 @@ module bpred (
|
||||
.PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
|
||||
.PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
|
||||
|
||||
=======
|
||||
end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor
|
||||
gsharebasic #(`BPRED_SIZE, "global") DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
|
||||
|
||||
>>>>>>> upstream/main
|
||||
end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
|
||||
// *** Fix me
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
@ -134,15 +154,14 @@ module bpred (
|
||||
// Part 2 Branch target address prediction
|
||||
// BTB contains target address for all CFI
|
||||
|
||||
btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
|
||||
.PCNextF, .PCF, .PCD, .PCE,
|
||||
btb #(`BTB_SIZE)
|
||||
TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCF, .PCD, .PCE, .PCM,
|
||||
.PredPCF,
|
||||
.BTBPredInstrClassF,
|
||||
.PredValidF,
|
||||
.AnyWrongPredInstrClassE,
|
||||
.IEUAdrE,
|
||||
.InstrClassD,
|
||||
.InstrClassE);
|
||||
.PredictionInstrClassWrongM,
|
||||
.IEUAdrE, .IEUAdrM,
|
||||
.InstrClassD, .InstrClassE, .InstrClassM);
|
||||
|
||||
// the branch predictor needs a compact decoding of the instruction class.
|
||||
if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
|
||||
@ -176,10 +195,8 @@ module bpred (
|
||||
PredInstrClassF[3];
|
||||
end else begin
|
||||
assign PredInstrClassF = BTBPredInstrClassF;
|
||||
assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) |
|
||||
PredInstrClassF[2] |
|
||||
(PredInstrClassF[1] & PredValidF) |
|
||||
(PredInstrClassF[3] & PredValidF);
|
||||
assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) |
|
||||
PredInstrClassF[1];
|
||||
end
|
||||
|
||||
// Part 3 RAS
|
||||
@ -222,7 +239,17 @@ module bpred (
|
||||
assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
|
||||
|
||||
// branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
|
||||
<<<<<<< HEAD
|
||||
assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
|
||||
=======
|
||||
//assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE));
|
||||
assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
|
||||
|
||||
logic BPPredWrongEAlt;
|
||||
logic NotMatch;
|
||||
assign BPPredWrongEAlt = PredictionPCWrongE & InstrValidE & InstrValidD; // this does not work for cubic benchmark
|
||||
assign NotMatch = BPPredWrongE != BPPredWrongEAlt;
|
||||
>>>>>>> upstream/main
|
||||
|
||||
// Output the predicted PC or corrected PC on miss-predict.
|
||||
// Selects the BP or PC+2/4.
|
||||
|
||||
@ -30,32 +30,30 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module btb #(parameter int Depth = 10 ) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallM, FlushD, FlushM,
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages
|
||||
output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
|
||||
output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
|
||||
output logic PredValidF, // BTB's guess is valid
|
||||
module btb #(parameter Depth = 10 ) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
|
||||
output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
|
||||
output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
|
||||
// update
|
||||
input logic AnyWrongPredInstrClassE, // BTB's instruction class guess was wrong
|
||||
input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
|
||||
input logic [3:0] InstrClassD, // Instruction class to insert into btb
|
||||
input logic [3:0] InstrClassE // Instruction class to insert into btb
|
||||
input logic PredictionInstrClassWrongM, // BTB's instruction class guess was wrong
|
||||
input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
|
||||
input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb
|
||||
input logic [3:0] InstrClassD, // Instruction class to insert into btb
|
||||
input logic [3:0] InstrClassE, // Instruction class to insert into btb
|
||||
input logic [3:0] InstrClassM // Instruction class to insert into btb
|
||||
);
|
||||
|
||||
localparam TotalDepth = 2 ** Depth;
|
||||
logic [TotalDepth-1:0] ValidBits;
|
||||
logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
|
||||
logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex;
|
||||
logic [`XLEN-1:0] ResetPC;
|
||||
logic MatchF, MatchD, MatchE, MatchNextX, MatchXF;
|
||||
logic [`XLEN+4:0] ForwardBTBPrediction, ForwardBTBPredictionF;
|
||||
logic MatchF, MatchD, MatchE, MatchM, MatchNextX, MatchXF;
|
||||
logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF;
|
||||
logic [`XLEN+3:0] TableBTBPredictionF;
|
||||
logic [`XLEN-1:0] PredPCD;
|
||||
logic [3:0] PredInstrClassD; // *** copy of reg outside module
|
||||
logic UpdateEn;
|
||||
logic TablePredValidF, PredValidD;
|
||||
|
||||
// hashing function for indexing the PC
|
||||
// We have Depth bits to index, but XLEN bits as the input.
|
||||
@ -64,6 +62,7 @@ module btb #(parameter int Depth = 10 ) (
|
||||
assign PCFIndex = {PCF[Depth+1] ^ PCF[1], PCF[Depth:2]};
|
||||
assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]};
|
||||
assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
|
||||
assign PCMIndex = {PCM[Depth+1] ^ PCM[1], PCM[Depth:2]};
|
||||
|
||||
// must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid
|
||||
// during reset. The BTB must produce a non X PC1NextF to allow the simulation to run.
|
||||
@ -75,36 +74,28 @@ module btb #(parameter int Depth = 10 ) (
|
||||
assign MatchF = PCNextFIndex == PCFIndex;
|
||||
assign MatchD = PCNextFIndex == PCDIndex;
|
||||
assign MatchE = PCNextFIndex == PCEIndex;
|
||||
assign MatchNextX = MatchF | MatchD | MatchE;
|
||||
assign MatchM = PCNextFIndex == PCMIndex;
|
||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} :
|
||||
MatchD ? {PredValidD, InstrClassD, PredPCD} :
|
||||
{1'b1, InstrClassE, IEUAdrE} ;
|
||||
assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
|
||||
MatchD ? {InstrClassD, PredPCD} :
|
||||
MatchE ? {InstrClassE, IEUAdrE} :
|
||||
{InstrClassM, IEUAdrM} ;
|
||||
|
||||
flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
|
||||
flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
|
||||
|
||||
assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF};
|
||||
assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF};
|
||||
|
||||
always_ff @ (posedge clk) begin
|
||||
if (reset) begin
|
||||
ValidBits <= #1 {TotalDepth{1'b0}};
|
||||
end else if ((UpdateEn) & ~StallM & ~FlushM) begin
|
||||
ValidBits[PCEIndex] <= #1 |InstrClassE;
|
||||
end
|
||||
if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
|
||||
end
|
||||
|
||||
//assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
|
||||
|
||||
assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE;
|
||||
assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM;
|
||||
|
||||
// An optimization may be using a PC relative address.
|
||||
ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
|
||||
.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
|
||||
.ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
|
||||
.ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
|
||||
|
||||
flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD});
|
||||
flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,146 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// gsharePredictor.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module foldedgshare #(parameter k = 16, depth = 10) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE, MatchM, MatchW;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
|
||||
|
||||
logic [k-1:0] GHRF;
|
||||
logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW;
|
||||
logic [k-1:0] GHRNextF;
|
||||
logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW;
|
||||
logic [k-1:0] IndexNextF, IndexF;
|
||||
logic [k-1:0] IndexD, IndexE, IndexM, IndexW;
|
||||
logic [depth-1:0] FinalIndexNextF, FinalIndexW;
|
||||
|
||||
logic PCSrcM, PCSrcW;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
localparam delta = 2 * depth - k;
|
||||
|
||||
assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
|
||||
assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
|
||||
assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
|
||||
assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
|
||||
|
||||
// just be dumb for now.
|
||||
//localparam int kToDepthRatio = (k+depth) / depth;
|
||||
assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]};
|
||||
assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]};
|
||||
|
||||
ram2p1r1wbe #(2**depth, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
|
||||
.ra1(FinalIndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(FinalIndexW),
|
||||
.wd2(NewDirPredictionW),
|
||||
.we2(BranchInstrW & ~StallW & ~FlushW),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
// and then register for use in the Fetch stage.
|
||||
assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
|
||||
assign MatchW = BranchInstrW & (IndexNextF == IndexW);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
|
||||
MatchD ? NewDirPredictionD :
|
||||
MatchE ? NewDirPredictionE :
|
||||
MatchM ? NewDirPredictionM :
|
||||
NewDirPredictionW;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
// New prediction pipeline
|
||||
satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
|
||||
flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||
flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
|
||||
|
||||
// PCSrc pipeline
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
|
||||
|
||||
// GHR pipeline
|
||||
assign GHRNextF = FlushD ? GHRNextD[k:1] :
|
||||
BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
|
||||
GHRF;
|
||||
|
||||
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
|
||||
|
||||
assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
|
||||
flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
|
||||
|
||||
assign GHRNextE = FlushE ? GHRNextM : GHRD;
|
||||
flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
|
||||
assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
|
||||
|
||||
assign GHRNextM = FlushM ? GHRNextW : GHRE;
|
||||
flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
|
||||
|
||||
assign GHRNextW = FlushW ? GHRW : GHRM;
|
||||
flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
|
||||
|
||||
endmodule
|
||||
@ -1,12 +1,13 @@
|
||||
///////////////////////////////////////////
|
||||
// globalHistoryPredictor.sv
|
||||
// gshare.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
// Written: Ross Thompson
|
||||
// Email: ross1728@gmail.com
|
||||
// Created: 16 March 2021
|
||||
// Adapted from ssanghai@hmc.edu (Shreya Sanghai)
|
||||
// Modified: 20 February 2023
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
// Purpose: gshare and Global History Branch predictors
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
@ -28,7 +29,8 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module gshare #(parameter k = 10) (
|
||||
module gshare #(parameter k = 10,
|
||||
parameter string TYPE = "gshare") (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
@ -36,28 +38,60 @@ module gshare #(parameter k = 10) (
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCE,
|
||||
input logic BranchInstrE, BranchInstrM, PCSrcE
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, PCSrcE
|
||||
);
|
||||
|
||||
logic [k-1:0] IndexNextF, IndexE;
|
||||
logic [1:0] DirPredictionD, DirPredictionE;
|
||||
logic MatchF, MatchD, MatchE, MatchM;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
logic [1:0] NewDirPredictionE, NewDirPredictionM;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHR;
|
||||
logic [k-1:0] GHRNext;
|
||||
logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHRM;
|
||||
logic [k-1:0] GHRNextM, GHRNextF;
|
||||
logic PCSrcM;
|
||||
|
||||
assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
|
||||
if(TYPE == "gshare") begin
|
||||
assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
|
||||
assign IndexD = GHRD ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
|
||||
assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
|
||||
assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
end else if(TYPE == "global") begin
|
||||
assign IndexNextF = GHRNextF;
|
||||
assign IndexF = GHRF;
|
||||
assign IndexD = GHRD;
|
||||
assign IndexE = GHRE;
|
||||
assign IndexM = GHRM;
|
||||
end
|
||||
|
||||
assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
|
||||
MatchD ? {2{DirPredictionD[1]}} :
|
||||
MatchE ? {NewDirPredictionE} :
|
||||
NewDirPredictionM ;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallM & ~FlushM),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(DirPredictionF),
|
||||
.wa2(IndexE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(BranchInstrE & ~StallM & ~FlushM),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexM),
|
||||
.wd2(NewDirPredictionM),
|
||||
.we2(BranchInstrM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||
@ -68,13 +102,14 @@ module gshare #(parameter k = 10) (
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
|
||||
assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
|
||||
flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
|
||||
assign GHRNextF = BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF;
|
||||
assign GHRF = BranchInstrD ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD;
|
||||
assign GHRD = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
|
||||
assign GHRE = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
|
||||
|
||||
assign GHRNextM = {PCSrcM, GHRM[k-1:1]};
|
||||
|
||||
flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNextM, GHRM);
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
|
||||
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
|
||||
flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
|
||||
flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,10 +1,11 @@
|
||||
///////////////////////////////////////////
|
||||
// globalHistoryPredictor.sv
|
||||
// gsharebasic.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
// Written: Ross Thompson
|
||||
// Email: ross1728@gmail.com
|
||||
// Created: 16 March 2021
|
||||
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
|
||||
// Modified: 20 February 2023
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
@ -28,12 +29,12 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module globalhistory #(parameter k = 10) (
|
||||
module gsharebasic #(parameter k = 10,
|
||||
parameter string TYPE = "global") (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
@ -41,21 +42,29 @@ module globalhistory #(parameter k = 10) (
|
||||
input logic BranchInstrE, BranchInstrM, PCSrcE
|
||||
);
|
||||
|
||||
logic [k-1:0] IndexNextF, IndexE;
|
||||
logic [1:0] DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionE, NewDirPredictionM;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHR;
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR;
|
||||
logic [k-1:0] GHRNext;
|
||||
logic PCSrcM;
|
||||
|
||||
if(TYPE == "gshare") begin
|
||||
assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
end else if(TYPE == "global") begin
|
||||
assign IndexNextF = GHRNext;
|
||||
assign IndexE = GHRE;
|
||||
end
|
||||
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallM & ~FlushM),
|
||||
.ra1(GHR),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(DirPredictionF),
|
||||
.wa2(GHRE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(BranchInstrE & ~StallM & ~FlushM),
|
||||
.wa2(IndexE),
|
||||
.wd2(NewDirPredictionM),
|
||||
.we2(BranchInstrM & ~StallW & ~FlushW),
|
||||
.bwe2(1'b1));
|
||||
|
||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||
@ -66,7 +75,6 @@ module globalhistory #(parameter k = 10) (
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
|
||||
|
||||
assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
|
||||
flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
@ -74,6 +82,7 @@ module globalhistory #(parameter k = 10) (
|
||||
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
|
||||
flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
|
||||
flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
|
||||
flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
|
||||
|
||||
|
||||
endmodule
|
||||
@ -1,219 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// gsharePredictor.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module optgshare #(parameter k = 10) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE, MatchM, MatchW;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
|
||||
|
||||
logic [k-1:0] GHRF;
|
||||
logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW;
|
||||
logic [k-1:0] GHRNextF;
|
||||
logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW;
|
||||
logic [k-1:0] IndexNextF, IndexF;
|
||||
logic [k-1:0] IndexD, IndexE, IndexM, IndexW;
|
||||
|
||||
logic PCSrcM, PCSrcW;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
|
||||
logic [k+4:0] GHRNext, GHR;
|
||||
logic GHRUpdateEn;
|
||||
|
||||
assign GHRUpdateEn = BranchInstrF | (DirPredictionWrongE & BranchInstrE) |
|
||||
FlushD | FlushE | FlushM | FlushW;
|
||||
|
||||
// it doesn't work this way. Instead we need to see how many branch instructions are flushed.
|
||||
// then shift over by that amount.
|
||||
logic RemoveBrW, RemoveBrM, RemoveBrE, RemoveBrD, RemoveBrF, RemoveBrNextF;
|
||||
|
||||
assign RemoveBrW = '0;
|
||||
assign RemoveBrM = BranchInstrM & FlushW;
|
||||
assign RemoveBrE = BranchInstrE & FlushM;
|
||||
assign RemoveBrD = BranchInstrD & FlushE;
|
||||
assign RemoveBrF = BranchInstrF & FlushD;
|
||||
assign RemoveBrNextF = BranchInstrF & FlushD;
|
||||
|
||||
always_comb begin
|
||||
casez ({BranchInstrF, DirPredictionWrongE, RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM})
|
||||
6'b00_0000: GHRNext = GHR; // no change
|
||||
6'b00_0001: GHRNext = {GHR[k+4:k+1], GHR[k-1:0], 1'b0}; // RemoveBrM
|
||||
6'b0?_0010: GHRNext = {GHR[k+4:k+2], GHR[k:0], 1'b0}; // RemoveBrE
|
||||
6'b0?_0011: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrE, RemoveBrM
|
||||
|
||||
6'b00_0100: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrD
|
||||
6'b00_0101: GHRNext = {GHR[k+4:k+3], GHR[k+1:0], 1'b0}; // RemoveBrD, RemoveBrM
|
||||
6'b0?_0110: GHRNext = {GHR[k+4:k+3], GHR[k+1], GHR[k-1:0], 2'b0}; // RemoveBrD, RemoveBrE
|
||||
6'b0?_0111: GHRNext = {GHR[k+4:k+3], GHR[k-1:0], 3'b0}; // RemoveBrD, RemoveBrE, RemoveBrM
|
||||
|
||||
6'b?0_1000: GHRNext = {GHR[k+2:0], 2'b0}; // RemoveBrF,
|
||||
6'b?0_1001: GHRNext = {GHR[k+2:k+1], GHR[k-1:0], 3'b0}; // RemoveBrF, RemoveBrM
|
||||
6'b??_1010: GHRNext = {GHR[k+2], GHR[k:0], 3'b0}; // RemoveBrF, RemoveBrE
|
||||
6'b??_1011: GHRNext = {GHR[k+2], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrE, RemoveBrM
|
||||
|
||||
6'b?0_1100: GHRNext = {GHR[k+1:0], 3'b0}; // RemoveBrF, RemoveBrD
|
||||
6'b?0_1101: GHRNext = {GHR[k+1], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrM
|
||||
6'b??_1110: GHRNext = {GHR[k:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrE
|
||||
6'b??_1111: GHRNext = {GHR[k-1:0], 5'b0}; // RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM
|
||||
|
||||
6'b?1_0000: GHRNext = {PCSrcE, GHR[k+3:0]}; // Miss prediction, no branches to flushes
|
||||
6'b?1_0001: GHRNext = {PCSrcE, GHR[k+3:k], GHR[k-1:1], 1'b0}; // Miss prediction, branch in Memory stage dropped
|
||||
|
||||
6'b?1_1100: GHRNext = {PCSrcE, GHR[k+1:0], 2'b00}; // Miss prediction, cannot have RemoveBrE
|
||||
6'b?1_1101: GHRNext = {PCSrcE, GHR[k+1], GHR[k-1:0], 3'b0}; // Miss prediction, cannot have RemoveBrE
|
||||
6'b10_0000: GHRNext = {DirPredictionF[1], GHR[k+4:1]};
|
||||
6'b10_0001: GHRNext = {DirPredictionF[1], GHR[k+4:k+1], GHR[k-1:1], 1'b0};
|
||||
6'b10_0010: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k:1], 1'b0};
|
||||
6'b10_0011: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k-1:1], 2'b0};
|
||||
6'b10_0100: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1:1], 1'b0};
|
||||
6'b10_0101: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1], GHR[k-1:1], 2'b0};
|
||||
6'b10_0110: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k], GHR[k-1:1], 2'b0};
|
||||
6'b10_0111: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k-1:1], 3'b0};
|
||||
|
||||
default: GHRNext = GHR;
|
||||
endcase
|
||||
end
|
||||
|
||||
flopenr #(k+5) GHRReg(clk, reset, GHRUpdateEn, GHRNext, GHR);
|
||||
logic [k-1:0] GHRNextF_temp, GHRF_temp;
|
||||
logic [k:0] GHRD_temp, GHRE_temp, GHRM_temp, GHRW_temp;
|
||||
logic GHRFExtra_temp;
|
||||
|
||||
// these are also in the ieu controller. should create inputs.
|
||||
logic InstrValidF, InstrValidD, InstrValidE, InstrValidM, InstrValidW;
|
||||
flopenrc #(1) InstrValidFReg(clk, reset, FlushD, ~StallF, 1'b1, InstrValidF);
|
||||
flopenrc #(1) InstrValidDReg(clk, reset, FlushD, ~StallD, InstrValidF, InstrValidD);
|
||||
flopenrc #(1) InstrValidEReg(clk, reset, FlushE, ~StallE, InstrValidD, InstrValidE);
|
||||
flopenrc #(1) InstrValidMReg(clk, reset, FlushM, ~StallM, InstrValidE, InstrValidM);
|
||||
flopenrc #(1) InstrValidWReg(clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
|
||||
|
||||
|
||||
assign GHRNextF_temp = GHRNext[k+4:5];
|
||||
assign GHRF_temp = InstrValidF ? GHR[k+3:4] : GHRNextF_temp;
|
||||
assign GHRFExtra_temp = InstrValidF ? 1'b0 : GHR[k+4];
|
||||
assign GHRD_temp = InstrValidD ? GHR[k+3:3] : {GHRFExtra_temp, GHRF_temp};
|
||||
assign GHRE_temp = InstrValidE ? GHR[k+2:2] : GHRD_temp;
|
||||
assign GHRM_temp = InstrValidM ? GHR[k+1:1] : GHRE_temp;
|
||||
assign GHRW_temp = InstrValidW ? GHR[k:0] : GHRM_temp;
|
||||
|
||||
|
||||
assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
|
||||
assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
|
||||
assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
|
||||
assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexW),
|
||||
.wd2(NewDirPredictionW),
|
||||
.we2(BranchInstrW & ~StallW & ~FlushW),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
// and then register for use in the Fetch stage.
|
||||
assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
|
||||
assign MatchW = BranchInstrW & (IndexNextF == IndexW);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
|
||||
MatchD ? NewDirPredictionD :
|
||||
MatchE ? NewDirPredictionE :
|
||||
MatchM ? NewDirPredictionM :
|
||||
NewDirPredictionW;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
// New prediction pipeline
|
||||
satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
|
||||
flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||
flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
|
||||
|
||||
// PCSrc pipeline
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
|
||||
|
||||
// GHR pipeline
|
||||
assign GHRNextF = FlushD ? GHRNextD[k:1] :
|
||||
BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
|
||||
GHRF;
|
||||
|
||||
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
|
||||
|
||||
assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
|
||||
flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
|
||||
|
||||
assign GHRNextE = FlushE ? GHRNextM : GHRD;
|
||||
flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
|
||||
assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
|
||||
|
||||
assign GHRNextM = FlushM ? GHRNextW : GHRE;
|
||||
flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
|
||||
|
||||
assign GHRNextW = FlushW ? GHRW : GHRM;
|
||||
flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
|
||||
|
||||
endmodule
|
||||
@ -1,126 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// speculativeglobalhistory.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module speculativeglobalhistory #(parameter int k = 10 ) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE,
|
||||
input logic [3:0] WrongPredInstrClassD,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionE;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE;
|
||||
logic GHRLastF;
|
||||
logic [k-1:0] GHRNextF, GHRNextD, GHRNextE;
|
||||
logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE;
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
|
||||
logic FlushDOrDirWrong;
|
||||
|
||||
assign IndexNextF = GHRNextF;
|
||||
assign IndexF = GHRF;
|
||||
assign IndexD = GHRD[k-1:0];
|
||||
assign IndexE = GHRE[k-1:0];
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(InstrClassE[0]),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
// and then register for use in the Fetch stage.
|
||||
assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
|
||||
MatchD ? {2{DirPredictionD[1]}} :
|
||||
NewDirPredictionE ;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
|
||||
// GHR pipeline
|
||||
|
||||
// If Fetch has a branch, speculatively insert prediction into the GHR
|
||||
// If the front end is flushed or the direction prediction is wrong, reset to
|
||||
// most recent valid GHR. For a BP wrong this is GHRD with the correct prediction shifted in.
|
||||
// For FlushE this is GHRE. GHRNextE is both.
|
||||
assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
|
||||
mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0],
|
||||
{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
|
||||
|
||||
// Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
|
||||
flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF);
|
||||
flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF);
|
||||
|
||||
// With instruction class prediction, the class could be wrong and is checked in Decode.
|
||||
// If it is wrong and branch does exist then shift right and insert the prediction.
|
||||
// If the branch does not exist then shift left and use GHRLastF to restore the LSB.
|
||||
logic [k-1:0] GHRClassWrong;
|
||||
mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, InstrClassD[0], GHRClassWrong);
|
||||
// As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
|
||||
mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);
|
||||
|
||||
flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD);
|
||||
|
||||
mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
|
||||
|
||||
flopenr #(k) GHREReg(clk, reset, ((InstrClassE[0] & ~FlushM) & ~StallE) | FlushE, GHRNextE, GHRE);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
|
||||
|
||||
endmodule
|
||||
@ -1,127 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// gsharePredictor.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module speculativegshare #(parameter int k = 10 ) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
|
||||
input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE,
|
||||
input logic [3:0] WrongPredInstrClassD,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionE;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE;
|
||||
logic GHRLastF;
|
||||
logic [k-1:0] GHRNextF, GHRNextD, GHRNextE;
|
||||
logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE;
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
|
||||
logic FlushDOrDirWrong;
|
||||
|
||||
assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
|
||||
assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
|
||||
assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(InstrClassE[0]),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
// and then register for use in the Fetch stage.
|
||||
assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
|
||||
MatchD ? {2{DirPredictionD[1]}} :
|
||||
NewDirPredictionE ;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
|
||||
// GHR pipeline
|
||||
|
||||
// If Fetch has a branch, speculatively insert prediction into the GHR
|
||||
// If the front end is flushed or the direction prediction is wrong, reset to
|
||||
// most recent valid GHR. For a BP wrong this is GHRD with the correct prediction shifted in.
|
||||
// For FlushE this is GHRE. GHRNextE is both.
|
||||
assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
|
||||
mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0],
|
||||
{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
|
||||
|
||||
// Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
|
||||
flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF);
|
||||
flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF);
|
||||
|
||||
// With instruction class prediction, the class could be wrong and is checked in Decode.
|
||||
// If it is wrong and branch does exist then shift right and insert the prediction.
|
||||
// If the branch does not exist then shift left and use GHRLastF to restore the LSB.
|
||||
logic [k-1:0] GHRClassWrong;
|
||||
mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, InstrClassD[0], GHRClassWrong);
|
||||
// As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
|
||||
mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);
|
||||
|
||||
flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD);
|
||||
|
||||
mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
|
||||
|
||||
flopenr #(k) GHREReg(clk, reset, ((InstrClassE[0] & ~FlushM) & ~StallE) | FlushE, GHRNextE, GHRE);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
|
||||
|
||||
endmodule
|
||||
@ -50,6 +50,7 @@ module ifu (
|
||||
output logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
|
||||
input logic PCSrcE, // Executation stage branch is taken
|
||||
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
|
||||
input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address
|
||||
output logic [`XLEN-1:0] PCE, // Execution stage instruction address
|
||||
output logic BPPredWrongE, // Prediction is wrong
|
||||
output logic BPPredWrongM, // Prediction is wrong
|
||||
@ -68,9 +69,10 @@ module ifu (
|
||||
output logic RASPredPCWrongM, // RAS prediction is wrong
|
||||
output logic PredictionInstrClassWrongM, // Class prediction is wrong
|
||||
// Faults
|
||||
input logic IllegalBaseInstrFaultD, // Illegal non-compressed instruction
|
||||
input logic IllegalBaseInstrD, // Illegal non-compressed instruction
|
||||
input logic IllegalFPUInstrD, // Illegal FP instruction
|
||||
output logic InstrPageFaultF, // Instruction page fault
|
||||
output logic IllegalIEUInstrFaultD, // Illegal instruction including compressed
|
||||
output logic IllegalIEUFPUInstrD, // Illegal instruction including compressed & FP
|
||||
output logic InstrMisalignedFaultM, // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
|
||||
// mmu management
|
||||
input logic [1:0] PrivilegeModeW, // Priviledge mode in Writeback stage
|
||||
@ -114,6 +116,7 @@ module ifu (
|
||||
logic CompressedE; // The execution instruction is compressed
|
||||
logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill
|
||||
logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage
|
||||
logic IllegalIEUInstrD; // IEU Instruction (regular or compressed) is not good
|
||||
|
||||
logic [1:0] IFURWF; // IFU alreays read IFURWF = 10
|
||||
logic [31:0] InstrE; // Instruction in the Execution stage
|
||||
@ -323,8 +326,9 @@ module ifu (
|
||||
if (`BPRED_SUPPORTED) begin : bpred
|
||||
bpred bpred(.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW,
|
||||
.FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE,
|
||||
.InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
|
||||
.FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE,
|
||||
.BranchD, .BranchE, .JumpD, .JumpE,
|
||||
.InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
|
||||
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
|
||||
|
||||
@ -346,11 +350,12 @@ module ifu (
|
||||
if (`C_SUPPORTED) begin
|
||||
logic IllegalCompInstrD;
|
||||
decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
|
||||
assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
|
||||
assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
|
||||
end else begin
|
||||
assign InstrD = InstrRawD;
|
||||
assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD;
|
||||
assign IllegalIEUInstrD = IllegalBaseInstrD;
|
||||
end
|
||||
assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
|
||||
|
||||
// Misaligned PC logic
|
||||
// Instruction address misalignement only from br/jal(r) instructions.
|
||||
|
||||
@ -33,8 +33,9 @@ module irom(
|
||||
output logic [31:0] IROMInstrF // Instruction read data
|
||||
);
|
||||
|
||||
localparam ADDR_WDITH = $clog2(`IROM_RANGE/8);
|
||||
localparam OFFSET = $clog2(`XLEN/8);
|
||||
localparam XLENBYTES = `XLEN/8;
|
||||
localparam ADDR_WDITH = $clog2(`IROM_RANGE/XLENBYTES);
|
||||
localparam OFFSET = $clog2(XLENBYTES);
|
||||
|
||||
logic [`XLEN-1:0] IROMInstrFFull;
|
||||
logic [31:0] RawIROMInstrF;
|
||||
|
||||
@ -42,12 +42,16 @@ module dtim(
|
||||
|
||||
logic we;
|
||||
|
||||
localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8);
|
||||
localparam OFFSET = $clog2(`LLEN/8);
|
||||
localparam LLENBYTES = `LLEN/8;
|
||||
// verilator lint_off WIDTH
|
||||
localparam DEPTH = `DTIM_RANGE/LLENBYTES;
|
||||
// verilator lint_on WIDTH
|
||||
localparam ADDR_WDITH = $clog2(DEPTH);
|
||||
localparam OFFSET = $clog2(LLENBYTES);
|
||||
|
||||
assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap.
|
||||
|
||||
ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN))
|
||||
ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(`LLEN))
|
||||
ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
|
||||
endmodule
|
||||
|
||||
|
||||
@ -107,15 +107,21 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
|
||||
.Cacheable, .Idempotent, .SelTIM,
|
||||
.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
|
||||
|
||||
pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.ExecuteAccessF, .WriteAccessM, .ReadAccessM,
|
||||
.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
|
||||
if (`PMP_ENTRIES > 0)
|
||||
pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.ExecuteAccessF, .WriteAccessM, .ReadAccessM,
|
||||
.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
|
||||
else begin
|
||||
assign PMPInstrAccessFaultF = 0;
|
||||
assign PMPStoreAmoAccessFaultM = 0;
|
||||
assign PMPLoadAccessFaultM = 0;
|
||||
end
|
||||
|
||||
// Access faults
|
||||
// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
|
||||
assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
|
||||
assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
|
||||
assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
|
||||
assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
|
||||
assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit);
|
||||
|
||||
// Misaligned faults
|
||||
|
||||
@ -49,15 +49,15 @@ module pmpchecker (
|
||||
output logic PMPStoreAmoAccessFaultM
|
||||
);
|
||||
|
||||
if (`PMP_ENTRIES > 0) begin
|
||||
// Bit i is high when the address falls in PMP region i
|
||||
logic EnforcePMP;
|
||||
logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
|
||||
logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
|
||||
logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null
|
||||
logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
|
||||
logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
|
||||
// Bit i is high when the address falls in PMP region i
|
||||
logic EnforcePMP;
|
||||
logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
|
||||
logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
|
||||
logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null
|
||||
logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
|
||||
logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
|
||||
|
||||
if (`PMP_ENTRIES > 0)
|
||||
pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
|
||||
.PhysicalAddress,
|
||||
.PMPCfg(PMPCFG_ARRAY_REGW),
|
||||
@ -66,17 +66,12 @@ module pmpchecker (
|
||||
.PAgePMPAdrOut(PAgePMPAdr),
|
||||
.Match, .Active, .L, .X, .W, .R);
|
||||
|
||||
priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
|
||||
priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
|
||||
|
||||
// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
|
||||
assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active;
|
||||
// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
|
||||
assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active;
|
||||
|
||||
assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
|
||||
assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ;
|
||||
assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ;
|
||||
end else begin
|
||||
assign PMPInstrAccessFaultF = 0;
|
||||
assign PMPStoreAmoAccessFaultM = 0;
|
||||
assign PMPLoadAccessFaultM = 0;
|
||||
end
|
||||
assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
|
||||
assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ;
|
||||
assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ;
|
||||
endmodule
|
||||
|
||||
@ -94,9 +94,9 @@ module csrc #(parameter
|
||||
assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
|
||||
assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong
|
||||
assign CounterEvent[11] = DCacheAccess & InstrValidNotFlushedM; // data cache access
|
||||
assign CounterEvent[12] = DCacheMiss & InstrValidNotFlushedM; // data cache miss
|
||||
assign CounterEvent[12] = DCacheMiss; // data cache miss. Miss asserted 1 cycle at start of cache miss
|
||||
assign CounterEvent[13] = ICacheAccess & InstrValidNotFlushedM; // instruction cache access
|
||||
assign CounterEvent[14] = ICacheMiss & InstrValidNotFlushedM; // instruction cache miss
|
||||
assign CounterEvent[14] = ICacheMiss; // instruction cache miss. Miss asserted 1 cycle at start of cache miss
|
||||
assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM; // branch predictor wrong
|
||||
assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
|
||||
end
|
||||
|
||||
@ -34,8 +34,7 @@ module privdec (
|
||||
input logic StallM,
|
||||
input logic [31:20] InstrM, // privileged instruction function field
|
||||
input logic PrivilegedM, // is this a privileged instruction (from IEU controller)
|
||||
input logic IllegalIEUInstrFaultM, // Not a legal IEU instruction
|
||||
input logic IllegalFPUInstrM, // Not a legal FPU instruction
|
||||
input logic IllegalIEUFPUInstrM, // Not a legal IEU instruction
|
||||
input logic IllegalCSRAccessM, // Not a legal CSR access
|
||||
input logic [1:0] PrivilegeModeW, // current privilege level
|
||||
input logic STATUS_TSR, STATUS_TVM, STATUS_TW, // status bits
|
||||
@ -85,6 +84,6 @@ module privdec (
|
||||
///////////////////////////////////////////
|
||||
|
||||
assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
|
||||
assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM |
|
||||
WFITimeoutM;
|
||||
assign IllegalInstrFaultM = IllegalIEUFPUInstrM | IllegalPrivilegedInstrM | IllegalCSRAccessM |
|
||||
WFITimeoutM;
|
||||
endmodule
|
||||
|
||||
@ -65,7 +65,7 @@ module privileged (
|
||||
input logic LoadPageFaultM, StoreAmoPageFaultM, // page faults
|
||||
input logic InstrMisalignedFaultM, // misaligned instruction fault
|
||||
input logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned data fault
|
||||
input logic IllegalIEUInstrFaultD, IllegalFPUInstrM, // illegal instruction faults
|
||||
input logic IllegalIEUFPUInstrD, // illegal instruction from IEU or FPU
|
||||
input logic MTimerInt, MExtInt, SExtInt, MSwInt, // interrupt sources
|
||||
input logic [63:0] MTIME_CLINT, // timer value from CLINT
|
||||
input logic [4:0] SetFflagsM, // set FCSR flags from FPU
|
||||
@ -95,7 +95,7 @@ module privileged (
|
||||
logic [11:0] MIDELEG_REGW; // interrupt delegation CSR
|
||||
logic sretM, mretM; // supervisor / machine return instruction
|
||||
logic IllegalCSRAccessM; // Illegal access to CSR
|
||||
logic IllegalIEUInstrFaultM; // Illegal IEU instruction, delayed to Mem stage
|
||||
logic IllegalIEUFPUInstrM; // Illegal IEU or FPU instruction, delayed to Mem stage
|
||||
logic InstrPageFaultM; // Instruction page fault, delayed to Mem stage
|
||||
logic InstrAccessFaultM; // Instruction access fault, delayed to Mem stages
|
||||
logic IllegalInstrFaultM; // Illegal instruction fault
|
||||
@ -115,7 +115,7 @@ module privileged (
|
||||
|
||||
// decode privileged instructions
|
||||
privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]),
|
||||
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM,
|
||||
.PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM,
|
||||
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
|
||||
.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM);
|
||||
|
||||
@ -137,8 +137,8 @@ module privileged (
|
||||
|
||||
// pipeline early-arriving trap sources
|
||||
privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD,
|
||||
.InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM);
|
||||
.InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUFPUInstrD,
|
||||
.InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUFPUInstrM);
|
||||
|
||||
// trap logic
|
||||
trap trap(.reset,
|
||||
|
||||
@ -33,24 +33,24 @@ module privpiperegs (
|
||||
input logic StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
input logic InstrPageFaultF, InstrAccessFaultF, // instruction faults
|
||||
input logic IllegalIEUInstrFaultD, // illegal IEU instruction decoded
|
||||
input logic IllegalIEUFPUInstrD, // illegal IEU instruction decoded
|
||||
output logic InstrPageFaultM, InstrAccessFaultM, // delayed instruction faults
|
||||
output logic IllegalIEUInstrFaultM // delayed illegal IEU instruction
|
||||
output logic IllegalIEUFPUInstrM // delayed illegal IEU instruction
|
||||
);
|
||||
|
||||
// Delayed fault signals
|
||||
logic InstrPageFaultD, InstrAccessFaultD;
|
||||
logic InstrPageFaultE, InstrAccessFaultE;
|
||||
logic IllegalIEUInstrFaultE;
|
||||
logic IllegalIEUFPUInstrE;
|
||||
|
||||
// pipeline fault signals
|
||||
flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
|
||||
{InstrPageFaultF, InstrAccessFaultF},
|
||||
{InstrPageFaultD, InstrAccessFaultD});
|
||||
flopenrc #(3) faultregE(clk, reset, FlushE, ~StallE,
|
||||
{IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD},
|
||||
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE});
|
||||
{IllegalIEUFPUInstrD, InstrPageFaultD, InstrAccessFaultD},
|
||||
{IllegalIEUFPUInstrE, InstrPageFaultE, InstrAccessFaultE});
|
||||
flopenrc #(3) faultregM(clk, reset, FlushM, ~StallM,
|
||||
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE},
|
||||
{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM});
|
||||
{IllegalIEUFPUInstrE, InstrPageFaultE, InstrAccessFaultE},
|
||||
{IllegalIEUFPUInstrM, InstrPageFaultM, InstrAccessFaultM});
|
||||
endmodule
|
||||
@ -70,7 +70,7 @@ module wallypipelinedcore (
|
||||
logic [1:0] MemRWM;
|
||||
logic InstrValidD, InstrValidE, InstrValidM;
|
||||
logic InstrMisalignedFaultM;
|
||||
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
|
||||
logic IllegalBaseInstrD, IllegalFPUInstrD, IllegalIEUFPUInstrD;
|
||||
logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
|
||||
logic LoadMisalignedFaultM, LoadAccessFaultM;
|
||||
logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
|
||||
@ -91,7 +91,6 @@ module wallypipelinedcore (
|
||||
logic [`XLEN-1:0] FCvtIntResW;
|
||||
logic FCvtIntW;
|
||||
logic FDivBusyE;
|
||||
logic IllegalFPUInstrM;
|
||||
logic FRegWriteM;
|
||||
logic FCvtIntStallD;
|
||||
logic FpLoadStoreM;
|
||||
@ -172,13 +171,13 @@ module wallypipelinedcore (
|
||||
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
|
||||
.ICacheAccess, .ICacheMiss,
|
||||
// Execute
|
||||
.PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, .BPPredWrongM,
|
||||
.PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPPredWrongE, .BPPredWrongM,
|
||||
// Mem
|
||||
.CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
|
||||
.InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,
|
||||
.BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||
// Faults out
|
||||
.IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
|
||||
.IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
|
||||
// mmu management
|
||||
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
|
||||
.STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
|
||||
@ -188,7 +187,7 @@ module wallypipelinedcore (
|
||||
// integer execution unit: integer register file, datapath and controller
|
||||
ieu ieu(.clk, .reset,
|
||||
// Decode Stage interface
|
||||
.InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
|
||||
.InstrD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
|
||||
// Execute Stage interface
|
||||
.PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
|
||||
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE,
|
||||
@ -291,12 +290,12 @@ module wallypipelinedcore (
|
||||
.RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||
.InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
||||
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
|
||||
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD,
|
||||
.InstrMisalignedFaultM, .IllegalIEUFPUInstrD,
|
||||
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
|
||||
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
|
||||
.MTIME_CLINT, .IEUAdrM, .SetFflagsM,
|
||||
.InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
|
||||
.IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW,
|
||||
.PrivilegeModeW, .SATP_REGW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
|
||||
@ -344,7 +343,7 @@ module wallypipelinedcore (
|
||||
.FCvtIntResW, // fp -> int conversion result to be stored in int register
|
||||
.FCvtIntW, // fpu result selection
|
||||
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
|
||||
.IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
|
||||
.IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
|
||||
.SetFflagsM, // FPU flags (to privileged unit)
|
||||
.FIntDivResultW);
|
||||
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
|
||||
@ -354,7 +353,7 @@ module wallypipelinedcore (
|
||||
assign FIntResM = 0;
|
||||
assign FCvtIntW = 0;
|
||||
assign FDivBusyE = 0;
|
||||
assign IllegalFPUInstrM = 1;
|
||||
assign IllegalFPUInstrD = 1;
|
||||
assign SetFflagsM = 0;
|
||||
assign FpLoadStoreM = 0;
|
||||
end
|
||||
|
||||
@ -74,6 +74,7 @@ else
|
||||
sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh
|
||||
sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh
|
||||
sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh
|
||||
sed -i 's/BTB_SIZE.*/BTB_SIZE 5/g' $(CONFIGDIR)/wally-config.vh
|
||||
ifneq ($(filter $(CONFIG), $(DIRS32)),)
|
||||
sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
|
||||
sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
|
||||
@ -91,6 +92,7 @@ endif
|
||||
# when mod = noPriv, the privileged unit and PMP are disabled
|
||||
# when mod = noFPU, the FPU, privileged unit, and PMP are disabled
|
||||
# when mod = noMulDiv, the MDU, FPU, privileged unit, and PMP are disabled.
|
||||
# when mod = noAtomic, the Atomic, MDU, FPU, privileged unit, and PMP are disabled
|
||||
|
||||
ifneq ($(MOD), orig)
|
||||
# PMP 0
|
||||
@ -105,6 +107,10 @@ ifneq ($(MOD), noPriv)
|
||||
ifneq ($(MOD), noFPU)
|
||||
# no muldiv
|
||||
sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh
|
||||
ifneq ($(MOD), noMulDiv)
|
||||
# no atomic
|
||||
sed -i 's/1 *<< *0/0 << 0/' $(CONFIGDIR)/wally-config.vh
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
118
synthDC/extractArea.pl
Executable file
118
synthDC/extractArea.pl
Executable file
@ -0,0 +1,118 @@
|
||||
#!/bin/perl -W
|
||||
|
||||
###########################################
|
||||
## extractArea.pl
|
||||
##
|
||||
## Written: David_Harris@hmc.edu
|
||||
## Created: 19 Feb 2023
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Pull area statistics from run directory
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
|
||||
use strict;
|
||||
use warnings;
|
||||
import os;
|
||||
|
||||
my %configResults;
|
||||
my $dir = "runs";
|
||||
my $macro = "Macro/Black Box area:";
|
||||
my $seq = "Noncombinational area:";
|
||||
my $buf = "Buf/Inv area:";
|
||||
my $comb = "Combinational area:";
|
||||
my $macroC = "Number of macros/black boxes:";
|
||||
my $seqC = "Number of sequential cells:";
|
||||
my $bufC = "Number of buf/inv:";
|
||||
my $combC = "Number of combinational cells:";
|
||||
my @keywords = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore", $macro, $seq, $buf, $comb, $macroC, $seqC, $bufC, $combC);
|
||||
my @keywordsp = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore",
|
||||
"RAMs", "Flip-flops", "Inv/Buf", "Logic", "RAMs Cnt", "Flip-flops Cnt", "Inv/Buf Cnt", "Logic Cnt", "Total Cnt");
|
||||
my @configs = ("rv32e", "rv32i", "rv32imc", "rv32gc", "rv64i", "rv64gc");
|
||||
|
||||
opendir(DIR, $dir) or die "Could not open $dir";
|
||||
|
||||
while (my $filename = readdir(DIR)) {
|
||||
if ($filename =~ /orig_tsmc28psyn/) {
|
||||
# if ($filename =~ /orig_sky90/) {
|
||||
&processRun("$dir/$filename");
|
||||
}
|
||||
}
|
||||
closedir(DIR);
|
||||
|
||||
# print table of results
|
||||
printf("%20s\t", "");
|
||||
foreach my $config (@configs) {
|
||||
printf("%s\t", $config);
|
||||
}
|
||||
print ("\n");
|
||||
foreach my $kw (@keywordsp) {
|
||||
my $kws = substr($kw, 0, 3);
|
||||
printf("%20s\t", $kw);
|
||||
foreach my $config (@configs) {
|
||||
my $r = $configResults{$config};
|
||||
if (exists ${$r}{$kw}) {
|
||||
my $area = ${$r}{$kw};
|
||||
while ($area =~ s/(\d+)(\d\d\d)/$1\,$2/){};
|
||||
#print "${$r}{$kw}\t";
|
||||
print "$area\t";
|
||||
} else {
|
||||
print("\t");
|
||||
}
|
||||
}
|
||||
print("\n");
|
||||
}
|
||||
|
||||
sub processRun {
|
||||
my $fname = shift;
|
||||
my $ffname = "$fname/reports/area.rep";
|
||||
open(FILE, "$ffname") or die ("Could not read $ffname");
|
||||
|
||||
# Extract configuration from fname;
|
||||
$fname =~ /_([^_]*)_orig/;
|
||||
my $config = $1;
|
||||
#print("Reading $config from $ffname\n");
|
||||
|
||||
# Search for results
|
||||
my %results;
|
||||
while (my $line = <FILE>) {
|
||||
foreach my $kw (@keywords) {
|
||||
# print "$kw $line\n";
|
||||
if ($line =~ /^${kw}\s+(\S*)/) {
|
||||
#print "$line $kw $1\n";
|
||||
$results{$kw} = int($1);
|
||||
}
|
||||
}
|
||||
}
|
||||
foreach my $kw (@keywords) {
|
||||
#print "$kw\t$results{$kw}\n";
|
||||
}
|
||||
$results{"Logic"} = $results{$comb} - $results{$buf};
|
||||
$results{"Inv/Buf"} = $results{$buf};
|
||||
$results{"Flip-flops"} = $results{$seq};
|
||||
$results{"RAMs"} = $results{$macro};
|
||||
$results{"Logic Cnt"} = $results{$combC} - $results{$bufC};
|
||||
$results{"Inv/Buf Cnt"} = $results{$bufC};
|
||||
$results{"Flip-flops Cnt"} = $results{$seqC};
|
||||
$results{"RAMs Cnt"} = $results{$macroC};
|
||||
$results{"Total Cnt"} = $results{$macroC} + $results{$seqC} + $results{$combC};
|
||||
close(FILE);
|
||||
$configResults{$config} = \%results;
|
||||
}
|
||||
@ -141,7 +141,7 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
|
||||
if norm:
|
||||
delays = [d/fo4 for d in delays]
|
||||
areas = [a/add32area for a in areas]
|
||||
|
||||
|
||||
plt.scatter(delays, areas, marker=marker, color=color)
|
||||
plt.xlabel('Cycle time (ns)')
|
||||
plt.ylabel('Area (sq microns)')
|
||||
@ -165,6 +165,9 @@ def plotFeatures(tech, width, config):
|
||||
areas += [oneSynth.area]
|
||||
labels += [oneSynth.mod]
|
||||
|
||||
if (delays == []):
|
||||
print("No delays found for freq ", freq, ". Did you set --skyfreq and --tsmcfreq?\n")
|
||||
|
||||
fig, (ax) = plt.subplots(1, 1)
|
||||
|
||||
fig = areaDelay(tech, delays, areas, labels, fig, ax)
|
||||
@ -185,6 +188,7 @@ def plotConfigs(tech, mod=''):
|
||||
|
||||
fig, (ax) = plt.subplots(1, 1)
|
||||
|
||||
|
||||
fig = areaDelay(tech, delays, areas, labels, fig, ax)
|
||||
|
||||
titleStr = tech+'_'+mod
|
||||
@ -263,3 +267,4 @@ if __name__ == '__main__':
|
||||
plotConfigs('sky90', mod='orig')
|
||||
plotConfigs('tsmc28psyn', mod='orig')
|
||||
normAreaDelay(mod='orig')
|
||||
os.system("./extractArea.pl");
|
||||
|
||||
@ -116,7 +116,7 @@ if { $find_clock != [list] } {
|
||||
}
|
||||
|
||||
# Optimize paths that are close to critical
|
||||
set_critical_range [expr $my_period*0.05] $current_design
|
||||
set_critical_range 0.05 $current_design
|
||||
|
||||
# Partitioning - flatten or hierarchically synthesize
|
||||
if { $maxopt == 1 } {
|
||||
@ -227,7 +227,7 @@ set write_cst 1 ;# generate report of constraints
|
||||
set write_hier 1 ;# generate hierarchy report
|
||||
|
||||
# Report Constraint Violators
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint_all_violators.rpt"]
|
||||
set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"]
|
||||
redirect $filename {report_constraint -all_violators}
|
||||
|
||||
# Check design
|
||||
@ -247,23 +247,23 @@ set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"]
|
||||
write_sdf $filename
|
||||
|
||||
# QoR
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_qor.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/qor.rep"]
|
||||
redirect $filename { report_qor }
|
||||
|
||||
# Report Timing
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_reportpath.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/reportpath.rep"]
|
||||
#redirect $filename { report_path_group }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_report_clock.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/report_clock.rep"]
|
||||
# redirect $filename { report_clock }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_timing.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/timing.rep"]
|
||||
redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mindelay.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/mindelay.rep"]
|
||||
redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_per_module_timing.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/per_module_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" }
|
||||
@ -281,7 +281,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fpu ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mdu_timing.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/mdu_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through entire mdu ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through multiply unit ////\n\n\n" }
|
||||
@ -305,7 +305,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through div/DAbsBE ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 }
|
||||
|
||||
# set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"]
|
||||
# set filename [format "%s%s%s%s" $outputDir "/reports/fpu_timing.rep"]
|
||||
# redirect $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
|
||||
@ -313,90 +313,87 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ifu_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 }
|
||||
# set filename [format "%s%s%s%s" $outputDir "/reports/ifu_timing.rep"]
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_stall_flush_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 }
|
||||
# set filename [format "%s%s%s%s" $outputDir "/reports/stall_flush_timing.rep"]
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ieu_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 }
|
||||
# set filename [format "%s%s%s%s" $outputDir "/reports/ieu_timing.rep"]
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {postprocess/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {divsqrt/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 }
|
||||
# set filename [format "%s%s%s%s" $outputDir "/reports/fpu_timing.rep"]
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {postprocess/*} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {divsqrt/*} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mmu_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 }
|
||||
# set filename [format "%s%s%s%s" $outputDir "/reports/mmu_timing.rep"]
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_priv_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 }
|
||||
# set filename [format "%s%s%s%s" $outputDir "/reports/priv_timing.rep"]
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 }
|
||||
# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" }
|
||||
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_min_timing.rep"]
|
||||
redirect $filename { report_timing -delay min }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_area.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/area.rep"]
|
||||
redirect $filename { report_area -hierarchy -nosplit -physical -designware}
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_cell.rep"]
|
||||
# redirect $filename { report_cell [get_cells -hier *] }
|
||||
set filename [format "%s%s" $outputDir "/reports/cell.rep"]
|
||||
#redirect $filename { report_cell [get_cells -hier *] } # not too useful
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_power.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/power.rep"]
|
||||
redirect $filename { report_power -hierarchy -levels 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/constraint.rep"]
|
||||
redirect $filename { report_constraint }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"]
|
||||
set filename [format "%s%s" $outputDir "/reports/hier.rep"]
|
||||
# redirect $filename { report_hierarchy }
|
||||
|
||||
# end run clock and echo run time in minutes
|
||||
|
||||
@ -56,7 +56,7 @@ if __name__ == '__main__':
|
||||
defaultfreq = 500 if tech == 'sky90' else 1500
|
||||
freq = args.targetfreq if args.targetfreq else defaultfreq
|
||||
config = args.version if args.version else 'rv64gc'
|
||||
for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']:
|
||||
for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'PMP0']:
|
||||
runSynth(config, mod, tech, freq, maxopt, usesram)
|
||||
else:
|
||||
defaultfreq = 500 if tech == 'sky90' else 1500
|
||||
|
||||
@ -28,8 +28,8 @@
|
||||
`include "wally-config.vh"
|
||||
`include "tests.vh"
|
||||
|
||||
`define PrintHPMCounters 0
|
||||
`define BPRED_LOGGER 0
|
||||
`define PrintHPMCounters 1
|
||||
`define BPRED_LOGGER 1
|
||||
|
||||
module testbench;
|
||||
parameter DEBUG=0;
|
||||
@ -470,13 +470,36 @@ logic [3:0] dummy;
|
||||
.start(DCacheFlushStart),
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_SUPPORTED == 1)
|
||||
begin
|
||||
genvar adrindex;
|
||||
|
||||
if (`BPRED_SUPPORTED == 1) begin
|
||||
integer adrindex;
|
||||
|
||||
always @(*) begin
|
||||
if(reset) begin
|
||||
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
|
||||
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
|
||||
end
|
||||
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
|
||||
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
|
||||
end
|
||||
#1;
|
||||
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
|
||||
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
|
||||
end
|
||||
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
|
||||
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
if (`BPRED_SUPPORTED == 1) begin
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
genvar adrindex;
|
||||
// Initializing all zeroes into the branch predictor memory.
|
||||
for(adrindex = 0; adrindex < 2**10; adrindex++) begin
|
||||
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
|
||||
initial begin
|
||||
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
|
||||
#1;
|
||||
@ -490,6 +513,7 @@ logic [3:0] dummy;
|
||||
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
|
||||
end
|
||||
end
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
if (`BPRED_LOGGER) begin
|
||||
string direction;
|
||||
|
||||
@ -50,6 +50,8 @@ string tvpaths[] = '{
|
||||
|
||||
string embench[] = '{
|
||||
`EMBENCH,
|
||||
"bd_speedopt_speed/src/nsichneu/nsichneu",
|
||||
"bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
|
||||
"bd_speedopt_speed/src/aha-mont64/aha-mont64",
|
||||
"bd_speedopt_speed/src/crc32/crc32",
|
||||
"bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
|
||||
@ -61,7 +63,6 @@ string tvpaths[] = '{
|
||||
"bd_speedopt_speed/src/nettle-aes/nettle-aes",
|
||||
"bd_speedopt_speed/src/nettle-sha256/nettle-sha256",
|
||||
"bd_speedopt_speed/src/nbody/nbody",
|
||||
"bd_speedopt_speed/src/nsichneu/nsichneu",
|
||||
"bd_speedopt_speed/src/picojpeg/picojpeg",
|
||||
// "bd_speedopt_speed/src/primecount/primecount",
|
||||
"bd_speedopt_speed/src/qrduino/qrduino",
|
||||
|
||||
@ -4,6 +4,7 @@ TARGET = debug
|
||||
|
||||
$(TARGET).signature.output: $(TARGET).elf.memfile $(TARGET).elf
|
||||
spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=4 $(TARGET).elf
|
||||
riscv_sim_RV64 debug.elf -T debug.sig
|
||||
# diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
|
||||
# echo "Signature matches! Success!"
|
||||
mkdir -p ../work
|
||||
|
||||
@ -18,24 +18,29 @@ rvtest_entry_point:
|
||||
fsd f12, 0(a6)
|
||||
|
||||
# openhwgroup/cvw Issue #56
|
||||
fld f4, 16(a7)
|
||||
fld f4, 16(a7) # cfa695b1047553b1
|
||||
fld f14, 24(a7)
|
||||
fsgnjx.s f10,f4,f14 # expected f 0xffffffff7fc00000, hdl has been giving 0xcfa695b1047553b1
|
||||
fsd f19, 8(a6)
|
||||
fsd f19, 16(a6)
|
||||
|
||||
# openhwgroup/cvw Issue #57
|
||||
fld f0, 32(a7)
|
||||
fld f15, 40(a7)
|
||||
fsgnjx.s f30,f0,f15 # expected f 0xfffffffffb3754ef, hdl has been giving 0xffffffff7b3754ef
|
||||
fsd f30, 16(a6)
|
||||
fsd f30, 24(a6)
|
||||
|
||||
# openhwgroup/cvw Issue #58
|
||||
fld f14, 48(a7)
|
||||
fclass.s x2, f14 # expected 0x0000000000000200, hdl had been giving 0x0000000000000220
|
||||
sd x2, 24(a6)
|
||||
sd x2, 32(a6)
|
||||
|
||||
# fsgnjx.s, fclass.s, fsgnjn.s, fsgnj.s, fneg.s, fabs.s, fmv.s all treat inputs as dp rather than sp
|
||||
|
||||
#openhwgroup/cvw Issue #65 #expected 0xffffffffffffffff, hdl had been giving 0x00000000ffffffff
|
||||
fld f17, 56(a7)
|
||||
fmv.x.s x30, f17
|
||||
sd x30, 40(a6)
|
||||
|
||||
|
||||
#########################
|
||||
# HTIF and signature
|
||||
@ -66,6 +71,7 @@ rvtest_data:
|
||||
.dword 0xffffffff7fc00000
|
||||
.dword 0xfffffffffb3754ef
|
||||
.dword 0x7fefffffffffffff
|
||||
.dword 0x00000000ffffffff
|
||||
|
||||
.EQU XLEN,64
|
||||
begin_signature:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user