Updated source code to be compatible with verilator 5.011 for lint only.

config/shared/BranchPredictorType.vh

@@ -1,3 +1,3 @@
-typedef enum  {BP_TWOBIT, BP_GSHARE, BP_GLOBAL, BP_GSHARE_BASIC, 
+typedef enum logic[3:0] {BP_TWOBIT, BP_GSHARE, BP_GLOBAL, BP_GSHARE_BASIC, 
                BP_GLOBAL_BASIC, BP_LOCAL_BASIC, BP_LOCAL_AHEAD, BP_LOCAL_REPAIR} BranchPredictorType;
 

config/shared/parameter-defs.vh

@@ -72,7 +72,11 @@ parameter cvw_t P = '{
   PLIC_GPIO_ID :        PLIC_GPIO_ID,
   PLIC_UART_ID :        PLIC_UART_ID,
   BPRED_SUPPORTED :        BPRED_SUPPORTED,
+                       /* verilator lint_off ENUMVALUE */
+                       // *** definitely need to fix this.
+                       // it thinks we are casting from the enum type to BPRED_TYPE.
   BPRED_TYPE :        BPRED_TYPE,
+                       /* verilator lint_off ENUMVALUE */
   BPRED_SIZE :        BPRED_SIZE,
   BPRED_NUM_LHR : BPRED_NUM_LHR,                       
   BTB_SIZE :        BTB_SIZE,

src/ifu/bpred/RASPredictor.sv

@@ -27,7 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module RASPredictor import cvw::*;  #(parameter cvw_t P, StackSize = 16 )(
+module RASPredictor import cvw::*;  #(parameter cvw_t P, 
+                                      parameter StackSize = 16 )(
   input  logic             clk,
   input  logic             reset, 
   input  logic             StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,

src/ifu/bpred/btb.sv

@@ -28,7 +28,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module btb import cvw::*;  #(parameter cvw_t P, Depth = 10 ) (
+module btb import cvw::*;  #(parameter cvw_t P, 
+                             parameter Depth = 10 ) (
   input  logic             clk,
   input  logic             reset,
   input  logic             StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,

src/ifu/bpred/icpred.sv

@@ -26,7 +26,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module icpred import cvw::*;  #(parameter cvw_t P, INSTR_CLASS_PRED = 1)(
+module icpred import cvw::*;  #(parameter cvw_t P, 
+                                parameter INSTR_CLASS_PRED = 1)(
   input  logic             clk, reset,
   input  logic             StallF, StallD, StallE, StallM, StallW,
   input  logic             FlushD, FlushE, FlushM, FlushW,

src/mmu/tlb/tlbcam.sv

@@ -29,7 +29,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module tlbcam  import cvw::*;  #(parameter cvw_t P, TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
+module tlbcam  import cvw::*;  #(parameter cvw_t P,
+                                 parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
   input  logic                    clk, reset,
   input  logic [P.VPN_BITS-1:0]    VPN,
   input  logic [1:0]              PageTypeWriteVal,

src/mmu/tlb/tlbcamline.sv

@@ -29,7 +29,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module tlbcamline import cvw::*;  #(parameter cvw_t P, KEY_BITS = 20, SEGMENT_BITS = 10) (
+module tlbcamline import cvw::*;  #(parameter cvw_t P, 
+                                    parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
   input  logic                  clk, reset,
   input  logic [P.VPN_BITS-1:0]  VPN, // The requested page number to compare against the key
   input  logic [P.ASID_BITS-1:0] SATP_ASID,

src/mmu/tlb/tlbram.sv

@@ -29,7 +29,8 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 
-module tlbram import cvw::*;  #(parameter cvw_t P, TLB_ENTRIES = 8) (
+module tlbram import cvw::*;  #(parameter cvw_t P, 
+                                parameter TLB_ENTRIES = 8) (
   input  logic                      clk, reset,
   input  logic [P.XLEN-1:0]          PTE,
   input  logic [TLB_ENTRIES-1:0]    Matches, WriteEnables,

src/privileged/csr.sv

@@ -28,7 +28,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module csr import cvw::*;  #(parameter cvw_t P, MIP = 12'h344, SIP = 12'h144) (
+module csr import cvw::*;  #(parameter cvw_t P) (
   input  logic             clk, reset,
   input  logic             FlushM, FlushW,
   input  logic             StallE, StallM, StallW,
@@ -91,6 +91,9 @@ module csr import cvw::*;  #(parameter cvw_t P, MIP = 12'h344, SIP = 12'h144) (
   output logic             BigEndianM                 // memory access is big-endian based on privilege mode and STATUS register endian fields
 );
 
+  localparam MIP = 12'h344;
+  localparam SIP = 12'h144;
+  
   logic [P.XLEN-1:0]        CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
   logic [P.XLEN-1:0]        CSRReadValM;  
   logic [P.XLEN-1:0]        CSRSrcM;

src/uncore/ahbapbbridge.sv

@@ -25,7 +25,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module ahbapbbridge import cvw::*;  #(parameter cvw_t P, PERIPHS = 2) (
+module ahbapbbridge import cvw::*;  #(parameter cvw_t P, 
+                                      parameter PERIPHS = 2) (
   input  logic                HCLK, HRESETn,
   input  logic [PERIPHS-1:0]  HSEL,  
   input  logic [P.PA_BITS-1:0] HADDR, 

src/wally/wallypipelinedsoc.sv

@@ -28,7 +28,6 @@
 
 `include "config.vh"
 //import cvw::*;  // global CORE-V-Wally parameters
-`include "wally-config.vh"
 
 module wallypipelinedsoc import cvw::*;  (
   input  logic                clk,