Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.

src/cache/cachefsm.sv

@@ -92,7 +92,8 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   assign FlushFlag = FlushAdrFlag & FlushWayFlag;
 
   // outputs for the performance counters.
-  assign CacheAccess = (|CacheRW) & CurrState == STATE_READY; // exclusion-tag: icache CacheW
+  assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) |
+                                     (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
   assign CacheMiss = CacheAccess & ~CacheHit;
 
   // special case on reset. When the fsm first exists reset the

src/privileged/csrc.sv

@@ -101,10 +101,10 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
     assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;                      // instruction class predictor wrong
     assign CounterEvent[11] = LoadStallM;                                                // Load Stalls. don't want to suppress on flush as this only happens if flushed.
     assign CounterEvent[12] = StoreStallM;                                               //  Store Stall
-    assign CounterEvent[13] = DCacheAccess & InstrValidNotFlushedM;                      // data cache access
+    assign CounterEvent[13] = DCacheAccess;                                              // data cache access
     assign CounterEvent[14] = DCacheMiss;                                                // data cache miss. Miss asserted 1 cycle at start of cache miss
     assign CounterEvent[15] = DCacheStallM;                                              // d cache miss cycles
-    assign CounterEvent[16] = ICacheAccess & InstrValidNotFlushedM;                      // instruction cache access
+    assign CounterEvent[16] = ICacheAccess;                                              // instruction cache access
     assign CounterEvent[17] = ICacheMiss;                                                // instruction cache miss. Miss asserted 1 cycle at start of cache miss
     assign CounterEvent[18] = ICacheStallF;                                              // i cache miss cycles
     assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM;                         // CSR writes
@@ -187,4 +187,4 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
     end
 endmodule
 
-//  mounteren should only exist if u-mode exists
+//  mounteren should only exist if u-mode exists