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Trying to figure out why the parameterization slowed down modelsim so much.

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Ross Thompson 2023-05-24 12:44:42 -05:00
parent 69a9bf7055
commit 930fb67308
16 changed files with 1940 additions and 181 deletions
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//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
localparam FPGA = 1;
localparam QEMU = 0;
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32'd64;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam MISA = (32'h0014112D);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;
localparam DCACHE_SUPPORTED = 1;
localparam ICACHE_SUPPORTED = 1;
localparam VIRTMEM_SUPPORTED = 1;
localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ;
localparam BIGENDIAN_SUPPORTED = 1;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 32'd32;
localparam DTLB_ENTRIES = 32'd32;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 32'd4;
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
localparam DCACHE_LINELENINBITS = 32'd512;
localparam ICACHE_NUMWAYS = 32'd4;
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
localparam ICACHE_LINELENINBITS = 32'd512;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 32'd4;
localparam IDIV_ON_FPU = 1;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 32'd16;
// Address space
localparam RESET_VECTOR = 64'h0000000000001000;
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
localparam DTIM_SUPPORTED = 1'b0;
localparam DTIM_BASE = 64'h80000000;
localparam DTIM_RANGE = 64'h00001FFF;
localparam IROM_SUPPORTED = 1'b0;
localparam IROM_BASE = 64'h80000000;
localparam IROM_RANGE = 64'h00001FFF;
localparam BOOTROM_SUPPORTED = 1'b1;
localparam BOOTROM_BASE = 64'h00001000 ;
localparam BOOTROM_RANGE = 64'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam UNCORE_RAM_BASE = 64'h80000000;
localparam UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam EXT_MEM_BASE = 64'h80000000;
localparam EXT_MEM_RANGE = 64'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b1;
localparam CLINT_BASE = 64'h02000000;
localparam CLINT_RANGE = 64'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b1;
localparam GPIO_BASE = 64'h10060000;
localparam GPIO_RANGE = 64'h000000FF;
localparam UART_SUPPORTED = 1'b1;
localparam UART_BASE = 64'h10000000;
localparam UART_RANGE = 64'h00000007;
localparam PLIC_SUPPORTED = 1'b1;
localparam PLIC_BASE = 64'h0C000000;
localparam PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam SDC_BASE = 64'h00012100;
localparam SDC_RANGE = 64'h0000001F;
// Bus Interface width
localparam AHBW = 32'd64;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 0;
// Hardware configuration
localparam UART_PRESCALE = 32'd0;
// Interrupt configuration
localparam PLIC_NUM_SRC = 32'd53;
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_UART_ID = 32'd10;
localparam PLIC_GPIO_ID = 32'd3;
localparam BPRED_SUPPORTED = 1;
localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT;
localparam BPRED_SIZE = 32'd10;
localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 1;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'h4;
localparam DIVCOPIES = 32'h4;
// bit manipulation
localparam ZBA_SUPPORTED = 0;
localparam ZBB_SUPPORTED = 0;
localparam ZBC_SUPPORTED = 0;
localparam ZBS_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;
`include "test-shared.vh"

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//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
localparam FPGA = 0;
localparam QEMU = 0;
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
// E
localparam MISA = (32'h00000010);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd0;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;
localparam DCACHE_SUPPORTED = 0;
localparam ICACHE_SUPPORTED = 0;
localparam VIRTMEM_SUPPORTED = 0;
localparam VECTORED_INTERRUPTS_SUPPORTED = 0;
localparam BIGENDIAN_SUPPORTED = 0;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 32'd0;
localparam DTLB_ENTRIES = 32'd0;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 32'd4;
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
localparam DCACHE_LINELENINBITS = 32'd512;
localparam ICACHE_NUMWAYS = 32'd4;
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
localparam ICACHE_LINELENINBITS = 32'd512;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 32'd1;
localparam IDIV_ON_FPU = 0;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 32'd0;
// Address space
localparam RESET_VECTOR = 64'h80000000;
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
localparam DTIM_SUPPORTED = 1'b0;
localparam DTIM_BASE = 64'h80000000;
localparam DTIM_RANGE = 64'h007FFFFF;
localparam IROM_SUPPORTED = 1'b0;
localparam IROM_BASE = 64'h80000000;
localparam IROM_RANGE = 64'h007FFFFF;
localparam BOOTROM_SUPPORTED = 1'b1;
localparam BOOTROM_BASE = 64'h00001000;
localparam BOOTROM_RANGE = 64'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam UNCORE_RAM_BASE = 64'h80000000;
localparam UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam EXT_MEM_BASE = 64'h80000000;
localparam EXT_MEM_RANGE = 64'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b0;
localparam CLINT_BASE = 64'h02000000;
localparam CLINT_RANGE = 64'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b0;
localparam GPIO_BASE = 64'h10060000;
localparam GPIO_RANGE = 64'h000000FF;
localparam UART_SUPPORTED = 1'b0;
localparam UART_BASE = 64'h10000000;
localparam UART_RANGE = 64'h00000007;
localparam PLIC_SUPPORTED = 1'b0;
localparam PLIC_BASE = 64'h0C000000;
localparam PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam SDC_BASE = 64'h00012100;
localparam SDC_RANGE = 64'h0000001F;
// Bus Interface width
localparam AHBW = 32'd32;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
// Hardware configuration
localparam UART_PRESCALE = 32'd1;
// Interrupt configuration
localparam PLIC_NUM_SRC = 32'd10;
// comment out the following if >=32 sources
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_GPIO_ID = 32'd3;
localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 0;
localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N
localparam BPRED_SIZE = 32'd10;
localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'd4;
localparam DIVCOPIES = 32'd4;
// bit manipulation
localparam ZBA_SUPPORTED = 0;
localparam ZBB_SUPPORTED = 0;
localparam ZBC_SUPPORTED = 0;
localparam ZBS_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;
`include "test-shared.vh"

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//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
localparam PA_BITS = 34;
//localparam AHBW = 32;
//localparam XLEN = 32;
//localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
////localparam BUS_SUPPORTED = 1'b1;
//localparam ZICSR_SUPPORTED = 1'b0;
localparam M_SUPPORTED = 1'b0;
localparam F_SUPPORTED = 1'b0;
//localparam ZMMUL_SUPPORTED = 1'b0;
//localparam F_SUPPORTED = 1'b0;
//localparam PMP_ENTRIES = 0;
localparam LLEN = 32;
//localparam FPGA = 1'b0;
//localparam QEMU = 1'b0;
// //VPN_SEGMENT_BITS: (LLEN == 32 ? 10 : 9),
// `include "test-shared.vh"
localparam FLEN = 32;
`include "test-shared.vh"
// include shared configuration
//`include "wally-shared.vh"
localparam FPGA = 0;
localparam QEMU = 0;
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32;
// IEEE 754 compliance
localparam IEEE754 = 0;
// E
localparam MISA = (32'h00000010);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 0;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;
localparam DCACHE_SUPPORTED = 0;
localparam ICACHE_SUPPORTED = 0;
localparam VIRTMEM_SUPPORTED = 0;
localparam VECTORED_INTERRUPTS_SUPPORTED = 0;
localparam BIGENDIAN_SUPPORTED = 0;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 0;
localparam DTLB_ENTRIES = 0;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 4;
localparam DCACHE_WAYSIZEINBYTES = 4096;
localparam DCACHE_LINELENINBITS = 512;
localparam ICACHE_NUMWAYS = 4;
localparam ICACHE_WAYSIZEINBYTES = 4096;
localparam ICACHE_LINELENINBITS = 512;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 1;
localparam IDIV_ON_FPU = 0;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 0;
// Address space
localparam RESET_VECTOR = 32'h80000000;
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 16;
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
localparam DTIM_SUPPORTED = 1'b0;
localparam DTIM_BASE = 34'h80000000;
localparam DTIM_RANGE = 34'h007FFFFF;
localparam IROM_SUPPORTED = 1'b0;
localparam IROM_BASE = 34'h80000000;
localparam IROM_RANGE = 34'h007FFFFF;
localparam BOOTROM_SUPPORTED = 1'b1;
localparam BOOTROM_BASE = 34'h00001000;
localparam BOOTROM_RANGE = 34'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam UNCORE_RAM_BASE = 34'h80000000;
localparam UNCORE_RAM_RANGE = 34'h07FFFFFF;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam EXT_MEM_BASE = 34'h80000000;
localparam EXT_MEM_RANGE = 34'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b0;
localparam CLINT_BASE = 34'h02000000;
localparam CLINT_RANGE = 34'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b0;
localparam GPIO_BASE = 34'h10060000;
localparam GPIO_RANGE = 34'h000000FF;
localparam UART_SUPPORTED = 1'b0;
localparam UART_BASE = 34'h10000000;
localparam UART_RANGE = 34'h00000007;
localparam PLIC_SUPPORTED = 1'b0;
localparam PLIC_BASE = 34'h0C000000;
localparam PLIC_RANGE = 34'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam SDC_BASE = 34'h00012100;
localparam SDC_RANGE = 34'h0000001F;
// Bus Interface width
localparam AHBW = 32;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
// Hardware configuration
localparam UART_PRESCALE = 1;
// Interrupt configuration
localparam PLIC_NUM_SRC = 10;
// comment out the following if >=32 sources
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_GPIO_ID = 3;
localparam PLIC_UART_ID = 10;
localparam BPRED_SUPPORTED = 0;
localparam BPRED_TYPE = "BP_GSHARE"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
localparam BPRED_SIZE = 10;
localparam BTB_SIZE = 10;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 4;
localparam DIVCOPIES = 4;
// bit manipulation
localparam ZBA_SUPPORTED = 0;
localparam ZBB_SUPPORTED = 0;
localparam ZBC_SUPPORTED = 0;
localparam ZBS_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;

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//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
// `include "wally-shared.vh"
localparam FPGA = 0;
localparam QEMU = 0;
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 1;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;
localparam DCACHE_SUPPORTED = 1;
localparam ICACHE_SUPPORTED = 1;
localparam VIRTMEM_SUPPORTED = 1;
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
localparam BIGENDIAN_SUPPORTED = 1;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 32'd32;
localparam DTLB_ENTRIES = 32'd32;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 32'd4;
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
localparam DCACHE_LINELENINBITS = 32'd512;
localparam ICACHE_NUMWAYS = 32'd4;
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
localparam ICACHE_LINELENINBITS = 32'd512;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 32'd4;
localparam IDIV_ON_FPU = 1;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 32'd16;
// Address space
localparam RESET_VECTOR = 64'h80000000;
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
localparam DTIM_SUPPORTED = 1'b0;
localparam DTIM_BASE = 64'h80000000;
localparam DTIM_RANGE = 64'h007FFFFF;
localparam IROM_SUPPORTED = 1'b0;
localparam IROM_BASE = 64'h80000000;
localparam IROM_RANGE = 64'h007FFFFF;
localparam BOOTROM_SUPPORTED = 1'b1;
localparam BOOTROM_BASE = 64'h00001000;
localparam BOOTROM_RANGE = 64'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam UNCORE_RAM_BASE = 64'h80000000;
localparam UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam EXT_MEM_BASE = 64'h80000000;
localparam EXT_MEM_RANGE = 64'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b1;
localparam CLINT_BASE = 64'h02000000;
localparam CLINT_RANGE = 64'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b1;
localparam GPIO_BASE = 64'h10060000;
localparam GPIO_RANGE = 64'h000000FF;
localparam UART_SUPPORTED = 1'b1;
localparam UART_BASE = 64'h10000000;
localparam UART_RANGE = 64'h00000007;
localparam PLIC_SUPPORTED = 1'b1;
localparam PLIC_BASE = 64'h0C000000;
localparam PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam SDC_BASE = 64'h00012100;
localparam SDC_RANGE = 64'h0000001F;
// Bus Interface width
localparam AHBW = 32'd32;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
// Hardware configuration
localparam UART_PRESCALE = 32'd1;
// Interrupt configuration
localparam PLIC_NUM_SRC = 32'd10;
// comment out the following if >=32 sources
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_GPIO_ID = 32'd3;
localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 1;
// BP_GSHARE, BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
// GSHARE_N, GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N
localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N
localparam BPRED_SIZE = 32'd16;
localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'd4;
localparam DIVCOPIES = 32'd4;
// bit manipulation
localparam ZBA_SUPPORTED = 1;
localparam ZBB_SUPPORTED = 1;
localparam ZBC_SUPPORTED = 1;
localparam ZBS_SUPPORTED = 1;
// Memory synthesis configuration
localparam USE_SRAM = 0;
`include "test-shared.vh"

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//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
localparam FPGA = 0;
localparam QEMU = 0;
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
// I
localparam MISA = (32'h00000104);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 0;
localparam DCACHE_SUPPORTED = 0;
localparam ICACHE_SUPPORTED = 0;
localparam VIRTMEM_SUPPORTED = 0;
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
localparam BIGENDIAN_SUPPORTED = 0;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 32'd32;
localparam DTLB_ENTRIES = 32'd32;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 32'd4;
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
localparam DCACHE_LINELENINBITS = 32'd512;
localparam ICACHE_NUMWAYS = 32'd4;
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
localparam ICACHE_LINELENINBITS = 32'd512;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 32'd4;
localparam IDIV_ON_FPU = 0;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 32'd0;
// Address space
localparam RESET_VECTOR = 64'h80000000;
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
localparam DTIM_SUPPORTED = 1'b1;
localparam DTIM_BASE = 64'h80000000;
localparam DTIM_RANGE = 64'h007FFFFF;
localparam IROM_SUPPORTED = 1'b1;
localparam IROM_BASE = 64'h80000000;
localparam IROM_RANGE = 64'h007FFFFF;
localparam BOOTROM_SUPPORTED = 1'b0;
localparam BOOTROM_BASE = 64'h00001000;
localparam BOOTROM_RANGE = 64'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b0;
localparam UNCORE_RAM_BASE = 64'h80000000;
localparam UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam EXT_MEM_BASE = 64'h80000000;
localparam EXT_MEM_RANGE = 64'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b0;
localparam CLINT_BASE = 64'h02000000;
localparam CLINT_RANGE = 64'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b0;
localparam GPIO_BASE = 64'h10060000;
localparam GPIO_RANGE = 64'h000000FF;
localparam UART_SUPPORTED = 1'b0;
localparam UART_BASE = 64'h10000000;
localparam UART_RANGE = 64'h00000007;
localparam PLIC_SUPPORTED = 1'b0;
localparam PLIC_BASE = 64'h0C000000;
localparam PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam SDC_BASE = 64'h00012100;
localparam SDC_RANGE = 64'h0000001F;
// Bus Interface width
localparam AHBW = 32'd32;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
// Hardware configuration
localparam UART_PRESCALE = 32'd1;
// Interrupt configuration
localparam PLIC_NUM_SRC = 32'd10;
// comment out the following if >=32 sources
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_GPIO_ID = 32'd3;
localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 0;
localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N
localparam BPRED_SIZE = 32'd10;
localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'h4;
localparam DIVCOPIES = 32'h4;
// bit manipulation
localparam ZBA_SUPPORTED = 0;
localparam ZBB_SUPPORTED = 0;
localparam ZBC_SUPPORTED = 0;
localparam ZBS_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;
`include "test-shared.vh"

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//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
localparam FPGA = 0;
localparam QEMU = 0;
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;
localparam DCACHE_SUPPORTED = 0;
localparam ICACHE_SUPPORTED = 0;
localparam VIRTMEM_SUPPORTED = 0;
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
localparam BIGENDIAN_SUPPORTED = 0;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 32'd0;
localparam DTLB_ENTRIES = 32'd0;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 32'd4;
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
localparam DCACHE_LINELENINBITS = 32'd512;
localparam ICACHE_NUMWAYS = 32'd4;
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
localparam ICACHE_LINELENINBITS = 32'd512;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 32'd2;
localparam IDIV_ON_FPU = 0;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 32'd0;
// Address space
localparam RESET_VECTOR = 64'h80000000;
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
localparam DTIM_SUPPORTED = 1'b1;
localparam DTIM_BASE = 64'h80000000;
localparam DTIM_RANGE = 64'h007FFFFF;
localparam IROM_SUPPORTED = 1'b1;
localparam IROM_BASE = 64'h80000000;
localparam IROM_RANGE = 64'h007FFFFF;
localparam BOOTROM_SUPPORTED = 1'b0;
localparam BOOTROM_BASE = 64'h00001000;
localparam BOOTROM_RANGE = 64'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b0;
localparam UNCORE_RAM_BASE = 64'h80000000;
localparam UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam EXT_MEM_BASE = 64'h80000000;
localparam EXT_MEM_RANGE = 64'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b1;
localparam CLINT_BASE = 64'h02000000;
localparam CLINT_RANGE = 64'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b1;
localparam GPIO_BASE = 64'h10060000;
localparam GPIO_RANGE = 64'h000000FF;
localparam UART_SUPPORTED = 1'b1;
localparam UART_BASE = 64'h10000000;
localparam UART_RANGE = 64'h00000007;
localparam PLIC_SUPPORTED = 1'b1;
localparam PLIC_BASE = 64'h0C000000;
localparam PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam SDC_BASE = 64'h00012100;
localparam SDC_RANGE = 64'h0000001F;
// Bus Interface width
localparam AHBW = 32'd32;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
// Hardware configuration
localparam UART_PRESCALE = 32'd1;
// Interrupt configuration
localparam PLIC_NUM_SRC = 32'd10;
// comment out the following if >=32 sources
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_GPIO_ID = 32'd3;
localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 0;
localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N
localparam BPRED_SIZE = 32'd10;
localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'h4;
localparam DIVCOPIES = 32'h4;
// bit manipulation
localparam ZBA_SUPPORTED = 0;
localparam ZBB_SUPPORTED = 0;
localparam ZBC_SUPPORTED = 0;
localparam ZBS_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;
`include "test-shared.vh"

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//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
localparam FPGA = 0;
localparam QEMU = 0;
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32'd64;
// IEEE 754 compliance
localparam IEEE754 = 0;
// MISA RISC-V configuration per specification
localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 1;
localparam SSTC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;
localparam DCACHE_SUPPORTED = 1;
localparam ICACHE_SUPPORTED = 1;
localparam VIRTMEM_SUPPORTED = 1;
localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ;
localparam BIGENDIAN_SUPPORTED = 1;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 32'd32;
localparam DTLB_ENTRIES = 32'd32;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 32'd4;
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
localparam DCACHE_LINELENINBITS = 32'd512;
localparam ICACHE_NUMWAYS = 32'd4;
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
localparam ICACHE_LINELENINBITS = 32'd512;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 32'd4;
localparam IDIV_ON_FPU = 1;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 32'd16;
// Address space
localparam RESET_VECTOR = 64'h0000000080000000;
// Bus Interface width
localparam AHBW = 32'd64;
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physiccal Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam DTIM_SUPPORTED = 1'b0;
localparam DTIM_BASE = 64'h80000000;
localparam DTIM_RANGE = 64'h007FFFFF;
localparam IROM_SUPPORTED = 1'b0;
localparam IROM_BASE = 64'h80000000;
localparam IROM_RANGE = 64'h007FFFFF;
localparam BOOTROM_SUPPORTED = 1'b1;
localparam BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
localparam BOOTROM_RANGE = 64'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam UNCORE_RAM_BASE = 64'h80000000;
localparam UNCORE_RAM_RANGE = 64'h7FFFFFFF;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam EXT_MEM_BASE = 64'h80000000;
localparam EXT_MEM_RANGE = 64'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b1;
localparam CLINT_BASE = 64'h02000000;
localparam CLINT_RANGE = 64'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b1;
localparam GPIO_BASE = 64'h10060000;
localparam GPIO_RANGE = 64'h000000FF;
localparam UART_SUPPORTED = 1'b1;
localparam UART_BASE = 64'h10000000;
localparam UART_RANGE = 64'h00000007;
localparam PLIC_SUPPORTED = 1'b1;
localparam PLIC_BASE = 64'h0C000000;
localparam PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam SDC_BASE = 64'h00012100;
localparam SDC_RANGE = 64'h0000001F;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
// Hardware configuration
localparam UART_PRESCALE = 32'd1;
// Interrupt configuration
localparam PLIC_NUM_SRC = 32'd10;
// comment out the following if >=32 sources
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_GPIO_ID = 32'd3;
localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 1;
localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
localparam BPRED_SIZE = 32'd10;
localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'h4;
localparam DIVCOPIES = 32'h4;
// bit manipulation
localparam ZBA_SUPPORTED = 0;
localparam ZBB_SUPPORTED = 0;
localparam ZBC_SUPPORTED = 0;
localparam ZBS_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;
`include "test-shared.vh"

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//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
// `include "wally-shared.vh"
localparam FPGA = 0;
localparam QEMU = 0;
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32'd64;
// IEEE 754 compliance
localparam IEEE754 = 0;
// MISA RISC-V configuration per specification
localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 1;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;
localparam DCACHE_SUPPORTED = 1;
localparam ICACHE_SUPPORTED = 1;
localparam VIRTMEM_SUPPORTED = 1;
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
localparam BIGENDIAN_SUPPORTED = 1;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 32'd32;
localparam DTLB_ENTRIES = 32'd32;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 32'd4;
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
localparam DCACHE_LINELENINBITS = 32'd512;
localparam ICACHE_NUMWAYS = 32'd4;
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
localparam ICACHE_LINELENINBITS = 32'd512;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 32'd4;
localparam IDIV_ON_FPU = 1;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 32'd16;
// Address space
localparam RESET_VECTOR = 64'h0000000080000000;
// Bus Interface width
localparam AHBW = 32'd64;
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam DTIM_SUPPORTED = 1'b0;
localparam DTIM_BASE = 64'h80000000;
localparam DTIM_RANGE = 64'h007FFFFF;
localparam IROM_SUPPORTED = 1'b0;
localparam IROM_BASE = 64'h80000000;
localparam IROM_RANGE = 64'h007FFFFF;
localparam BOOTROM_SUPPORTED = 1'b1;
localparam BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder;
localparam BOOTROM_RANGE = 64'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam UNCORE_RAM_BASE = 64'h80000000;
localparam UNCORE_RAM_RANGE = 64'h7FFFFFFF;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam EXT_MEM_BASE = 64'h80000000;
localparam EXT_MEM_RANGE = 64'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b1;
localparam CLINT_BASE = 64'h02000000;
localparam CLINT_RANGE = 64'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b1;
localparam GPIO_BASE = 64'h10060000;
localparam GPIO_RANGE = 64'h000000FF;
localparam UART_SUPPORTED = 1'b1;
localparam UART_BASE = 64'h10000000;
localparam UART_RANGE = 64'h00000007;
localparam PLIC_SUPPORTED = 1'b1;
localparam PLIC_BASE = 64'h0C000000;
localparam PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam SDC_BASE = 64'h00012100;
localparam SDC_RANGE = 64'h0000001F;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
// Hardware configuration
localparam UART_PRESCALE = 32'd1;
// Interrupt configuration
localparam PLIC_NUM_SRC = 32'd10;
// comment out the following if >=32 sources
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_GPIO_ID = 32'd3;
localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 1;
localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
localparam BPRED_SIZE = 32'd10;
localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'h4;
localparam DIVCOPIES = 32'h4;
// bit manipulation
localparam ZBA_SUPPORTED = 1;
localparam ZBB_SUPPORTED = 1;
localparam ZBC_SUPPORTED = 1;
localparam ZBS_SUPPORTED = 1;
// Memory synthesis configuration
localparam USE_SRAM = 0;
`include "test-shared.vh"

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//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
localparam FPGA = 0;
localparam QEMU = 0;
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32'd64;
// IEEE 754 compliance
localparam IEEE754 = 0;
// MISA RISC-V configuration per specification
localparam MISA = (32'h00000104);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 0;
localparam DCACHE_SUPPORTED = 0;
localparam ICACHE_SUPPORTED = 0;
localparam VIRTMEM_SUPPORTED = 0;
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
localparam BIGENDIAN_SUPPORTED = 0;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 32'd0;
localparam DTLB_ENTRIES = 32'd0;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 32'd4;
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
localparam DCACHE_LINELENINBITS = 32'd512;
localparam ICACHE_NUMWAYS = 32'd4;
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
localparam ICACHE_LINELENINBITS = 32'd512;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 32'd4;
localparam IDIV_ON_FPU = 0;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 32'd0;
// Address space
localparam RESET_VECTOR = 64'h0000000080000000;
// Bus Interface width
localparam AHBW = (XLEN);
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physiccal Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam DTIM_SUPPORTED = 1'b1;
localparam DTIM_BASE = 64'h80000000;
localparam DTIM_RANGE = 64'h007FFFFF;
localparam IROM_SUPPORTED = 1'b1;
localparam IROM_BASE = 64'h80000000;
localparam IROM_RANGE = 64'h007FFFFF;
localparam BOOTROM_SUPPORTED = 1'b0;
localparam BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
localparam BOOTROM_RANGE = 64'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b0;
localparam UNCORE_RAM_BASE = 64'h80000000;
localparam UNCORE_RAM_RANGE = 64'h7FFFFFFF;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam EXT_MEM_BASE = 64'h80000000;
localparam EXT_MEM_RANGE = 64'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b0;
localparam CLINT_BASE = 64'h02000000;
localparam CLINT_RANGE = 64'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b0;
localparam GPIO_BASE = 64'h10060000;
localparam GPIO_RANGE = 64'h000000FF;
localparam UART_SUPPORTED = 1'b0;
localparam UART_BASE = 64'h10000000;
localparam UART_RANGE = 64'h00000007;
localparam PLIC_SUPPORTED = 1'b0;
localparam PLIC_BASE = 64'h0C000000;
localparam PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam SDC_BASE = 64'h00012100;
localparam SDC_RANGE = 64'h0000001F;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
// Hardware configuration
localparam UART_PRESCALE = 32'd1;
// Interrupt configuration
localparam PLIC_NUM_SRC = 32'd10;
// comment out the following if >=32 sources
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_GPIO_ID = 32'd3;
localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 0;
localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
localparam BPRED_SIZE = 32'd10;
localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'h4;
localparam DIVCOPIES = 32'h4;
// bit manipulation
localparam ZBA_SUPPORTED = 0;
localparam ZBB_SUPPORTED = 0;
localparam ZBC_SUPPORTED = 0;
localparam ZBS_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;
`include "test-shared.vh"

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@ -0,0 +1,164 @@
// Populate parameter structure with values specific to the current configuration
parameter cvw_t P = '{
FPGA : FPGA,
QEMU : QEMU,
XLEN : XLEN,
IEEE754 : IEEE754,
MISA : MISA,
AHBW : AHBW,
ZICSR_SUPPORTED : ZICSR_SUPPORTED,
ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED,
COUNTERS : COUNTERS,
ZICOUNTERS_SUPPORTED : ZICOUNTERS_SUPPORTED,
ZFH_SUPPORTED : ZFH_SUPPORTED,
SSTC_SUPPORTED : SSTC_SUPPORTED,
VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED,
VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
BIGENDIAN_SUPPORTED : BIGENDIAN_SUPPORTED,
SVADU_SUPPORTED : SVADU_SUPPORTED,
ZMMUL_SUPPORTED : ZMMUL_SUPPORTED,
BUS_SUPPORTED : BUS_SUPPORTED,
DCACHE_SUPPORTED : DCACHE_SUPPORTED,
ICACHE_SUPPORTED : ICACHE_SUPPORTED,
ITLB_ENTRIES : ITLB_ENTRIES,
DTLB_ENTRIES : DTLB_ENTRIES,
DCACHE_NUMWAYS : DCACHE_NUMWAYS,
DCACHE_WAYSIZEINBYTES : DCACHE_WAYSIZEINBYTES,
DCACHE_LINELENINBITS : DCACHE_LINELENINBITS,
ICACHE_NUMWAYS : ICACHE_NUMWAYS,
ICACHE_WAYSIZEINBYTES : ICACHE_WAYSIZEINBYTES,
ICACHE_LINELENINBITS : ICACHE_LINELENINBITS,
IDIV_BITSPERCYCLE : IDIV_BITSPERCYCLE,
IDIV_ON_FPU : IDIV_ON_FPU,
PMP_ENTRIES : PMP_ENTRIES,
RESET_VECTOR : RESET_VECTOR,
WFI_TIMEOUT_BIT : WFI_TIMEOUT_BIT,
DTIM_SUPPORTED : DTIM_SUPPORTED,
DTIM_BASE : DTIM_BASE,
DTIM_RANGE : DTIM_RANGE,
IROM_SUPPORTED : IROM_SUPPORTED,
IROM_BASE : IROM_BASE,
IROM_RANGE : IROM_RANGE,
BOOTROM_SUPPORTED : BOOTROM_SUPPORTED,
BOOTROM_BASE : BOOTROM_BASE,
BOOTROM_RANGE : BOOTROM_RANGE,
UNCORE_RAM_SUPPORTED : UNCORE_RAM_SUPPORTED,
UNCORE_RAM_BASE : UNCORE_RAM_BASE,
UNCORE_RAM_RANGE : UNCORE_RAM_RANGE,
EXT_MEM_SUPPORTED : EXT_MEM_SUPPORTED,
EXT_MEM_BASE : EXT_MEM_BASE,
EXT_MEM_RANGE : EXT_MEM_RANGE,
CLINT_SUPPORTED : CLINT_SUPPORTED,
CLINT_BASE : CLINT_BASE,
CLINT_RANGE : CLINT_RANGE,
GPIO_SUPPORTED : GPIO_SUPPORTED,
GPIO_BASE : GPIO_BASE,
GPIO_RANGE : GPIO_RANGE,
UART_SUPPORTED : UART_SUPPORTED,
UART_BASE : UART_BASE,
UART_RANGE : UART_RANGE,
PLIC_SUPPORTED : PLIC_SUPPORTED,
PLIC_BASE : PLIC_BASE,
PLIC_RANGE : PLIC_RANGE,
SDC_SUPPORTED : SDC_SUPPORTED,
SDC_BASE : SDC_BASE,
SDC_RANGE : SDC_RANGE,
GPIO_LOOPBACK_TEST : GPIO_LOOPBACK_TEST,
UART_PRESCALE : UART_PRESCALE ,
PLIC_NUM_SRC : PLIC_NUM_SRC,
PLIC_NUM_SRC_LT_32 : PLIC_NUM_SRC_LT_32,
PLIC_GPIO_ID : PLIC_GPIO_ID,
PLIC_UART_ID : PLIC_UART_ID,
BPRED_SUPPORTED : BPRED_SUPPORTED,
BPRED_TYPE : BPRED_TYPE,
BPRED_SIZE : BPRED_SIZE,
BTB_SIZE : BTB_SIZE,
RADIX : RADIX,
DIVCOPIES : DIVCOPIES,
ZBA_SUPPORTED : ZBA_SUPPORTED,
ZBB_SUPPORTED : ZBB_SUPPORTED,
ZBC_SUPPORTED : ZBC_SUPPORTED,
ZBS_SUPPORTED : ZBS_SUPPORTED,
USE_SRAM : USE_SRAM,
M_MODE : M_MODE,
S_MODE : S_MODE,
U_MODE : U_MODE,
VPN_SEGMENT_BITS : VPN_SEGMENT_BITS,
VPN_BITS : VPN_BITS,
PPN_BITS : PPN_BITS,
PA_BITS : PA_BITS,
SVMODE_BITS : SVMODE_BITS,
ASID_BASE : ASID_BASE,
ASID_BITS : ASID_BITS,
NO_TRANSLATE : NO_TRANSLATE,
SV32 : SV32,
SV39 : SV39,
SV48 : SV48,
A_SUPPORTED : A_SUPPORTED,
B_SUPPORTED : B_SUPPORTED,
C_SUPPORTED : C_SUPPORTED,
D_SUPPORTED : D_SUPPORTED,
E_SUPPORTED : E_SUPPORTED,
F_SUPPORTED : F_SUPPORTED,
I_SUPPORTED : I_SUPPORTED,
M_SUPPORTED : M_SUPPORTED,
Q_SUPPORTED : Q_SUPPORTED,
S_SUPPORTED : S_SUPPORTED,
U_SUPPORTED : U_SUPPORTED,
LOG_XLEN : LOG_XLEN,
PMPCFG_ENTRIES : PMPCFG_ENTRIES,
Q_LEN : Q_LEN,
Q_NE : Q_NE,
Q_NF : Q_NF,
Q_BIAS : Q_BIAS,
Q_FMT : Q_FMT,
D_LEN : D_LEN,
D_NE : D_NE,
D_NF : D_NF,
D_BIAS : D_BIAS,
D_FMT : D_FMT,
S_LEN : S_LEN,
S_NE : S_NE,
S_NF : S_NF,
S_BIAS : S_BIAS,
S_FMT : S_FMT,
H_LEN : H_LEN,
H_NE : H_NE,
H_NF : H_NF,
H_BIAS : H_BIAS,
H_FMT : H_FMT,
FLEN : FLEN,
NE : NE ,
NF : NF ,
FMT : FMT ,
BIAS : BIAS,
FPSIZES : FPSIZES,
FMTBITS : FMTBITS,
LEN1 : LEN1 ,
NE1 : NE1 ,
NF1 : NF1 ,
FMT1 : FMT1 ,
BIAS1 : BIAS1,
LEN2 : LEN2 ,
NE2 : NE2 ,
NF2 : NF2 ,
FMT2 : FMT2 ,
BIAS2 : BIAS2,
CVTLEN : CVTLEN,
LLEN : LLEN,
LOGCVTLEN : LOGCVTLEN,
NORMSHIFTSZ : NORMSHIFTSZ,
LOGNORMSHIFTSZ : LOGNORMSHIFTSZ,
CORRSHIFTSZ : CORRSHIFTSZ,
DIVN : DIVN,
LOGR : LOGR,
RK : RK,
LOGRK : LOGRK,
FPDUR : FPDUR,
DURLEN : DURLEN,
DIVb : DIVb,
DIVBLEN : DIVBLEN,
DIVa : DIVa
};

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@ -0,0 +1,119 @@
// constants defining different privilege modes
// defined in Table 1.1 of the privileged spec
localparam M_MODE = (2'b11);
localparam S_MODE = (2'b01);
localparam U_MODE = (2'b00);
// Virtual Memory Constants
localparam VPN_SEGMENT_BITS = (XLEN == 32 ? 32'd10 : 32'd9);
localparam VPN_BITS = (XLEN==32 ? (2*VPN_SEGMENT_BITS) : (4*VPN_SEGMENT_BITS));
localparam PPN_BITS = (XLEN==32 ? 32'd22 : 32'd44);
localparam PA_BITS = (XLEN==32 ? 32'd34 : 32'd56);
localparam SVMODE_BITS = (XLEN==32 ? 32'd1 : 32'd4);
localparam ASID_BASE = (XLEN==32 ? 32'd22 : 32'd44);
localparam ASID_BITS = (XLEN==32 ? 32'd9 : 32'd16);
// constants to check SATP_MODE against
// defined in Table 4.3 of the privileged spec
localparam NO_TRANSLATE = 4'd0;
localparam SV32 = 4'd1;
localparam SV39 = 4'd8;
localparam SV48 = 4'd9;
// macros to define supported modes
localparam A_SUPPORTED = ((MISA >> 0) % 2 == 1);
localparam B_SUPPORTED = ((ZBA_SUPPORTED | ZBB_SUPPORTED | ZBC_SUPPORTED | ZBS_SUPPORTED));// not based on MISA
localparam C_SUPPORTED = ((MISA >> 2) % 2 == 1);
localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1);
localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1);
localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1);
localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1);
localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1);
localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1);
localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1);
localparam U_SUPPORTED = ((MISA >> 20) % 2 == 1);
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
// logarithm of XLEN, used for number of index bits to select
localparam LOG_XLEN = (XLEN == 32 ? 32'd5 : 32'd6);
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
localparam PMPCFG_ENTRIES = (PMP_ENTRIES/32'd8);
// Floating point constants for Quad, Double, Single, and Half precisions
// Lim: I've made some of these 64 bit to avoid width warnings.
// If errors crop up, try downsizing back to 32.
localparam Q_LEN = 32'd128;
localparam Q_NE = 32'd15;
localparam Q_NF = 32'd112;
localparam Q_BIAS = 32'd16383;
localparam Q_FMT = 2'd3;
localparam D_LEN = 32'd64;
localparam D_NE = 32'd11;
localparam D_NF = 32'd52;
localparam D_BIAS = 32'd1023;
localparam D_FMT = 2'd1;
localparam S_LEN = 32'd32;
localparam S_NE = 32'd8;
localparam S_NF = 32'd23;
localparam S_BIAS = 32'd127;
localparam S_FMT = 2'd0;
localparam H_LEN = 32'd16;
localparam H_NE = 32'd5;
localparam H_NF = 32'd10;
localparam H_BIAS = 32'd15;
localparam H_FMT = 2'd2;
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
localparam FLEN = (Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : S_LEN);
localparam NE = (Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : S_NE);
localparam NF = (Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : S_NF);
localparam FMT = (Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : 2'd0);
localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS);
/* Delete once tested dh 10/10/22
localparam FLEN = (Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : F_SUPPORTED ? S_LEN : H_LEN);
localparam NE = (Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : F_SUPPORTED ? S_NE : H_NE);
localparam NF = (Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : F_SUPPORTED ? S_NF : H_NF);
localparam FMT = (Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : F_SUPPORTED ? 2'd0 : 2'd2);
localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : F_SUPPORTED ? S_BIAS : H_BIAS);*/
// Floating point constants needed for FPU paramerterization
localparam FPSIZES = ((32)'(Q_SUPPORTED)+(32)'(D_SUPPORTED)+(32)'(F_SUPPORTED)+(32)'(ZFH_SUPPORTED));
localparam FMTBITS = ((32)'(FPSIZES>=3)+1);
localparam LEN1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_LEN : (F_SUPPORTED & (FLEN != S_LEN)) ? S_LEN : H_LEN);
localparam NE1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NE : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NE : H_NE);
localparam NF1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NF : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NF : H_NF);
localparam FMT1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? 2'd1 : (F_SUPPORTED & (FLEN != S_LEN)) ? 2'd0 : 2'd2);
localparam BIAS1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_BIAS : (F_SUPPORTED & (FLEN != S_LEN)) ? S_BIAS : H_BIAS);
localparam LEN2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_LEN : H_LEN);
localparam NE2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NE : H_NE);
localparam NF2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NF : H_NF);
localparam FMT2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0 : 2'd2);
localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
// division constants
localparam DIVN = (((NF<XLEN) & IDIV_ON_FPU) ? XLEN : NF+2); // standard length of input
localparam LOGR = ($clog2(RADIX)); // r = log(R)
localparam RK = (LOGR*DIVCOPIES); // r*k used for intdiv preproc
localparam LOGRK = ($clog2(RK)); // log2(r*k)
localparam FPDUR = ((DIVN+1+(LOGR*DIVCOPIES))/(LOGR*DIVCOPIES)+(RADIX/4));
localparam DURLEN = ($clog2(FPDUR+1));
localparam DIVb = (FPDUR*LOGR*DIVCOPIES-1); // canonical fdiv size (b)
localparam DIVBLEN = ($clog2(DIVb+1)-1);
localparam DIVa = (DIVb+1-XLEN); // used for idiv on fpu
// largest length in IEU/FPU
localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF));
localparam LLEN = (($unsigned(FLEN)<$unsigned(XLEN)) ? ($unsigned(XLEN)) : ($unsigned(FLEN)));
localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
localparam NORMSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6)));
localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));
localparam CORRSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVN+1+NF) > (3*NF+4) ? (DIVN+1+NF) : (3*NF+4)));
// Disable spurious Verilator warnings
/* verilator lint_off STMTDLY */
/* verilator lint_off ASSIGNDLY */
/* verilator lint_off PINCONNECTEMPTY */

2
sim/lint-wally
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@ -8,7 +8,7 @@ basepath=$(dirname $0)/..
for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
#for config in rv64gc; do
echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after $config lint due to errors or warnings"
exit 1
fi

387
src/wally/cvw.sv
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@ -28,188 +28,237 @@
// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package
// that is referenced by all Wally modules but not by other subsystems.
// Load configuration-specific information
`include "wally-config.vh"
`ifndef CVW_T
`define CVW_T 1
// Place configuration in a package
package cvw;
parameter XLEN = `XLEN;
parameter FPGA = `FPGA;
parameter QEMU = `QEMU;
parameter IEEE754 = `IEEE754;
parameter MISA = `MISA;
parameter ZICSR_SUPPORTED = `ZICSR_SUPPORTED;
parameter ZIFENCEI_SUPPORTED = `ZIFENCEI_SUPPORTED;
parameter COUNTERS = `COUNTERS;
parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED;
parameter ZFH_SUPPORTED = `ZFH_SUPPORTED;
parameter BUS_SUPPORTED = `BUS_SUPPORTED;
parameter DCACHE_SUPPORTED = `DCACHE_SUPPORTED;
parameter ICACHE_SUPPORTED = `ICACHE_SUPPORTED;
parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED;
parameter VECTORED_INTERRUPTS_SUPPORTED = `VECTORED_INTERRUPTS_SUPPORTED;
parameter BIGENDIAN_SUPPORTED = `BIGENDIAN_SUPPORTED;
parameter ITLB_ENTRIES = `ITLB_ENTRIES;
parameter DTLB_ENTRIES = `DTLB_ENTRIES;
parameter DCACHE_NUMWAYS = `DCACHE_NUMWAYS;
parameter DCACHE_WAYSIZEINBYTES = `DCACHE_WAYSIZEINBYTES;
parameter DCACHE_LINELENINBITS = `DCACHE_LINELENINBITS;
parameter ICACHE_NUMWAYS = `ICACHE_NUMWAYS;
parameter ICACHE_WAYSIZEINBYTES = `ICACHE_WAYSIZEINBYTES;
parameter ICACHE_LINELENINBITS = `ICACHE_LINELENINBITS;
parameter IDIV_BITSPERCYCLE = `IDIV_BITSPERCYCLE;
parameter IDIV_ON_FPU = `IDIV_ON_FPU;
parameter PMP_ENTRIES = `PMP_ENTRIES;
parameter RESET_VECTOR = `RESET_VECTOR;
parameter WFI_TIMEOUT_BIT = `WFI_TIMEOUT_BIT;
parameter DTIM_SUPPORTED = `DTIM_SUPPORTED;
parameter DTIM_BASE = `DTIM_BASE;
parameter DTIM_RANGE = `DTIM_RANGE;
parameter IROM_SUPPORTED = `IROM_SUPPORTED;
parameter IROM_BASE = `IROM_BASE;
parameter IROM_RANGE = `IROM_RANGE;
parameter BOOTROM_SUPPORTED = `BOOTROM_SUPPORTED;
parameter BOOTROM_BASE = `BOOTROM_BASE;
parameter BOOTROM_RANGE = `BOOTROM_RANGE;
parameter UNCORE_RAM_SUPPORTED = `UNCORE_RAM_SUPPORTED;
parameter UNCORE_RAM_BASE = `UNCORE_RAM_BASE;
parameter UNCORE_RAM_RANGE = `UNCORE_RAM_RANGE;
parameter EXT_MEM_SUPPORTED = `EXT_MEM_SUPPORTED;
parameter EXT_MEM_BASE = `EXT_MEM_BASE;
parameter EXT_MEM_RANGE = `EXT_MEM_RANGE;
parameter CLINT_SUPPORTED = `CLINT_SUPPORTED;
parameter CLINT_BASE = `CLINT_BASE;
parameter CLINT_RANGE = `CLINT_RANGE;
parameter GPIO_SUPPORTED = `GPIO_SUPPORTED;
parameter GPIO_BASE = `GPIO_BASE;
parameter GPIO_RANGE = `GPIO_RANGE;
parameter UART_SUPPORTED = `UART_SUPPORTED;
parameter UART_BASE = `UART_BASE;
parameter UART_RANGE = `UART_RANGE;
parameter PLIC_SUPPORTED = `PLIC_SUPPORTED;
parameter PLIC_BASE = `PLIC_BASE;
parameter PLIC_RANGE = `PLIC_RANGE;
parameter SDC_SUPPORTED = `SDC_SUPPORTED;
parameter SDC_BASE = `SDC_BASE;
parameter SDC_RANGE = `SDC_RANGE;
parameter AHBW = `AHBW;
parameter GPIO_LOOPBACK_TEST = `GPIO_LOOPBACK_TEST;
parameter UART_PRESCALE = `UART_PRESCALE;
parameter PLIC_NUM_SRC = `PLIC_NUM_SRC;
parameter PLIC_GPIO_ID = `PLIC_GPIO_ID;
parameter PLIC_UART_ID = `PLIC_UART_ID;
parameter BPRED_SUPPORTED = `BPRED_SUPPORTED;
parameter BPRED_TYPE = `BPRED_TYPE;
parameter BPRED_SIZE = `BPRED_SIZE;
parameter SVADU_SUPPORTED = `SVADU_SUPPORTED;
// parameter = `;
typedef struct packed {
logic FPGA; // Modifications to tare
logic QEMU; // Hacks to agree with QEMU during Linux boot
int XLEN; // Machine width (32 or 64)
logic IEEE754; // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead)
int MISA; // Machine Instruction Set Architecture
int AHBW; // AHB bus width (usually = XLEN)
// RISC-V Features
logic ZICSR_SUPPORTED;
logic ZIFENCEI_SUPPORTED;
logic [11:0] COUNTERS;
logic ZICOUNTERS_SUPPORTED;
logic ZFH_SUPPORTED;
logic SSTC_SUPPORTED;
logic VIRTMEM_SUPPORTED;
logic VECTORED_INTERRUPTS_SUPPORTED;
logic BIGENDIAN_SUPPORTED;
logic SVADU_SUPPORTED;
logic ZMMUL_SUPPORTED;
// Microarchitectural Features
logic BUS_SUPPORTED;
logic DCACHE_SUPPORTED;
logic ICACHE_SUPPORTED;
// TLB configuration. Entries should be a power of 2
int ITLB_ENTRIES;
int DTLB_ENTRIES;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 ints per way, 256 bit or more lines
int DCACHE_NUMWAYS;
int DCACHE_WAYSIZEINBYTES;
int DCACHE_LINELENINBITS;
int ICACHE_NUMWAYS;
int ICACHE_WAYSIZEINBYTES;
int ICACHE_LINELENINBITS;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
int IDIV_BITSPERCYCLE;
logic IDIV_ON_FPU;
// Legal number of PMP entries are 0, 16, or 64
int PMP_ENTRIES;
// Address space
longint RESET_VECTOR;
// WFI Timeout Wait
int WFI_TIMEOUT_BIT;
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
logic DTIM_SUPPORTED;
longint DTIM_BASE;
longint DTIM_RANGE;
logic IROM_SUPPORTED;
longint IROM_BASE;
longint IROM_RANGE;
logic BOOTROM_SUPPORTED;
longint BOOTROM_BASE;
longint BOOTROM_RANGE;
logic UNCORE_RAM_SUPPORTED;
longint UNCORE_RAM_BASE;
longint UNCORE_RAM_RANGE;
logic EXT_MEM_SUPPORTED;
longint EXT_MEM_BASE;
longint EXT_MEM_RANGE;
logic CLINT_SUPPORTED;
longint CLINT_BASE;
longint CLINT_RANGE;
logic GPIO_SUPPORTED;
longint GPIO_BASE;
longint GPIO_RANGE;
logic UART_SUPPORTED;
longint UART_BASE;
longint UART_RANGE;
logic PLIC_SUPPORTED;
longint PLIC_BASE;
longint PLIC_RANGE;
logic SDC_SUPPORTED;
longint SDC_BASE;
longint SDC_RANGE;
// Test modes
// Tie GPIO outputs back to inputs
logic GPIO_LOOPBACK_TEST;
// Hardware configuration
int UART_PRESCALE ;
// Interrupt configuration
int PLIC_NUM_SRC;
logic PLIC_NUM_SRC_LT_32;
int PLIC_GPIO_ID;
int PLIC_UART_ID;
logic BPRED_SUPPORTED;
longint BPRED_TYPE;
int BPRED_SIZE;
int BTB_SIZE;
// Shared parameters
// FPU division architecture
int RADIX;
int DIVCOPIES;
// constants defining different privilege modes
// defined in Table 1.1 of the privileged spec
parameter M_MODE = (2'b11);
parameter S_MODE = (2'b01);
parameter U_MODE = (2'b00);
// bit manipulation
logic ZBA_SUPPORTED;
logic ZBB_SUPPORTED;
logic ZBC_SUPPORTED;
logic ZBS_SUPPORTED;
// Virtual Memory Constants
parameter VPN_SEGMENT_BITS = (`XLEN == 32 ? 10 : 9);
parameter VPN_BITS = (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS));
parameter PPN_BITS = (`XLEN==32 ? 22 : 44);
parameter PA_BITS = (`XLEN==32 ? 34 : 56);
parameter SVMODE_BITS = (`XLEN==32 ? 1 : 4);
parameter ASID_BASE = (`XLEN==32 ? 22 : 44);
parameter ASID_BITS = (`XLEN==32 ? 9 : 16);
// Memory synthesis configuration
logic USE_SRAM;
// constants to check SATP_MODE against
// defined in Table 4.3 of the privileged spec
parameter NO_TRANSLATE = 0;
parameter SV32 = 1;
parameter SV39 = 8;
parameter SV48 = 9;
// constants defining different privilege modes
// defined in Table 1.1 of the privileged spec
logic [1:0] M_MODE ;
logic [1:0] S_MODE ;
logic [1:0] U_MODE ;
// macros to define supported modes
parameter A_SUPPORTED = ((`MISA >> 0) % 2 == 1);
parameter B_SUPPORTED = ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)); // not based on MISA
parameter C_SUPPORTED = ((`MISA >> 2) % 2 == 1);
parameter D_SUPPORTED = ((`MISA >> 3) % 2 == 1);
parameter E_SUPPORTED = ((`MISA >> 4) % 2 == 1);
parameter F_SUPPORTED = ((`MISA >> 5) % 2 == 1);
parameter I_SUPPORTED = ((`MISA >> 8) % 2 == 1);
parameter M_SUPPORTED = ((`MISA >> 12) % 2 == 1);
parameter Q_SUPPORTED = ((`MISA >> 16) % 2 == 1);
parameter S_SUPPORTED = ((`MISA >> 18) % 2 == 1);
parameter U_SUPPORTED = ((`MISA >> 20) % 2 == 1);
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
// Virtual Memory Constants
int VPN_SEGMENT_BITS;
int VPN_BITS;
int PPN_BITS;
int PA_BITS;
int SVMODE_BITS;
int ASID_BASE;
int ASID_BITS;
// logarithm of XLEN, used for number of index bits to select
parameter LOG_XLEN = (`XLEN == 32 ? 5 : 6);
// constants to check SATP_MODE against
// defined in Table 4.3 of the privileged spec
logic [3:0] NO_TRANSLATE;
logic [3:0] SV32;
logic [3:0] SV39;
logic [3:0] SV48;
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
parameter PMPCFG_ENTRIES = (`PMP_ENTRIES/8);
// Floating point constants for Quad, Double, Single, and Half precisions
parameter Q_LEN = 32'd128;
parameter Q_NE = 32'd15;
parameter Q_NF = 32'd112;
parameter Q_BIAS = 32'd16383;
parameter Q_FMT = 2'd3;
parameter D_LEN = 32'd64;
parameter D_NE = 32'd11;
parameter D_NF = 32'd52;
parameter D_BIAS = 32'd1023;
parameter D_FMT = 2'd1;
parameter S_LEN = 32'd32;
parameter S_NE = 32'd8;
parameter S_NF = 32'd23;
parameter S_BIAS = 32'd127;
parameter S_FMT = 2'd0;
parameter H_LEN = 32'd16;
parameter H_NE = 32'd5;
parameter H_NF = 32'd10;
parameter H_BIAS = 32'd15;
parameter H_FMT = 2'd2;
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
parameter FLEN = (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN);
parameter NE = (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE);
parameter NF = (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF);
parameter FMT = (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0);
parameter BIAS = (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS);
// macros to define supported modes
logic A_SUPPORTED;
logic B_SUPPORTED;
logic C_SUPPORTED;
logic D_SUPPORTED;
logic E_SUPPORTED;
logic F_SUPPORTED;
logic I_SUPPORTED;
logic M_SUPPORTED;
logic Q_SUPPORTED;
logic S_SUPPORTED;
logic U_SUPPORTED;
// Floating point constants needed for FPU paramerterization
parameter FPSIZES = ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED));
parameter FMTBITS = ((32)'(`FPSIZES>=3)+1);
parameter LEN1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN);
parameter NE1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE);
parameter NF1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF);
parameter FMT1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2);
parameter BIAS1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS);
parameter LEN2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN);
parameter NE2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE);
parameter NF2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF);
parameter FMT2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2);
parameter BIAS2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS);
// logarithm of XLEN, used for number of index bits to select
int LOG_XLEN;
// largest length in IEU/FPU
parameter CVTLEN = ((`NF<`XLEN) ? (`XLEN) : (`NF));
parameter LLEN = ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN));
parameter LOGCVTLEN = $unsigned($clog2(`CVTLEN+1));
parameter NORMSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)));
parameter LOGNORMSHIFTSZ = ($clog2(`NORMSHIFTSZ));
parameter CORRSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)));
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
int PMPCFG_ENTRIES;
// division constants
// Floating point constants for Quad, Double, Single, and Half precisions
int Q_LEN;
int Q_NE;
int Q_NF;
int Q_BIAS;
logic [1:0] Q_FMT;
int D_LEN;
int D_NE;
int D_NF;
int D_BIAS;
logic [1:0] D_FMT;
int S_LEN;
int S_NE;
int S_NF;
int S_BIAS;
logic [1:0] S_FMT;
int H_LEN;
int H_NE;
int H_NF;
int H_BIAS;
logic [1:0] H_FMT;
parameter DIVN = (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2); // standard length of input
parameter LOGR = ($clog2(`RADIX)); // r = log(R)
parameter RK = (`LOGR*`DIVCOPIES); // r*k used for intdiv preproc
parameter LOGRK = ($clog2(`RK)); // log2(r*k)
parameter FPDUR = ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4));
parameter DURLEN = ($clog2(`FPDUR+1));
parameter DIVb = (`FPDUR*`LOGR*`DIVCOPIES-1); // canonical fdiv size (b)
parameter DIVBLEN = ($clog2(`DIVb+1)-1);
parameter DIVa = (`DIVb+1-`XLEN); // used for idiv on fpu
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
int FLEN;
int NE ;
int NF ;
logic [1:0] FMT ;
int BIAS;
// Floating point constants needed for FPU paramerterization
int FPSIZES;
int FMTBITS;
int LEN1 ;
int NE1 ;
int NF1 ;
logic [1:0] FMT1 ;
int BIAS1;
int LEN2 ;
int NE2 ;
int NF2 ;
logic [1:0] FMT2 ;
int BIAS2;
// largest length in IEU/FPU
int CVTLEN;
int LLEN;
int LOGCVTLEN;
int NORMSHIFTSZ;
int LOGNORMSHIFTSZ;
int CORRSHIFTSZ;
// division constants
int DIVN ;
int LOGR;
int RK ;
int LOGRK ;
int FPDUR ;
int DURLEN ;
int DIVb ;
int DIVBLEN ;
int DIVa ;
} cvw_t;
endpackage
`endif

2
src/wally/wallypipelinedcore.sv
View File

@ -29,7 +29,7 @@
//import cvw::*; // global CORE-V-Wally parameters
`include "wally-config.vh"
module wallypipelinedcore (
module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
// Privileged
input logic MTimerInt, MExtInt, SExtInt, MSwInt,

19
src/wally/wallypipelinedsoc.sv
View File

@ -26,22 +26,23 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
//import cvw::*; // global CORE-V-Wally parameters
`include "wally-config.vh"
module wallypipelinedsoc (
module wallypipelinedsoc import cvw::*; (
input logic clk,
input logic reset_ext, // external asynchronous reset pin
output logic reset, // reset synchronized to clk to prevent races on release
// AHB Interface
input logic [`AHBW-1:0] HRDATAEXT,
input logic [AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT,
output logic HSELEXT,
// outputs to external memory, shared with uncore memory
output logic HCLK, HRESETn,
output logic [`PA_BITS-1:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
output logic [`XLEN/8-1:0] HWSTRB,
output logic [PA_BITS-1:0] HADDR,
output logic [AHBW-1:0] HWDATA,
output logic [XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
@ -64,24 +65,26 @@ module wallypipelinedsoc (
);
// Uncore signals
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
logic [AHBW-1:0] HRDATA; // from AHB mux in uncore
logic HRESP; // response from AHB
logic MTimerInt, MSwInt;// timer and software interrupts from CLINT
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
logic MExtInt,SExtInt; // from PLIC
`include "parameter-defs.vh"
// synchronize reset to SOC clock domain
synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
// instantiate processor and internal memories
wallypipelinedcore core(.clk, .reset,
wallypipelinedcore #(P) core(.clk, .reset,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
);
// instantiate uncore if a bus interface exists
if (`BUS_SUPPORTED) begin : uncore
if (BUS_SUPPORTED) begin : uncore
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,

4
testbench/testbench.sv
View File

@ -28,7 +28,7 @@
`include "wally-config.vh"
`include "tests.vh"
`define PrintHPMCounters 1
`define PrintHPMCounters 0
`define BPRED_LOGGER 0
`define I_CACHE_ADDR_LOGGER 0
`define D_CACHE_ADDR_LOGGER 0
@ -204,7 +204,7 @@ module testbench;
assign SDCDat = '0;
end
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);