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https://github.com/openhwgroup/cvw
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Changes BTA to BPBTA.
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@ -71,7 +71,7 @@ module bpred (
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logic [1:0] BPDirPredF;
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logic [`XLEN-1:0] BTAF, RASPCF;
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logic [`XLEN-1:0] BPBTAF, RASPCF;
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logic BPPCWrongE;
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logic IClassWrongE;
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logic BPDirPredWrongE;
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@ -85,7 +85,7 @@ module bpred (
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logic BTBTargetWrongE;
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logic RASTargetWrongE;
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logic [`XLEN-1:0] BTAD;
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logic [`XLEN-1:0] BPBTAD;
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logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
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logic BPBranchF, BPJumpF, BPReturnF, BPCallF;
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@ -95,7 +95,7 @@ module bpred (
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logic BranchM, JumpM, ReturnM, CallM;
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logic BranchW, JumpW, ReturnW, CallW;
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logic BPReturnWrongD;
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logic [`XLEN-1:0] BTAE;
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logic [`XLEN-1:0] BPBTAE;
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@ -150,7 +150,7 @@ module bpred (
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btb #(`BTB_SIZE)
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TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCF, .PCD, .PCE, .PCM,
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.BTAF, .BTAD, .BTAE,
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.BPBTAF, .BPBTAD, .BPBTAE,
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.BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}),
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.IClassWrongM, .IClassWrongE,
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.IEUAdrE, .IEUAdrM,
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@ -181,7 +181,7 @@ module bpred (
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// Output the predicted PC or corrected PC on miss-predict.
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assign BPPCSrcF = (BPBranchF & BPDirPredF[1]) | BPJumpF;
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mux2 #(`XLEN) pcmuxbp(BTAF, RASPCF, BPReturnF, BPPCF);
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mux2 #(`XLEN) pcmuxbp(BPBTAF, RASPCF, BPReturnF, BPPCF);
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// Selects the BP or PC+2/4.
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mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPCF, BPPCSrcF, PC0NextF);
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// If the prediction is wrong select the correct address.
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@ -196,7 +196,7 @@ module bpred (
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if(`ZICOUNTERS_SUPPORTED) begin
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logic [`XLEN-1:0] RASPCD, RASPCE;
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logic BTBPredPCWrongE, RASPredPCWrongE;
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logic BTAWrongE, RASPredPCWrongE;
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// performance counters
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// 1. class (class wrong / minstret) (IClassWrongM / csr) // Correct now
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// 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal)
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@ -207,14 +207,14 @@ module bpred (
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// could be wrong or the fall through address selected for branch predict not taken.
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// By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
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// both without the above inaccuracies.
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// **** use BTAWrongM from BTB.
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assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
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// **** use BPBTAWrongM from BTB.
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assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
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assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
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flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
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flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
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flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
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{BPDirPredWrongE, BTBPredPCWrongE, RASPredPCWrongE},
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{BPDirPredWrongE, BTAWrongE, RASPredPCWrongE},
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{BPDirPredWrongM, BTAWrongM, RASPredPCWrongM});
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end else begin
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@ -35,9 +35,9 @@ module btb #(parameter Depth = 10 ) (
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,// PC at various stages
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output logic [`XLEN-1:0] BTAF, // BTB's guess at PC
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output logic [`XLEN-1:0] BTAD,
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output logic [`XLEN-1:0] BTAE,
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output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC
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output logic [`XLEN-1:0] BPBTAD,
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output logic [`XLEN-1:0] BPBTAE,
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output logic [3:0] BTBIClassF, // BTB's guess at instruction class
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// update
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input logic IClassWrongM, // BTB's instruction class guess was wrong
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@ -57,8 +57,8 @@ module btb #(parameter Depth = 10 ) (
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logic [`XLEN+3:0] TableBTBPredF;
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logic [`XLEN-1:0] IEUAdrW;
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logic [`XLEN-1:0] PCW;
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logic BTBWrongE, BTAWrongE;
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logic BTBWrongM, BTAWrongM;
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logic BTBWrongE, BPBTAWrongE;
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logic BTBWrongM, BPBTAWrongM;
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// hashing function for indexing the PC
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@ -84,12 +84,12 @@ module btb #(parameter Depth = 10 ) (
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assign MatchW = PCFIndex == PCWIndex;
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assign MatchX = MatchD | MatchE | MatchM | MatchW;
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assign ForwardBTBPredictionF = MatchD ? {InstrClassD, BTAD} :
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assign ForwardBTBPredictionF = MatchD ? {InstrClassD, BPBTAD} :
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MatchE ? {InstrClassE, IEUAdrE} :
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MatchM ? {InstrClassM, IEUAdrM} :
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{InstrClassW, IEUAdrW} ;
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assign {BTBIClassF, BTAF} = MatchX ? ForwardBTBPredictionF : {TableBTBPredF};
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assign {BTBIClassF, BPBTAF} = MatchX ? ForwardBTBPredictionF : {TableBTBPredF};
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// An optimization may be using a PC relative address.
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@ -97,16 +97,16 @@ module btb #(parameter Depth = 10 ) (
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.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF),
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.ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
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flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BTAF, BTAD);
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flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BPBTAF, BPBTAD);
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// BTAE is not strickly necessary. However it is used by two parts of wally.
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// BPBTAE is not strickly necessary. However it is used by two parts of wally.
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// 1. It gates updates to the BTB when the prediction does not change. This save power.
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// 2. BTAWrongE is used by the performance counters to track when the BTB's BTA or instruction class is wrong.
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flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BTAD, BTAE);
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assign BTAWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]);
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// 2. BPBTAWrongE is used by the performance counters to track when the BTB's BPBTA or instruction class is wrong.
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flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BPBTAD, BPBTAE);
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assign BPBTAWrongE = (BPBTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]);
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flopenrc #(1) BTAWrongMReg(clk, reset, FlushM, ~StallM, BTAWrongE, BTAWrongM);
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assign BTBWrongM = BTAWrongM | IClassWrongM;
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flopenrc #(1) BPBTAWrongMReg(clk, reset, FlushM, ~StallM, BPBTAWrongE, BPBTAWrongM);
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assign BTBWrongM = BPBTAWrongM | IClassWrongM;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
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flopenr #(`XLEN) IEUAdrWReg(clk, reset, ~StallW, IEUAdrM, IEUAdrW);
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