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https://github.com/openhwgroup/cvw
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Update fpu.sv
Program clean up
This commit is contained in:
Harshini Srinath
GitHub
parent
4c4e6ca520
commit
a98096aa7d
181
src/fpu/fpu.sv
181
src/fpu/fpu.sv
@ -27,40 +27,40 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fpu import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic reset,
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input logic clk,
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input logic reset,
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// Hazards
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input logic StallE, StallM, StallW, // stall signals (from HZU)
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input logic FlushE, FlushM, FlushW, // flush signals (from HZU)
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output logic FPUStallD, // Stall the decode stage (To HZU)
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output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
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input logic StallE, StallM, StallW, // stall signals (from HZU)
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input logic FlushE, FlushM, FlushW, // flush signals (from HZU)
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output logic FPUStallD, // Stall the decode stage (To HZU)
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output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
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// CSRs
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input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
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input logic [2:0] FRM_REGW, // Rounding mode (from CSR)
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input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
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input logic [2:0] FRM_REGW, // Rounding mode (from CSR)
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// Decode stage
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input logic [31:0] InstrD, // instruction (from IFU)
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input logic [31:0] InstrD, // instruction (from IFU)
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// Execute stage
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input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations
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input logic IntDivE, W64E, // Integer division on FPU
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input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU)
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input logic [4:0] RdE, // which FP register to write to (from IEU)
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output logic FWriteIntE, // integer register write enable (to IEU)
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output logic FCvtIntE, // Convert to int (to IEU)
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input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations
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input logic IntDivE, W64E, // Integer division on FPU
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input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU)
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input logic [4:0] RdE, // which FP register to write to (from IEU)
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output logic FWriteIntE, // integer register write enable (to IEU)
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output logic FCvtIntE, // Convert to int (to IEU)
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// Memory stage
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input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations
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input logic [4:0] RdM, // which FP register to write to (from IEU)
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output logic FRegWriteM, // FP register write enable (to privileged unit)
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output logic FpLoadStoreM, // Fp load instruction? (to LSU)
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output logic [P.FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU)
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output logic [P.XLEN-1:0] FIntResM, // data to be written to integer register (to IEU)
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU)
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output logic [4:0] SetFflagsM, // FPU flags (to privileged unit)
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input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations
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input logic [4:0] RdM, // which FP register to write to (from IEU)
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output logic FRegWriteM, // FP register write enable (to privileged unit)
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output logic FpLoadStoreM, // Fp load instruction? (to LSU)
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output logic [P.FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU)
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output logic [P.XLEN-1:0] FIntResM, // data to be written to integer register (to IEU)
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU)
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output logic [4:0] SetFflagsM, // FPU flags (to privileged unit)
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// Writeback stage
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input logic [4:0] RdW, // which FP register to write to (from IEU)
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input logic [P.FLEN-1:0] ReadDataW, // Read data (from LSU)
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output logic [P.XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU)
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output logic FCvtIntW, // select FCvtIntRes (to IEU)
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output logic [P.XLEN-1:0] FIntDivResultW // Result from integer division (to IEU)
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input logic [4:0] RdW, // which FP register to write to (from IEU)
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input logic [P.FLEN-1:0] ReadDataW, // Read data (from LSU)
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output logic [P.XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU)
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output logic FCvtIntW, // select FCvtIntRes (to IEU)
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output logic [P.XLEN-1:0] FIntDivResultW // Result from integer division (to IEU)
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);
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// RISC-V FPU specifics:
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@ -68,86 +68,86 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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// - RISC-V detects underflow after rounding
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// control signals
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logic FRegWriteW; // FP register write enable
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logic [2:0] FrmM; // FP rounding mode
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logic [P.FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double
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logic FDivStartE, IDivStartE; // Start division or squareroot
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logic FWriteIntM; // Write to integer register
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
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logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component
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logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input
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logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input
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logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation
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logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation
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logic FRegWriteE; // Write floating-point register
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logic FRegWriteW; // FP register write enable
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logic [2:0] FrmM; // FP rounding mode
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logic [P.FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double
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logic FDivStartE, IDivStartE; // Start division or squareroot
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logic FWriteIntM; // Write to integer register
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
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logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component
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logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input
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logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input
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logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation
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logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation
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logic FRegWriteE; // Write floating-point register
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// regfile signals
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logic [P.FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [P.FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [P.FLEN-1:0] XE; // Input 1 to the various units (after forwarding)
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logic [P.XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding)
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logic [P.FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding)
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logic [P.FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding)
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logic [P.FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [P.FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [P.FLEN-1:0] XE; // Input 1 to the various units (after forwarding)
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logic [P.XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding)
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logic [P.FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding)
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logic [P.FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding)
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// unpacking signals
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logic XsE, YsE, ZsE; // input's sign - execute stage
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logic XsM, YsM; // input's sign - memory stage
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logic [P.NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage
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logic [P.NE-1:0] ZeM; // input's exponent - memory stage
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logic [P.NF:0] XmE, YmE, ZmE; // input's significand - execute stage
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logic [P.NF:0] XmM, YmM, ZmM; // input's significand - memory stage
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logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
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logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
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logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
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logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
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logic XSubnormE; // is the input subnormal
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logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
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logic XZeroM, YZeroM; // is the input zero - memory stage
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logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
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logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
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logic XExpMaxE; // is the exponent all ones (max value)
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logic [P.FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations
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logic XsE, YsE, ZsE; // input's sign - execute stage
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logic XsM, YsM; // input's sign - memory stage
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logic [P.NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage
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logic [P.NE-1:0] ZeM; // input's exponent - memory stage
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logic [P.NF:0] XmE, YmE, ZmE; // input's significand - execute stage
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logic [P.NF:0] XmM, YmM, ZmM; // input's significand - memory stage
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logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
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logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
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logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
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logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
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logic XSubnormE; // is the input subnormal
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logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
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logic XZeroM, YZeroM; // is the input zero - memory stage
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logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
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logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
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logic XExpMaxE; // is the exponent all ones (max value)
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logic [P.FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations
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// Fma Signals
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logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting
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logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying
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logic [3*P.NF+3:0] SmE, SmM; // Sum significand
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logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output
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logic [P.NE+1:0] SeE,SeM; // Sum exponent
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logic InvAE, InvAM; // Invert addend
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logic AsE, AsM; // Addend sign
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logic PsE, PsM; // Product sign
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logic SsE, SsM; // Sum sign
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logic [$clog2(3*P.NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count
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logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting
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logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying
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logic [3*P.NF+3:0] SmE, SmM; // Sum significand
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logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output
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logic [P.NE+1:0] SeE,SeM; // Sum exponent
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logic InvAE, InvAM; // Invert addend
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logic AsE, AsM; // Addend sign
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logic PsE, PsM; // Product sign
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logic SsE, SsM; // Sum sign
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logic [$clog2(3*P.NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count
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// Cvt Signals
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logic [P.NE:0] CeE, CeM; // convert intermediate expoent
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logic [P.LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by
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logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
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logic CsE, CsM; // convert result sign
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logic IntZeroE, IntZeroM; // is the integer zero?
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logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
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logic CsE, CsM; // convert result sign
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logic IntZeroE, IntZeroM; // is the integer zero?
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logic [P.CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder)
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logic [P.XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU)
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// divide signals
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logic [P.DIVb:0] QmM; // fdivsqrt signifcand
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logic [P.NE+1:0] QeM; // fdivsqrt exponent
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logic DivStickyM; // fdivsqrt sticky bit
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logic FDivDoneE, IFDivStartE; // fdivsqrt control signals
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logic DivStickyM; // fdivsqrt sticky bit
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logic FDivDoneE, IFDivStartE; // fdivsqrt control signals
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logic [P.XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU)
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// result and flag signals
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logic [P.XLEN-1:0] ClassResE; // classify result
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logic [P.FLEN-1:0] CmpFpResE; // compare result to FPU (min/max)
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logic [P.XLEN-1:0] CmpIntResE; // compare result to IEU (eq/lt/le)
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logic CmpNVE; // compare invalid flag (Not Valid)
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logic CmpNVE; // compare invalid flag (Not Valid)
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logic [P.FLEN-1:0] SgnResE; // sign injection result
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logic [P.XLEN-1:0] FIntResE; // FPU to IEU E-stage result (classify, compare, move)
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logic [P.FLEN-1:0] PostProcResM; // Postprocessor output
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logic [4:0] PostProcFlgM; // Postprocessor flags
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logic PreNVE, PreNVM; // selected flag that is ready in the memory stage
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logic [4:0] PostProcFlgM; // Postprocessor flags
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logic PreNVE, PreNVM; // selected flag that is ready in the memory stage
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logic [P.FLEN-1:0] FpResM, FpResW; // FPU preliminary result
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logic [P.FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage
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logic [P.FLEN-1:0] FResultW; // final FP result being written to the FP register
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@ -156,9 +156,9 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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logic [P.FLEN-1:0] AlignedSrcAE; // align SrcA from IEU to the floating point format for fmv
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logic [P.FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed
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logic [P.FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed
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logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
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logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
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logic [P.FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer
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logic mvsgn; // sign bit for extending move
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logic mvsgn; // sign bit for extending move
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//////////////////////////////////////////////////////////////////////////////////////////
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// Decode Stage: fctrl decoder, read register file
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@ -205,15 +205,15 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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mux2 #(P.FLEN) fonemux ({{P.FLEN-P.LEN1{1'b1}}, 2'b0, {P.NE1-1{1'b1}}, (P.NF1)'(0)}, {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
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else if(P.FPSIZES == 3 | P.FPSIZES == 4)
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mux4 #(P.FLEN) fonemux ({{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)},
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{{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)},
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{{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)},
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{2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
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{{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)},
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{{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)},
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{2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
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assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
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mux2 #(P.FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
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// Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
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// For add and subtract, Z comes from second source operand
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if(P.FPSIZES == 1) assign BoxedZeroE = 0;
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if(P.FPSIZES == 1) assign BoxedZeroE = 0;
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else if(P.FPSIZES == 2)
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mux2 #(P.FLEN) fmulzeromux ({{P.FLEN-P.LEN1{1'b1}}, {P.LEN1{1'b0}}}, (P.FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
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else if(P.FPSIZES == 3 | P.FPSIZES == 4)
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@ -262,7 +262,6 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
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.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
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// NaN Box SrcA to convert integer to requested FP size
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if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
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else if(P.FPSIZES == 2)
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@ -334,7 +333,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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.PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
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// FPU flag selection - to privileged
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mux2 #(5) FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
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mux2 #(5) FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
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mux2 #(P.FLEN) FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
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// M/W pipe registers
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