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1584 Commits

Author SHA1 Message Date
James Stine
79bf543ba9 Update 2022-06-23 11:59:05 -05:00
James Stine
001e8e077d Add sqrt qlsc table generator 2022-06-23 11:46:44 -05:00
Katherine Parry
49067792dc fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
4a6dee5926 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
slmnemo
3e2afdf53b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 16:10:25 -07:00
slmnemo
10b6ff39a8 changed order of makefiles and fixed warnings when running makes 2022-06-21 16:10:18 -07:00
David Harris
2577b5c3a4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 22:56:02 +00:00
David Harris
3d5645d683 Trimmed lint-wally 2022-06-21 22:56:01 +00:00
slmnemo
d291387b81 added individual makes for arch and wally tests as well as memfiles to Makefile. run using make archtests/wallytests/memfiles 2022-06-21 15:54:24 -07:00
Katherine Parry
e9f5778e2a using memread for quotent select 2022-06-21 15:49:52 -07:00
Katherine Parry
c41391e228 removed rv64fp from lint 2022-06-21 15:48:47 -07:00
David Harris
8537b883d1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 22:45:28 +00:00
Daniel Torres
cf56a0d76a fixed issue where the unused spike elf files were being used to find objdump files that didn't exist causing makefile-memfile to fail prematurely 2022-06-21 15:39:04 -07:00
Madeleine Masser-Frye
0161683945 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 20:31:06 +00:00
Madeleine Masser-Frye
fe31ee92e8 switched comparator to dc flip version 2022-06-21 20:30:33 +00:00
James Stine
493d3b1ac0 Add hex output in bad but okay way 2022-06-21 15:07:24 -05:00
James Stine
8e177b02e4 Add MATLAB scripts for PD plot 2022-06-21 10:14:53 -05:00
slmnemo
2b2760f5bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
2b2ddbcc5e Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
edc15d6ef9 made fixes to radix-2 divider testbench - divider doesn't pass 2022-06-20 23:01:53 +00:00
Katherine Parry
5d5f79eb8f radix-4 divider passing tests 2022-06-20 22:56:08 +00:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
James Stine
1108268557 Update C program for r=4 division by recurrence to match Table in EL 2022-06-20 11:32:40 -05:00
Daniel Torres
d077199608 embench and testbench now support running both O2 and Os build variations without overwriting one another 2022-06-17 21:15:42 -07:00
Daniel Torres
1ef5ed8005 arch tests now run on spike and sail and compare signatures during build 2022-06-17 20:53:15 -07:00
Daniel Torres
dcdd3702c3 removed old code from makefile, simplified code in testbench 2022-06-17 15:13:38 -07:00
Daniel Torres
3a5c02b44a arch bug fixes and testbench changes 2022-06-17 15:07:16 -07:00
David Harris
7e4988c2de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-17 15:45:24 +00:00
Katherine Parry
8425f8838d hopefully fixed lint error 2022-06-17 00:14:39 +00:00
Katherine Parry
93906b9457 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-15 22:58:42 +00:00
Katherine Parry
e121dcd4af postprocess out of fpu critical path 2022-06-15 22:58:33 +00:00
Madeleine Masser-Frye
c2493168b6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-15 18:30:27 +00:00
Madeleine Masser-Frye
76e30ed8ab cleanup, plots for paper 2022-06-15 18:28:36 +00:00
James Stine
d69a8f4077 Add back SV for integer division to use 8-bit CPA in qslc 2022-06-15 11:46:39 -05:00
James Stine
535a9a04ee Add r=4 C code 2022-06-15 11:44:09 -05:00
Katherine Parry
11b252a735 some synth fpu optimizations 2022-06-14 23:58:39 +00:00
David Harris
ecd733942a Removed testbench.sv.bak 2022-06-14 22:04:38 +00:00
Katherine Parry
998876ce49 removed false critical path from fpu 2022-06-14 16:50:46 +00:00
Katherine Parry
566001e07b fixed acciedental critical path in FPU 2022-06-14 00:02:38 +00:00
DTowersM
919c1818a8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 23:34:35 +00:00
DTowersM
1f4d56ba32 added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
David Harris
8ea484a343 Cleanup on RAM module 2022-06-13 19:37:43 +00:00
David Harris
b7a7ca6eac Typo in gpio reset 2022-06-13 19:37:05 +00:00
slmnemo
eb41185a70 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:30:33 -07:00
David Harris
be65e8f862 Removed SRT testvectors from repo 2022-06-13 19:27:33 +00:00
slmnemo
915b8e2adb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:27:23 -07:00
slmnemo
7b704f8db0 Merge branch 'cacheburstmode' into main. 
Cache burst mode is now working! It also uses the new RAM.
 2022-06-13 12:26:18 -07:00
slmnemo
98c07ce2c0 Added more comments 2022-06-13 12:26:08 -07:00
David Harris
ccd16210bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 19:26:07 +00:00
David Harris
e9ef9a5cb8 Fixed XOR logic in GPIO 2022-06-13 19:26:03 +00:00
slmnemo
3d715a098c Added comment about name of LSUBusInit/Lock signal 2022-06-13 10:56:02 -07:00
slmnemo
cadd62e49f Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals 2022-06-10 20:43:56 -07:00
slmnemo
beb4317e68 Added comments to signals added so the bus is easier to analyze 2022-06-10 20:30:04 -07:00
slmnemo
b7357efc6b Fixed failed regression state by only enabling counting when doing cached operations 2022-06-10 20:00:09 -07:00
slmnemo
63ed390c90 Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01. 2022-06-10 19:10:01 -07:00
Madeleine Masser-Frye
422bd2043f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-10 21:11:47 +00:00
Madeleine Masser-Frye
7cdf9cd4d3 added 'd' suffix to muxes for data-critical synths 2022-06-10 21:11:05 +00:00
DTowersM
4bbe5eeecd simplified coremark 2022-06-10 19:15:17 +00:00
slmnemo
dc11066ff2 Passed Regression: Seems to work perfectly fine 2022-06-09 18:21:13 -07:00
slmnemo
ec7cdee0f3 Merge branch 'main' into cacheburstmode 2022-06-09 17:51:03 -07:00
slmnemo
5a6eae214a ? 2022-06-09 17:50:47 -07:00
DTowersM
9e2d80764d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-10 00:38:07 +00:00
DTowersM
dd34f25ffd changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
slmnemo
3e8d3bae88 Changes made on 9th Jun 2022-06-09 17:33:51 -07:00
slmnemo
4ff105f18c Fixed lint error 2022-06-09 17:22:04 -07:00
David Harris
c836f37a08 New RAM for further testing 2022-06-09 23:50:43 +00:00
stineje
470c0552f8 Update integer division for r4 and qslc_r4a2.c 2022-06-09 16:45:13 -05:00
David Harris
dd4fa7c682 qslc_r4a2 generator 2022-06-09 17:26:47 +00:00
slmnemo
0d04751c77 Fixed error when doing uncached accesses where HTRANS was always 2 2022-06-08 18:58:07 -07:00
slmnemo
81d373c7ab Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request. 2022-06-08 17:34:02 -07:00
Madeleine Masser-Frye
0e64494e46 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-09 00:08:15 +00:00
Madeleine Masser-Frye
a58a756076 added one bit muxes for data critical synths 2022-06-09 00:06:12 +00:00
slmnemo
11924bdd9b Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending 2022-06-08 15:59:15 -07:00
slmnemo
e17ee3073e Fixed ifu displaying LSU bus state in wave.do 2022-06-08 15:30:32 -07:00
slmnemo
315c2f0669 Working version: Fixed error where Word count would always increment even without AHB to bus ACK 2022-06-08 15:29:32 -07:00
slmnemo
054cf5f7b0 Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
DTowersM
6402b2dec4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-08 16:28:18 +00:00
DTowersM
6944996329 added #1 delays to Stalls and Flushes in hazard unit 2022-06-08 16:28:09 +00:00
slmnemo
284e0395a0 Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42 Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
David Harris
5240bd1c90 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
3c8eafc8ee Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
9e5ab4d378 Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
DTowersM
a190342b8a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 23:58:58 +00:00
DTowersM
02a424d65b modified testbench.sv- now works with coremark 2022-06-07 23:58:50 +00:00
DTowersM
e324db71b4 cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000 2022-06-07 23:27:54 +00:00
slmnemo
6d36150c3d Fixed off-by-one error in busdp capture 2022-06-07 19:36:39 +00:00
slmnemo
73e0c1c07f Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00
DTowersM
df330961b8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 06:03:19 +00:00
DTowersM
590cf243bb added support for 64 bit rv tests 2022-06-07 06:02:23 +00:00
Katherine Parry
cfcaddf8aa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-06 16:06:54 +00:00
Katherine Parry
8fa0fc4229 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
slmnemo
7f70655113 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-03 18:56:29 -07:00
slmnemo
3fe78c9084 Fixed recurrent issue with testbench where it would never stop 2022-06-03 18:56:24 -07:00
cturek
afdfe770fc Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench. 2022-06-04 00:14:10 +00:00
DTowersM
caaf56cbf7 testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh 2022-06-03 22:07:14 +00:00
Madeleine Masser-Frye
56a053fc3d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye
31e9d0a41a added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
Katherine Parry
fd980fe9d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-03 15:34:27 +00:00
Katherine Parry
6b39b8c702 fixed compilation errors 2022-06-03 15:34:17 +00:00
slmnemo
9d1dfbdb50 Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace 2022-06-03 04:55:14 -07:00
Katherine Parry
8420b1e87c removed some debuging code accedentally pushed 2022-06-02 22:45:19 +00:00
Katherine Parry
6a4502e987 added rv64fpquad 2022-06-02 22:10:00 +00:00
Katherine Parry
cd8b2a2b98 added config rv64fpquad 2022-06-02 22:09:11 +00:00
David Harris
c74fec7fa6 renamed sim-fp to sim-testfloat 2022-06-02 15:05:29 -07:00
Katherine Parry
03280c0f9c added createallvectors 2022-06-02 21:56:05 +00:00
slmnemo
c8515001a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 12:54:08 -07:00
Katherine Parry
9a09ee3a35 fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
slmnemo
88454aa2ab Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do" 
This reverts commit 89c7438424.
 2022-06-02 12:45:21 -07:00
slmnemo
ad9e85beb9 Revert "Fixed buildroot by adding a second ." 
This reverts commit 8b27c1884e.
 2022-06-02 12:43:59 -07:00
slmnemo
65b8d0c32a Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py" 
This reverts commit e33ca59d46.
 2022-06-02 12:41:01 -07:00
slmnemo
0d650b2880 Revert "Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace" 
This reverts commit e4024eb503.
 2022-06-02 12:40:46 -07:00
David Harris
1d8bc2dc1b Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
David Harris
154410a37f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-02 15:48:36 +00:00
David Harris
faa15b1f8d Cleaned up comments in controller 2022-06-02 15:48:33 +00:00
David Harris
197b588193 Cleaned up test cases in testbench 2022-06-02 08:44:28 -07:00
David Harris
c7ec9282fe Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
slmnemo
c16c5beef5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 02:52:03 +00:00
slmnemo
65961223f8 Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files 2022-06-02 02:51:51 +00:00
Katherine Parry
e42afbfb30 paramerterized some small fma units 2022-06-01 23:34:29 +00:00
DTowersM
215f69a2ab Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-01 21:00:51 +00:00
DTowersM
d28b4cf602 added support for embench post processing to testbench.sv 2022-06-01 21:00:44 +00:00
Katherine Parry
dd19e55b8f unpacker optimizations 2022-06-01 16:52:21 +00:00
slmnemo
446ad498aa Fixed double assignment on LSUBurstType 2022-06-01 01:04:49 +00:00
cturek
949f53695d Fixed typos 2022-06-01 00:07:36 +00:00
slmnemo
cf05fec9c7 Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access 2022-05-31 16:33:05 -07:00
slmnemo
a86c4d5ff3 Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode 2022-05-31 15:57:55 -07:00
slmnemo
9ad1a42886 Redid the FSM to prepare for burst mode implementation 2022-05-31 15:57:42 -07:00
David Harris
475a84491e Unpackinput cleanup 2022-05-31 22:31:21 +00:00
David Harris
f9533fea1a Removed normalized output from unpack and simplified interface 2022-05-31 21:32:31 +00:00
David Harris
0d0a9cba66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 21:12:45 +00:00
David Harris
aa7b0616e4 ../src/privileged/csrc.sv 2022-05-31 21:12:17 +00:00
DTowersM
8903af3764 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 20:13:41 +00:00
DTowersM
525f6a6069 added testbench.sv support for embench tests, test output still WIP 2022-05-31 20:13:32 +00:00
DTowersM
0de54a01bf removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM 2022-05-31 20:10:56 +00:00
DTowersM
95df88ae70 added embench tests to tests.vh 2022-05-31 20:08:04 +00:00
Katherine Parry
f6ac33ce8a reorginized unpackinput signals 2022-05-31 17:40:34 +00:00
Katherine Parry
4ed7933aa3 added unpackinput.sv 2022-05-31 16:18:50 +00:00
David Harris
788fe406b5 Moved delegation logic from privmode to trap to simplify interface 2022-05-31 14:58:11 +00:00
David Harris
0cfe9e3373 Removed unused fp add and convert modules 2022-05-29 23:07:56 +00:00
Katherine Parry
950a17bef5 fixed lint error 2022-05-28 10:20:13 -07:00
slmnemo
4a8d0be32c Reverted commit 60e3d7d81b 2022-05-28 04:00:01 -07:00
slmnemo
f18989e801 Revert Commit 6c61840045 2022-05-28 03:35:17 -07:00
slmnemo
60e3d7d81b Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name 2022-05-28 03:16:55 -07:00
slmnemo
6c61840045 Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do 2022-05-28 03:14:49 -07:00
slmnemo
f78fa3b9b9 Reverted incorrect Ack 2022-05-28 10:06:26 +00:00
David Harris
b04e9ac1f6 fixed merge conflicts 2022-05-28 09:44:55 +00:00
David Harris
4237bb7abd Added comments to some files, added a+b = 0 detector to comparator.sv 2022-05-28 09:41:48 +00:00
Katherine Parry
9c58c63864 removed unused signal from FMA 2022-05-27 16:47:56 -07:00
Katherine Parry
a0ff98042c unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
95b506c5e0 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
Katherine Parry
1be91753fe moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
Katherine Parry
c6d79cd718 Removed guard bit from fma rounding 2022-05-27 08:23:46 -07:00
slmnemo
bc17f883d4 changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word 2022-05-26 18:41:27 -07:00
slmnemo
847c7930c4 added LSUBurstDone signal to signal when a burst has finished 2022-05-26 16:29:13 -07:00
cturek
5a0889016c fixed sizing issues in expcalc 2022-05-26 22:35:17 +00:00
cturek
3301d7c52a Implemented on-the-fly conversion for unsigned numbers 2022-05-26 22:20:43 +00:00
Katherine Parry
3c04f1bdec Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 20:48:30 +00:00
Katherine Parry
9d281b2604 fcvt.sv paramaterized 2022-05-26 20:48:22 +00:00
slmnemo
80fc716cd7 Added signal to monitor HBURST and comments for each burst in busdp 2022-05-26 13:35:49 -07:00
DTowersM
6f0b5753ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 19:05:21 +00:00
DTowersM
7ffef6ccfa fixed indent spacing (cosmetic change) 2022-05-26 19:04:21 +00:00
cturek
4a4f153eef Set up the divider for on-the-fly conversion 2022-05-26 16:45:28 +00:00
slmnemo
08430a1e85 added burst size signals to the IFU, EBU, LSU, and busdp 2022-05-25 18:02:50 -07:00
slmnemo
e8d97f0826 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:41:04 -07:00
slmnemo
a2300f063d added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction 2022-05-25 17:40:57 -07:00
slmnemo
d1421b88ad Added line to testbench to prevent annoying burst sizes 2022-05-25 17:29:45 -07:00
slmnemo
cebf93cf9c idk lol it says this has an unadded change 2022-05-25 17:17:49 -07:00
DTowersM
de60b15cfe Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 00:12:46 +00:00
slmnemo
012cb7439d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:11:03 -07:00
slmnemo
b5476204da see commit 9042cc3c 2022-05-25 17:10:59 -07:00
Katherine Parry
f3b28b988b added fcvt.sv 2022-05-26 00:10:51 +00:00
DTowersM
a1cda79cd5 Merge branch 'embench' into main 
embench contained the working makefiles for embench and is being merged into main as it working and done
 2022-05-26 00:10:50 +00:00
DTowersM
3f7eddbc89 working makefile for embench and removed testbench-f64 2022-05-26 00:08:18 +00:00
slmnemo
8422095a33 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:03:26 -07:00
slmnemo
4e5505f301 added logic to prevent cache line length from exceeding the max size of a burst. 2022-05-25 17:03:15 -07:00
cturek
c9845b96f4 Renamed variables for readability 2022-05-26 00:01:51 +00:00
cturek
51debfa186 Fixed exponent verification, added sign module and added sign tests 2022-05-25 23:36:21 +00:00
Katherine Parry
f35450207f single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
81a869c921 ppaAnalyze: docstrings and tsmc28 plotting 2022-05-25 13:52:20 +00:00
Madeleine Masser-Frye
dd4997bd1b added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
slmnemo
0398aa02a0 fixed a comment spelling typo 2022-05-23 19:24:28 -07:00
Katherine Parry
576fe4ec24 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-23 23:11:41 +00:00
Katherine Parry
e5d2dfe94b added exponents to srt divider 2022-05-23 23:07:27 +00:00
David Harris
d78451e39c Checked in qst2.c from James 2022-05-23 20:26:05 +00:00
Ross Thompson
b70baed214 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 23:54:33 -05:00
Ross Thompson
e2cf941a23 Possible plic fix? 2022-05-22 23:47:01 -05:00
Madeleine Masser-Frye
d91fd44ea5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-22 23:23:39 +00:00
Madeleine Masser-Frye
dbe4b4bafa added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Ross Thompson
bcb4ebf888 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 10:55:33 -05:00
Ross Thompson
c4f1a0362b Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
92a2ad02db Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Madeleine Masser-Frye
39a3bf5cdc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-05-21 09:53:31 +00:00
Madeleine Masser-Frye
b832a21b73 ppa updates 
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
 2022-05-21 09:53:26 +00:00
slmnemo
e3a7e3e2f3 changes suggested by ben, hopefully fixing buildroot (which is now not running) 2022-05-20 18:42:38 -07:00
Katherine Parry
5d34db85b2 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
0afac6904e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 18:31:56 -07:00
slmnemo
af0300c3d7 added documentation for ahblite burst types to ahblite.sv 2022-05-19 18:31:46 -07:00
slmnemo
11e703c8c0 fixed lint autofailing due to no log being produced in regression-wally 2022-05-19 18:30:59 -07:00
slmnemo
79c28d34dc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 17:51:45 -07:00
slmnemo
e4024eb503 Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace 2022-05-19 17:51:26 -07:00
slmnemo
e33ca59d46 Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py 2022-05-19 17:50:48 -07:00
slmnemo
8b27c1884e Fixed buildroot by adding a second . 2022-05-19 17:49:32 -07:00
slmnemo
89c7438424 parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do 2022-05-19 16:21:38 -07:00
Katherine Parry
ab1f088672 fixed lint warning 2022-05-19 20:34:06 +00:00
Katherine Parry
6f2d8c24ad Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
mmasserfrye
bab7335bee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-19 20:24:57 +00:00
mmasserfrye
d34f4a7c3c updated synth plotting and regression 2022-05-19 20:24:47 +00:00
Katherine Parry
738bbf6479 Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
slmnemo
c96f07ad75 added instructions to slack notifier 2022-05-18 16:50:31 -07:00
mmasserfrye
84422f3859 added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
mmasserfrye
f8722f04f9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-18 16:10:36 +00:00
mmasserfrye
12c42cd507 adapted shifter in ppa.sv for widths beside 32 and 64 
modified plotting and regression in ppaAnalyze.py
 2022-05-18 16:08:40 +00:00
Ross Thompson
b853c4ba47 Updated fpga debugger. 2022-05-17 23:04:01 -05:00
slmnemo
23d6791b22 simplified make-tests.sh to run the current makefile in regression 2022-05-17 17:29:34 -07:00
slmnemo
82e68f2170 Revert "same as last breaking commit, testing if the bisect works to output a breaking commit." 
This reverts commit dcb485ec61.

gottem
 2022-05-17 17:26:33 -07:00
slmnemo
dcb485ec61 same as last breaking commit, testing if the bisect works to output a breaking commit. 2022-05-17 17:22:09 -07:00
slmnemo
b7d036f3d0 Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D." 
This reverts commit f970cc3ea9.

fixed it
 2022-05-17 17:05:11 -07:00
slmnemo
f970cc3ea9 broke it again but this time it doesn't compile due to a missing semicolon on Rs1D. 2022-05-17 17:03:16 -07:00
slmnemo
589bd0ca34 Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression" 
This reverts commit 4908f77cf9.

unbroke wally
 2022-05-17 16:57:29 -07:00
slmnemo
357d77d332 Revert "Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main"" 
This reverts commit 0e3099743c.

reverted the wrong commit
 2022-05-17 16:57:00 -07:00
slmnemo
0e3099743c Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" 
This reverts commit 1c5a3de6d5, reversing
changes made to 1ff47888a7.

undid things
 2022-05-17 16:54:29 -07:00
slmnemo
4908f77cf9 Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression 2022-05-17 16:33:09 -07:00
slmnemo
1c5a3de6d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Added empty directory '/wkdir' to /pipelined/regression to avoid tests failing out of box due to the missing directory
 2022-05-17 20:32:53 +00:00
slmnemo
1ff47888a7 added wkdir in regression so regression runs out of box (assuming the old version of arch tests) 2022-05-17 20:32:38 +00:00
David Harris
a2280dadfd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 15:09:52 +00:00
David Harris
49f25bd03d Restored srt to working without exponent unit 2022-05-17 15:09:48 +00:00
mmasserfrye
2254a8218d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 01:11:58 +00:00
mmasserfrye
d34a942eb2 added 8 and 128 bit versions, adjusted alu 2022-05-17 01:11:43 +00:00
slmnemo
e4f0f55530 Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature. 2022-05-17 01:04:13 +00:00
slmnemo
7656e3031c quit 2022-05-17 01:03:09 +00:00
David Harris
8851ddd905 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 00:07:09 +00:00
David Harris
1bcbdcf57d removed exptestgen 2022-05-17 00:06:44 +00:00
David Harris
ea3e7006d9 Cleaned up unpacker changes in srt and lint errors 2022-05-17 00:06:14 +00:00
slmnemo
8c8a7daec2 Fixed grammar on two comments in bpred.sv 2022-05-16 22:41:18 +00:00
mmasserfrye
68a70ed8ff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
resolved merge conflict
 2022-05-16 15:42:59 +00:00
mmasserfrye
b82520237c tuning modules for ppa 2022-05-16 15:39:15 +00:00
David Harris
48e89485dd Cause simplification 2022-05-12 23:47:21 +00:00
David Harris
9651ced9bb Cause simplification 2022-05-12 23:39:10 +00:00
David Harris
2f283d9654 Cause simplification 2022-05-12 23:37:40 +00:00
David Harris
f5f1870077 Cause simplification 2022-05-12 23:33:35 +00:00
David Harris
5b7cccbc4b Cause simplification 2022-05-12 23:33:22 +00:00
David Harris
581d841653 Cause simplification 2022-05-12 23:29:35 +00:00
David Harris
2a3f545e0c Cause simplification 2022-05-12 23:27:02 +00:00
David Harris
c2b9fc0d8e trap/csr cleanup 2022-05-12 22:26:21 +00:00
David Harris
292d1f33da More trap/csr simplification 2022-05-12 22:06:03 +00:00
David Harris
662fffa830 More trap/csr simplification 2022-05-12 22:04:20 +00:00
David Harris
16b86c199c More trap/csr simplification 2022-05-12 22:00:23 +00:00
David Harris
5f358a37c6 More trap/csr simplification 2022-05-12 21:55:50 +00:00
David Harris
21ac969c7d Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00
David Harris
072c464dc1 Simplified MTVAL logic 2022-05-12 21:36:13 +00:00
David Harris
14f9f41d2d Partitioned privileged pipeline registers into module 2022-05-12 20:45:45 +00:00
David Harris
78448c7053 privileged cleanup 2022-05-12 20:21:33 +00:00
mmasserfrye
31f372e7b3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 20:20:40 +00:00
mmasserfrye
a10b8e47af cleaned lint for ppa.sv 2022-05-12 20:20:05 +00:00
David Harris
dd61afb7dc Formatting cleanup 2022-05-12 18:37:47 +00:00
mmasserfrye
01685b982c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 18:08:20 +00:00
mmasserfrye
b089ee26ee renamed madzscript, modified ppa.sv alu and shifter 2022-05-12 18:05:02 +00:00
David Harris
fde8375fbd Moved Breakpoint and Ecall fault logic into privdec 2022-05-12 16:45:53 +00:00
David Harris
2ceed15bd5 Moved TLB Flush logic into privdec 2022-05-12 16:41:52 +00:00
David Harris
1e5d94bbab Moved WFI timeout into privdec 2022-05-12 16:22:39 +00:00
David Harris
39ceb3a550 Partitioned privilege mode fsm into new module 2022-05-12 16:16:42 +00:00
David Harris
e81e530f68 More signal cleanup 2022-05-12 15:39:44 +00:00
David Harris
ce24c080d5 More unused signal cleanup 2022-05-12 15:26:08 +00:00
David Harris
5670f77de2 More unused signal cleanup 2022-05-12 15:21:09 +00:00
David Harris
4edf9b6355 More unused signal cleanup 2022-05-12 15:15:30 +00:00
David Harris
1aa3e65bae Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
David Harris
e2e63ca9a8 Clean up unused signals 2022-05-12 14:49:58 +00:00
David Harris
f17501ed8c Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
545d46acb9 Simplifed mstatus.TSR handling 2022-05-12 14:09:52 +00:00
David Harris
1e7401daa0 Fixed typo in csrm 2022-05-12 06:55:39 -07:00
mmasserfrye
999754801c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 07:24:04 +00:00
mmasserfrye
6cba6a92ba filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
David Harris
9999f69922 Added MCONFIGPTR CSR hardwired to 0 2022-05-12 04:31:45 +00:00
David Harris
9dd378098f merged ppa.sv 2022-05-11 18:14:16 +00:00
David Harris
1f761c4e06 PPA script progress 2022-05-11 18:11:51 +00:00
mmasserfrye
552a55d631 ed 
modified ppa.sv
 2022-05-11 16:22:12 +00:00
David Harris
8166fd772e Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
137b411bea Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
490902a655 Updated PPA experiment 2022-05-10 23:09:42 +00:00
David Harris
bb24aebebd Initial PPA study 2022-05-10 20:48:47 +00:00
David Harris
04fd22aeb0 endian swapper 2022-05-08 06:51:50 +00:00
David Harris
4f1b0fdc64 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
David Harris
1a5bfcf078 Fixed bug in delegated interrupts not being taken 2022-05-08 04:50:27 +00:00
David Harris
a516f89f22 WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
David Harris
412d4656ed Zero'd wfiM when ZICSR not supported to fix hang in E tests 2022-05-05 15:32:13 +00:00
David Harris
7f42ff06d2 SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
David Harris
f436e93fc5 SFENCE.VMA should be illegal in user mode 2022-05-05 14:59:52 +00:00
David Harris
9b7aab122e wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
David Harris
1a7599ce94 Changed WFI to stall pipeline in memory stage 2022-05-05 02:03:44 +00:00
Kip Macsai-Goren
b155effe66 put privileged tests back into rv32/64gc 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
895a4f4832 updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
David Harris
8a43d6099b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-03 18:32:04 +00:00
David Harris
4b91fddc0a Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
3efbd2565a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
20bbe43a23 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
1166c40059 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
bcd8728b3e Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
b4a422f771 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
057524b840 Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
9e50c3440d sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
0df73d203b Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
David Harris
9e47fca2b7 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00
Kip Macsai-Goren
75e90f193e added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
c0b56bfd27 renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
c47ec36bc7 removed old unused tests from wally arch tests 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
746fcfde30 set WFI timeout to after 16 bits of counting for all configs 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
aedf0341af added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Skylar Litz
64a537c59b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-27 10:50:19 -07:00
Skylar Litz
f2b6842edb fix AttemptedInstructionCount from ground zero 2022-04-27 10:45:40 -07:00
David Harris
515270a8cf Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
David Harris
cce0a421be Checked in torture.tv 2022-04-27 13:06:24 +00:00
David Harris
9d82232c14 Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
4b00531d77 fixed incorrect configs in regression 2022-04-25 19:28:47 +00:00
Kip Macsai-Goren
74b103fae4 added working tests to test list, updated regression for new configs 2022-04-25 19:18:15 +00:00
Kip Macsai-Goren
33875b20b5 fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
Kip Macsai-Goren
2e0f45eab4 removed atomic, floating point from privileged tests configs 2022-04-25 19:13:15 +00:00
Kip Macsai-Goren
01f8bdfafc added new tests to tests.vh, comented out until they pass regression 2022-04-25 18:22:44 +00:00
Kip Macsai-Goren
992cedbc52 Lowered WFI timeout wait time for privileged configs 2022-04-25 17:47:10 +00:00
David Harris
0957b7040d Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
1a8369b02b Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
David Harris
142636173e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
David Harris
28e8aa4f97 Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00
David Harris
ffecdda6e6 Improved priority order and mtval of traps to match spec 2022-04-24 17:24:45 +00:00
David Harris
04b0579b89 Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
bd87af478a Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address) 2022-04-22 22:46:11 +00:00
bbracker
9eec1a83a6 deprecate unused LINUX_FIX_READ macro 2022-04-21 19:14:47 -07:00
bbracker
9c1e398bb5 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
Ross Thompson
e56b9f18d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-21 09:52:42 -05:00
Ross Thompson
a86274a1e0 Modified wally-pipelined.do for no trace linux sim. 2022-04-21 09:52:33 -05:00
David Harris
1e19cf9f14 Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
Kip Macsai-Goren
25d0f6305a added new tests to tests.vh 2022-04-20 17:34:40 +00:00
Kip Macsai-Goren
8e72ace5ac fixed rv32ia to support clint and GPIO for priv tests 2022-04-20 17:31:34 +00:00
Kip Macsai-Goren
324d3fcea5 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
Ross Thompson
b94927d8a6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-19 14:09:50 -05:00
David Harris
c57b9e6703 Added baby torture tests 2022-04-19 15:13:06 +00:00
David Harris
eaa0d44980 Fixed WFI decoding in IFU 2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
ced763beb6 Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Kip Macsai-Goren
121cc627f6 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Shreya Sanghai
6f0085201b replaced k with bpred size 2022-04-18 04:21:03 +00:00
Shreya Sanghai
a8b3cc8cf9 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
22842816a8 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
61dbf13a69 Fixed bug I introduced by csrc cleanup and changes to ILA. 2022-04-17 21:45:46 -05:00
David Harris
e04febdb57 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
c07b9d1722 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
David Harris
6504017044 Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
Ross Thompson
a5d4e39e7d Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
3add26be64 fixed no forcing bug in linux testbench. 2022-04-17 17:49:51 -05:00
David Harris
d8b4c985cd Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00
David Harris
6bb4cd1bca Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
5bb521635e Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
Kip Macsai-Goren
331efcedc4 added new tests to makefrag and tests.vh 2022-04-17 21:00:36 +00:00
Ross Thompson
5a6ad32688 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-17 15:23:46 -05:00
Ross Thompson
7135364d1a Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
David Harris
b4902a6ff9 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
David Harris
6769f0cb43 Added comments in fcvt 2022-04-17 16:53:10 +00:00
David Harris
d71940d96d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
55c667b60d Commented output power analysis to speed simulation. 2022-04-16 15:32:59 -05:00
Ross Thompson
f8bdb6db49 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
bfc68bef69 Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
David Harris
0932d4df46 Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
c3bca40e05 Added WFI to the testbench instruction name decoder 2022-04-14 17:12:11 +00:00
David Harris
6e16922aae WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
bbracker
0e183be3e5 fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM 2022-04-14 09:23:21 -07:00
bbracker
489ce4269a fix ReadDataM forcing 2022-04-13 15:32:00 -07:00
Ross Thompson
65573f07b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 13:39:47 -05:00
bbracker
c697c17b05 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 05:35:56 -07:00
bbracker
016e960401 change interrupt spoofing to happen at negative clock edges 2022-04-13 04:31:23 -07:00
bbracker
3465d8cd32 improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS 2022-04-13 03:37:53 -07:00
bbracker
67ef47b25b whoops forgot to update AttemptedInstructionCount in interrupt spoofing 2022-04-13 00:49:37 -07:00
bbracker
6c3d274970 change testbench-linux to by default use attempted instruction count for warning/error messages 2022-04-12 21:22:08 -07:00
Ross Thompson
2eb2263e94 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 19:38:04 -05:00
Ross Thompson
adb4e30c45 Missed the force on uart for no tracking. 2022-04-12 19:37:44 -05:00
Ross Thompson
d087deef65 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 17:56:48 -05:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
396f697d2f Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010 Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
56bea58a3c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-10 13:41:27 -05:00
Ross Thompson
fc5eac6820 Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. 2022-04-10 13:27:54 -05:00
bbracker
c0c5733a1d upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs 2022-04-08 13:45:27 -07:00
bbracker
23406d0926 small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
Ross Thompson
de868ef3a2 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Ross Thompson
1614996941 Fixed typo in tests.vh 2022-04-07 16:28:28 -05:00
Katherine Parry
74e0db04ac fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
Kip Macsai-Goren
c3a6b88acc updated test signature locations 2022-04-06 07:28:38 +00:00
Kip Macsai-Goren
fbcb0c0bd8 Added missing ZFH macro to new configs 2022-04-06 07:13:51 +00:00
David Harris
7f462a6168 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-05 23:23:47 +00:00
David Harris
23da303ad3 Added bootmem source ccode 2022-04-05 23:22:53 +00:00
Ross Thompson
900939581e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-05 15:42:07 -05:00
Ross Thompson
5faa88acd5 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Katherine Parry
c3d07b2c46 generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
91e99f0d34 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
077beb18dd Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
b77201143f Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Ross Thompson
400b5f7632 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
38160fe6ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-03 17:56:55 -05:00
Ross Thompson
3ebb7f1057 fpga simulation works again. 2022-04-03 17:31:07 -05:00
David Harris
fb95767da0 Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
Ross Thompson
3db60a1cc1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-02 16:39:54 -05:00
Ross Thompson
2376d66ec2 Added more ILA signals. 2022-04-02 16:39:45 -05:00
Kip Macsai-Goren
37c755e6ce added RV64IA config to have a config without compressed instructions 2022-04-02 18:24:08 +00:00
Ross Thompson
691f1a6b0d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 17:18:25 -05:00
Ross Thompson
51dfa16f59 Updated the fpga test bench. 2022-04-01 17:14:47 -05:00
Ross Thompson
48c49802b2 Fixed linting issues. 2022-04-01 15:20:45 -05:00
Ross Thompson
301f20052b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 12:50:34 -05:00
Ross Thompson
19a8df9739 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
bbracker
9d26bfe71d expand WALLY-PERIPH test to use SEIP on PLIC context 1 2022-03-31 18:02:06 -07:00
bbracker
e09079d8b4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 17:54:43 -07:00
bbracker
55df8bc3f7 fix lingering overrun error bug 2022-03-31 17:54:32 -07:00
Ross Thompson
48c862d536 Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
da93d14050 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
b5cdf035fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 15:50:04 -05:00
Ross Thompson
ade4a4cd5e Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
bdb3417656 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
0f7e995055 simplify plic logic 2022-03-31 13:46:24 -07:00
David Harris
c7043e4d63 Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
Ross Thompson
88c5cdc873 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:39:41 -05:00
Ross Thompson
bf9683f0d2 Forced to go back to hard coded preload. 2022-03-31 11:39:37 -05:00
Ross Thompson
54001222cf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:38:55 -05:00
Ross Thompson
285fc6fd4d Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
David Harris
dd3af17b3f Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
David Harris
3457c6e512 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 23:06:36 +00:00
bbracker
69a0f6e00b big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
0a5b500aca Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
David Harris
9b1f85d353 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:26:27 +00:00
David Harris
08fad856e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:13:42 +00:00
Ross Thompson
e4f4e1bd43 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
f52ab01362 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
839bede656 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
Ross Thompson
997c1b87fe rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
66e9380cfb Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
Kip Macsai-Goren
d031c003ba fixed arch bge test signature output location after update 2022-03-29 20:45:18 +00:00
David Harris
03fa9084bc Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
c4f2c6b110 fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
56a0542405 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00
Kip Macsai-Goren
a6d90a25c2 fixed signature location of the new periph with no compressed instructions 2022-03-29 02:15:17 +00:00
bbracker
8ea25e591b fix typo that Madeleine found 2022-03-28 15:39:29 -07:00
Kip Macsai-Goren
709f8e6e0d fixed double multiplication on vectored interrupts 2022-03-28 19:12:31 +00:00
Kip Macsai-Goren
eb337fd3e1 added test config that doesn't use compressed instructions for privileged tests 2022-03-28 19:12:31 +00:00
Skylar Litz
f91fb7a388 add AtemptedInstructionCount signal 2022-03-26 21:28:57 +00:00
Skylar Litz
62a330c290 update to match new filesystem organization 2022-03-26 21:28:32 +00:00
Kip Macsai-Goren
7ae1d14191 added basic trap tests that do not pass regression yet. updated signature adresses 2022-03-25 22:57:41 +00:00
Ross Thompson
61c714ebe6 I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. 2022-03-25 13:10:31 -05:00
Ross Thompson
fe896bff8e Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
bbracker
6f6663cd67 fix multiple-context PLIC checkpoint generation 2022-03-25 01:02:22 +00:00
bbracker
d33de3ef6b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
4b376e2834 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
71aad2d213 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
8f74fd2a50 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-23 14:10:38 -05:00
Katherine Parry
7cf994526a fixed typo in unpack.sv 2022-03-23 18:26:59 +00:00
Ross Thompson
aa60b57fb3 Cleanup in testbench-linux.sv. 2022-03-22 22:34:38 -05:00
Ross Thompson
33b9b5423d reverted temporary change to configs. 2022-03-22 22:31:34 -05:00
Katherine Parry
fcd23a006e fixed lint error in fpudivsqrtrecur.sv 2022-03-23 03:24:41 +00:00
Ross Thompson
849707f161 Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing. 2022-03-22 22:04:06 -05:00
Ross Thompson
c233ef9768 Reverted change to configuration which caused issue with lint. 2022-03-22 21:44:08 -05:00
Ross Thompson
b2487f4b72 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Ross Thompson
4ca9458534 added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP. 2022-03-22 21:28:34 -05:00
Katherine Parry
23adb2dd03 unpack.sv cleanup 2022-03-23 01:53:37 +00:00
Ross Thompson
e6b42cb10f Added spoof of uart addresses +0x2 and +0x6. 2022-03-22 16:52:27 -05:00
Ross Thompson
ca8fb45367 Added comment about needed fix to misaligned fault. 2022-03-22 16:52:07 -05:00
Katherine Parry
e3d01c875b FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
ee4b38dce3 dtim writes are supressed on non cacheable operation. 2022-03-12 00:46:11 -06:00
Ross Thompson
86cc758354 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
7a25d577ba Added new asserts to testbench. 2022-03-11 15:41:53 -06:00
Ross Thompson
67ff8f27f4 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
9dce2a0679 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
6e24a807f6 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
b7a680ec2a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a18f06c20b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
52cc852600 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
7f0c5cc847 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
257015a2df Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
6d914def08 Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
654c4d1148 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00
Ross Thompson
1aa87c9f3a Moved subwordwrite to lsu directory. 2022-03-10 18:15:25 -06:00
Ross Thompson
d0cf41dbe4 Simplified byte write enable logic. 2022-03-10 18:13:35 -06:00
Ross Thompson
396c97fc36 Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
d8e71e8e35 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
67ef46ea92 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
David Harris
bc2b757952 bit write update 2022-03-09 19:09:20 +00:00
David Harris
27f09ffb33 Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
David Harris
89e0830883 Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
Ross Thompson
95bb4cc8a8 Minor cleanup to interlockfsm. 2022-03-08 23:38:58 -06:00
Ross Thompson
9b113149b6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-08 18:05:35 -06:00
Ross Thompson
0310fe858f Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
75e93baaee Marked signals for name changes. 2022-03-08 17:41:02 -06:00
David Harris
00908132e6 Added more test cases and rounding modes to fma test generator 2022-03-08 23:29:29 +00:00
David Harris
8fa6a85af2 fixed setup.sh merge conflict 2022-03-08 23:21:06 +00:00
David Harris
c8f2dce026 fma16_testgen.c test cases 2022-03-08 23:18:18 +00:00
Ross Thompson
3ec32d7ce8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
d78ba777a4 Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
Ross Thompson
7b96b3f73c Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
bbracker
742e8d98cd fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
92e1583db5 change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
David Harris
7391c6d338 Checked in fma16_template.v 2022-03-06 13:29:35 +00:00
David Harris
e4d18f1808 removed more old 64priv tests 2022-03-04 03:57:19 +00:00
bbracker
41c75dc89d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:12:00 +00:00
bbracker
c3e59ae2df comment out nonfunctioning CSR-PERMISSIONS-M test 2022-03-04 00:11:55 +00:00
David Harris
a50f1a4424 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:07:34 +00:00
David Harris
2cea3349ad LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
bbracker
d645666fe7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:06:27 +00:00
bbracker
79ff8d3c80 remove imperas32p tests 2022-03-04 00:06:18 +00:00
David Harris
6431ad4a8b Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
David Harris
f76e396255 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 23:47:16 +00:00
David Harris
8e83aaeced fma file fixes 2022-03-02 23:47:01 +00:00
bbracker
87aad1d953 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00
bbracker
11423d1d17 but apparently QEMU doesn't show UXL in SSTATUS 2022-03-02 22:44:19 +00:00
bbracker
6d7bc928af update SXL UXL bits in MSTATUS to match new QEMU trace 2022-03-02 22:15:57 +00:00
bbracker
e9e827c83e add CSRs to waveview 2022-03-02 18:31:10 +00:00
bbracker
4fe35aadf2 add rv32a tests to regression 2022-03-02 17:54:55 +00:00
bbracker
7d7a4fefb3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 17:46:40 +00:00
David Harris
c543fedc60 removed imperas-riscv-tests 2022-03-02 17:28:20 +00:00
bbracker
b6031bb15f fix buildroot checkpointing and add it back to regression 2022-03-02 16:00:19 +00:00
bbracker
29179c6787 add LRSC test and add wally64a to regression 2022-03-02 07:09:37 +00:00
David Harris
0ecfff7e3a FMA project ready to start 2022-03-01 20:58:08 +00:00
bbracker
d2fa5fa645 buildroot graphical sim bugfix 2022-03-01 03:24:23 +00:00
bbracker
a8e8cfb838 switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv 2022-03-01 03:11:43 +00:00
bbracker
d8ddda760b deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test 2022-03-01 00:37:46 +00:00
David Harris
329fea9329 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
David Harris
2ea93c4ac3 adrdecs comments 2022-02-28 20:33:41 +00:00
David Harris
2de31a15da Modified address decoder for native access to CLINT 2022-02-28 19:13:14 +00:00
David Harris
3a43450ac9 hptw cleanup for synthesis 2022-02-28 05:54:34 +00:00
David Harris
f4be78ecc3 Created softfloat_demo showcasing how to do math with SoftFloat 2022-02-27 18:17:21 +00:00
David Harris
dbd73e8cfd Moved regression work directories to regression/wkdir to reduce clutter 2022-02-27 17:35:09 +00:00
David Harris
3675a813c6 Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior 2022-02-27 17:23:33 +00:00
David Harris
62d62f9a9e Moved FMA back into source tree to facilitate synthesis 2022-02-27 15:41:41 +00:00
David Harris
5b15e552c6 Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue 2022-02-27 15:12:10 +00:00
David Harris
c35a071203 Moved fma directory 2022-02-27 14:20:15 +00:00
David Harris
283a25e1a7 fma simulation infrastructure 2022-02-27 04:36:43 +00:00
David Harris
40bc380073 fma passing multiply vectors 2022-02-27 04:36:01 +00:00
David Harris
f29cc4b33f simplified fma Makefile 2022-02-26 19:55:42 +00:00
David Harris
b2db58e982 Made softfloat.a a symlink 2022-02-26 19:53:04 +00:00
David Harris
a9f9cfa5b6 Added start of fma 2022-02-26 19:51:19 +00:00
David Harris
ff674b695c Moved Softfloat / TestFloat 2022-02-26 19:17:32 +00:00
Ross Thompson
730fdb029a Fixed bug with DAPageFault being wrong when HPTW writes not supported. 2022-02-23 10:54:34 -06:00
Ross Thompson
6f53f7943f More spillsupport more structual. 2022-02-23 10:27:14 -06:00
Ross Thompson
19ec874641 Fixed bug with spill support and Instruction DA Page Faults. 2022-02-23 10:16:12 -06:00
Ross Thompson
15f6871a8d Added generates to pcnextf muxes for privileged and caches. 2022-02-22 22:45:00 -06:00
Ross Thompson
834b308ed6 Fixed "bug" with wally-pipelined.do 2022-02-22 22:19:25 -06:00
Ross Thompson
59f04f2518 Minor busdp cleanup. 2022-02-22 17:28:26 -06:00
Ross Thompson
ea29291024 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-22 14:45:53 -06:00
Ross Thompson
971dd494f6 Clarified interlockfsm. 2022-02-22 11:31:28 -06:00
bbracker
2322e66f9f fix lint bugs in PLIC and UART 2022-02-22 05:04:18 +00:00
bbracker
ac114e1c6d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
202bd2f8f8 change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests 2022-02-22 03:46:08 +00:00
bbracker
c26526c9f3 change RX side of UART to aslo be LSB-first 2022-02-22 03:34:08 +00:00
Ross Thompson
1ab2e7590b Added some clearity to lsuvirtmem.sv. 2022-02-21 17:20:58 -06:00
Ross Thompson
8a280f211f Annotated IFU for mux changes. 2022-02-21 17:20:34 -06:00
Ross Thompson
ace743ae91 Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW. 2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9 Cleaned up names in lsuvirtmem. 2022-02-21 16:44:30 -06:00
Ross Thompson
3ba70b74d6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 12:46:22 -06:00
Ross Thompson
456a54166a Minor cleanup of lsu. 2022-02-21 12:46:06 -06:00
ushakya22
5f916d17d2 Moved order of reading a, b, and result from test vectors file so that result 
matches up with inputs a and b
 2022-02-21 17:28:11 +00:00
ushakya22
3abc2c0592 - created new testbench file instead of having it at the bottom of the srt file 
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench

Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
 2022-02-21 16:24:50 +00:00
ushakya22
1ea3e8120a - Created exponent divsion module 
- top module includes exponent module now

Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
 2022-02-21 16:13:30 +00:00
ushakya22
3d5b407755 Changed Makefile to compile exptestgen instead of testgen 2022-02-21 16:08:45 +00:00
ushakya22
ec3fa45f86 reverted srt_standford back to original file pre modifications by Udeema 2022-02-21 16:08:09 +00:00
ushakya22
ed452aff5f verilator lint for srt 2022-02-21 16:05:43 +00:00
ushakya22
a3a572fe5f Created test vector generation file for exponent and mantissa division 2022-02-21 16:04:41 +00:00
Ross Thompson
5d9ad011d2 Moved mux into lsuvirtmem. 2022-02-21 09:31:29 -06:00
Ross Thompson
8af055c78e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 09:06:09 -06:00
Kip Macsai-Goren
04892c5d38 added scratch register tests for 64 and 32 bits 2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
d852e8a5c1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-21 00:34:54 +00:00
Ross Thompson
a60332b455 Minor changes to LSU. 2022-02-19 14:38:17 -06:00
David Harris
4e194b2576 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7 Removed problematic warning about reaching default state in HPTW 2022-02-18 23:08:40 +00:00
Kip Macsai-Goren
324efa7d42 added 32 bit pma tests to regression even though they've been working fo a while 2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
dcb5d0f6a9 Added misa test for both 32 and 64 bits 2022-02-18 19:41:50 +00:00
Ross Thompson
0bd533473c New config option to enable hptw writes to PTE in memory to update Access and Dirty bits. 2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453 Accidentally cleared dirty bit when setting access bit in hptw. 2022-02-17 16:20:20 -06:00
Ross Thompson
7dffcba182 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-17 14:49:37 -06:00
Ross Thompson
d152733a17 Rough implementation passing regression test with hptw atomic writes to memory. 2022-02-17 14:46:11 -06:00
David Harris
3036de316a Started make allsynth to try many experiments 2022-02-17 17:57:02 +00:00
Ross Thompson
4cfb601dc8 Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB. 2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3 Broken state. address translation not working after changes to hptw to support atomic updates to PT. 2022-02-16 23:37:36 -06:00
Ross Thompson
460b37b21a Added additional suppresses to vsim command incase buildroot files are missing. 2022-02-16 17:05:54 -06:00
Ross Thompson
beac362364 Moved a few muxes around after sww changes. 2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01 cleanup of signal names. 2022-02-16 15:29:08 -06:00
Ross Thompson
84edb8b5d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 15:22:35 -06:00
Ross Thompson
bd7343b791 Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path. 2022-02-16 15:22:19 -06:00
David Harris
131a1a4ded Cleaned warning on HPTW default state 2022-02-16 17:40:13 +00:00
David Harris
799736632b Register file comments about reset 2022-02-16 17:21:05 +00:00
Ross Thompson
a64839d999 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 09:48:16 -06:00
Skylar Litz
03f23d2aaa update bugfinder script to new file organization 2022-02-15 22:58:18 +00:00
Kip Macsai-Goren
e16581d73d added CSR permission and minfor to 32 bit tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
943c4d9d7c merged test macros in with 32 bit tests 2022-02-15 20:19:14 +00:00
David Harris
72e83db9fe removed csrn and all of its outputs because depricated 2022-02-15 19:59:29 +00:00
David Harris
d3034c4f01 Mostly removed N_SUPPORTED 2022-02-15 19:50:44 +00:00
David Harris
f734afb866 Just needed to recompile - all good. Now removed uretM because N-mode is depricated 2022-02-15 19:48:49 +00:00
David Harris
1326ade1a0 Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change. 2022-02-15 19:20:41 +00:00
Kip Macsai-Goren
9ff4025844 light cleanup for privileged tests 2022-02-15 17:06:16 +00:00
Ross Thompson
6076f90bbc Cache mods to be consistant with diagrams. 2022-02-14 12:40:51 -06:00
David Harris
dee2822359 srt fixes 2022-02-14 18:40:27 +00:00
David Harris
99aacd5aca srt batch files 2022-02-14 18:37:46 +00:00
ushakya22
f4740cfda4 bring branch back into main 
Merge branch 'srt_division_with_unpacker' into main
 2022-02-14 18:25:34 +00:00
ushakya22
4170b54c28 work in progress exponent handling 2022-02-14 18:24:29 +00:00
David Harris
1d5c8a7b98 t push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-02-14 01:22:22 +00:00
Ross Thompson
1bb4d46ac1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-13 18:21:15 -06:00
Ross Thompson
e852cb8a31 Eliminated more ports in cacheway. 2022-02-13 15:53:46 -06:00
Ross Thompson
1d7949513d More cache cleanup. 2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec More cache cleanup. 2022-02-13 12:38:39 -06:00
ushakya22
f87667d120 Added unpacker into testbench for srt 2022-02-12 22:05:18 +00:00
David Harris
b360e7b941 Synthesis cleanup 2022-02-12 06:25:12 +00:00
David Harris
a34cbdb7d0 Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0 2022-02-12 05:50:34 +00:00
Ross Thompson
dd944265aa Formating improvements to cache. 2022-02-11 23:10:58 -06:00
Ross Thompson
bf173b035c More cache simplifications. 2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d Reduced seladr to 1 bit as second bit is same as selflush. 2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b Reduced complexity of the address selection during flush. 2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154 Removed redundant signals from cache. 2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f Cache fsm simplifications. 2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595 Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY. 2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24 Simplified cache fsm. 2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662 Fixed bug. 
It was possible for DTLBMissM to prevent a dcache flush.
 2022-02-11 14:00:01 -06:00
Ross Thompson
33beaa4593 Updates to linux wave. 2022-02-11 13:28:18 -06:00
Ross Thompson
d9f77d3659 Updated linux wave. 2022-02-11 13:15:42 -06:00
Ross Thompson
1a1629c62f linux wave cleanup. 2022-02-11 10:48:45 -06:00
Ross Thompson
febd019854 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-11 10:47:21 -06:00
Ross Thompson
6d12010d02 Fixed subtle and infrequenct bug. 
Loading buildroot at 483M instructions started with a spill + ITLBMiss.  The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation.  However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation.  Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
 2022-02-11 10:46:06 -06:00
David Harris
de5e80696d Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
Ross Thompson
689c32215f Fixed bugs in ifu spills and missing reset on bus data register. 2022-02-10 18:11:57 -06:00
Ross Thompson
9fb612d4ff Updated wave files to reflect recent changes. 2022-02-10 17:52:19 -06:00
Ross Thompson
5fd22caed4 Replacement policy cleanup. 2022-02-10 11:42:40 -06:00
Ross Thompson
f716cce832 Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
104a9acf81 Cleanup. 2022-02-10 11:27:15 -06:00
Ross Thompson
fdb4f909fc Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
88c7a94aa9 Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
32eee5a06a More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
91f2b5adf5 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
7ff715f44f More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
754bd41fde Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
36ab78ef3b Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
4fd0154d03 Added commented out commands to generate saif file from vsim. 2022-02-09 18:40:45 -06:00
Ross Thompson
7810a09782 Annotated the final changes required to move sram address off the critial path. 2022-02-08 18:17:31 -06:00
Ross Thompson
30d6514661 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 17:52:15 -06:00
Ross Thompson
4a7ebb3757 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
bdb3794d5e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 15:43:18 -06:00
Ross Thompson
c2907ec0f4 Cleanup IFU. 2022-02-08 14:54:53 -06:00
Ross Thompson
038897f448 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:47:15 -06:00
Ross Thompson
4273775a2b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:22:19 -06:00
Ross Thompson
e02bc8db67 rv32e works for now. Still need to optimize. 2022-02-08 14:21:55 -06:00
Ross Thompson
f211fe635a Moved some muxes back into the bp. 2022-02-08 14:17:44 -06:00
David Harris
1479762ae9 RAM simplification 2022-02-08 20:15:23 +00:00
Ross Thompson
aa12d90272 Temporary commit which gets the no branch predictor implementation working. 2022-02-08 14:13:55 -06:00
David Harris
510b47523a rv32e config update 2022-02-08 17:59:50 +00:00
Ross Thompson
853a7bba18 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 11:36:30 -06:00
Ross Thompson
8a2ee22395 Finished merge. 2022-02-08 11:36:24 -06:00
David Harris
64e9f4c0d3 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00
Ross Thompson
e2191e3637 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
David Harris
f00b3ac27e Fixed TIM tests; rv32e test still failing 2022-02-08 15:24:37 +00:00
David Harris
76dccbad91 Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail 2022-02-08 12:40:02 +00:00
David Harris
c61cd55c5c Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
David Harris
cbef88ec10 Lab 3 file cleanup 2022-02-08 10:26:37 +00:00
Ross Thompson
5c9e23527d cachefsm cleanup. 2022-02-07 22:09:56 -06:00
Ross Thompson
da2dca9816 Removed VDWriteEnable. 2022-02-07 21:59:18 -06:00
Ross Thompson
161f907cae more partial cleanup of fsm and write enables. 2022-02-07 17:41:56 -06:00
Ross Thompson
359a23237d Progress towards simplifying the cache's write enables. 2022-02-07 17:23:09 -06:00
Ross Thompson
188fe28691 more cleanup. 2022-02-07 13:29:19 -06:00
Ross Thompson
9510a33c15 More cachefsm cleanup. 2022-02-07 13:19:37 -06:00
Ross Thompson
708e0cf183 More cachefsm cleanup. 2022-02-07 12:30:27 -06:00
Ross Thompson
5539a5fa6f More cachefsm cleanup. 2022-02-07 11:16:20 -06:00
Ross Thompson
6668956351 More cachefsm cleanup. 2022-02-07 11:12:28 -06:00
Ross Thompson
5536e3ca90 More cachefsm cleanup. 2022-02-07 10:54:22 -06:00
Ross Thompson
529d8b629a Cache cleanup. 2022-02-07 10:43:58 -06:00
Ross Thompson
41a79556e0 More cachfsm cleanup. 2022-02-07 10:33:50 -06:00
David Harris
99f3d7a7f6 Reverted cache change 2022-02-07 14:47:20 +00:00
David Harris
50b44b4416 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-07 14:43:31 +00:00
David Harris
45dc9c1ae6 Cache syntax cleanup 2022-02-07 14:43:24 +00:00
Ross Thompson
0b66106925 More cachefsm cleanup. 2022-02-06 21:50:44 -06:00
Ross Thompson
dd6baa9ed4 started cachefsm cleanup. 2022-02-06 21:39:38 -06:00
Kip Macsai-Goren
0eb280b314 added new tests to make and testbench 2022-02-06 19:47:22 +00:00
David Harris
9b55848ffc Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
bbracker
f67af23bf3 remove sporadic tabs from tests.vh so that it is now only spaces 2022-02-05 23:07:38 +00:00
bbracker
74ef58e20e remove rv32e from regression because it is broken; goes with previous commit 2022-02-05 23:05:21 +00:00
Ross Thompson
d21be9d998 Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
David Harris
0f7b8017d1 Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit 2022-02-05 05:35:51 +00:00
David Harris
a9d2386010 Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts 2022-02-05 05:28:40 +00:00
David Harris
66b4834ef5 Modified wally-pipelined-batch.do to handle buildroot 2022-02-05 05:07:07 +00:00
Ross Thompson
ea84211ff9 Removed unused ports from caches and buses. 2022-02-04 22:52:51 -06:00
Ross Thompson
011ad09341 Cleanup. 2022-02-04 22:40:51 -06:00
Ross Thompson
4074f695e0 Moved the hwdata mux back into the busdp. 2022-02-04 22:39:13 -06:00
Ross Thompson
40eb055861 Merged together the two sub cache line read muxes. 
One mux was used for loads and the other for eviction.
 2022-02-04 22:30:04 -06:00
David Harris
72bc64ef28 Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
Ross Thompson
290430cda8 Moved the sub cache line read logic to lsu/ifu. 2022-02-04 20:42:53 -06:00
Ross Thompson
725852362e Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00
Ross Thompson
cdd599e340 Second optimization of save/restore. 2022-02-04 14:35:12 -06:00
Ross Thompson
459054900f Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
7c1f7e335c Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
2c67f32b97 RV32e tests 2022-02-04 14:30:36 +00:00
David Harris
fb041fe06a rv32e 2022-02-04 01:56:30 +00:00
David Harris
ef5af9b5fd renamed configs 2022-02-03 23:36:41 +00:00
David Harris
ee3300bcd2 sram1rw cleanup 2022-02-03 18:03:22 +00:00
David Harris
97d31cec21 sram1rw cleanup 2022-02-03 17:50:23 +00:00
David Harris
f9dd79d3e3 cachereplacementpolicy cleanup 2022-02-03 17:19:14 +00:00
David Harris
034ff5462c cachereplacementpolicy cleanup 2022-02-03 17:18:48 +00:00
David Harris
65f3bf4e0a cacheway cleanup 2022-02-03 16:52:22 +00:00
David Harris
eef04eed84 cacheway cleanup 2022-02-03 16:33:01 +00:00
David Harris
4d09510af9 cacheway cleanup 2022-02-03 16:07:55 +00:00
David Harris
7f237220dd cacheway cleanup 2022-02-03 16:00:57 +00:00
David Harris
a6708ed887 cache cleanup 2022-02-03 15:36:11 +00:00
Ross Thompson
b642a19e12 Merge branch 'makefiles' into main 2022-02-03 08:33:50 -06:00
Ross Thompson
c34907c95b Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the 
regression directory.  Makefile calls the submakefiles for generating elf files.
The second makefile-memfiles generates the memfiles, addr, and label files.
 2022-02-03 08:32:48 -06:00
Ross Thompson
9336682749 Manged to get all the tests compiled and converted to memfiles using new makefiles. 2022-02-03 00:00:15 -06:00
Ross Thompson
06c5a825c4 Quick patch to regression-wally to "fix" rv32ic. 2022-02-02 19:24:24 -06:00
Ross Thompson
5c640b6582 broken makefiles. 2022-02-02 19:15:11 -06:00
Ross Thompson
943dff106e Broken makefiles. 2022-02-02 19:14:42 -06:00
David Harris
38bbe23d14 More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
David Harris
da8819d64b changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
David Harris
68a6b4af3d Removed Busybear and Buildroot Configuration 2022-02-02 20:32:22 +00:00
David Harris
02071700d6 Removed Busybear dependencies 2022-02-02 20:28:21 +00:00
Ross Thompson
98990a294c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-02 11:41:54 -06:00
Ross Thompson
f4a553fd7d Fixed testbench so coremark stops. 2022-02-02 11:37:48 -06:00
David Harris
4ba37d5cc0 Config file & wally-riscv-arch-test cleanup 2022-02-02 16:35:52 +00:00
Ross Thompson
2d827bf8c0 Added helpful signals to wavefile. 
Makefile for tests now creates the function address to name mapping files.
The function name and test name are included in the wave file.
 2022-02-02 10:15:54 -06:00
Ross Thompson
4b4cee3ddd Added correct stop condition for coremark. 2022-02-02 09:53:51 -06:00
Ross Thompson
143bdaa288 Modified makefiles to generate function address to name mappings for modelsim. 2022-02-01 18:25:03 -06:00
Ross Thompson
f055441ecf Improved function_radix to not printout warnings when no valid function is found. 2022-02-01 18:03:09 -06:00
Ross Thompson
5407b72af9 Setup the main regression test to be able to handle coremark. 2022-02-01 17:00:11 -06:00
Ross Thompson
6c5b0bec40 More cleanup of IFU. 2022-02-01 14:32:27 -06:00
Ross Thompson
85d510e315 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-01 10:50:38 -06:00
Ross Thompson
73edd50120 Updated fpga's bootloader to reflect the changes to the gpio address change. 2022-02-01 10:43:24 -06:00
Ross Thompson
1f0821da0d IFU and LSU now share the same busdp module. 2022-01-31 16:25:41 -06:00
Ross Thompson
86bac2a083 partial ifu cleanup. 2022-01-31 16:08:53 -06:00
Ross Thompson
e4ee630a3e cleanup. 2022-01-31 13:29:04 -06:00
Ross Thompson
5ce8dd60c5 Fixed modelsim warning with linux simulation. 2022-01-31 12:57:02 -06:00
Ross Thompson
c9a163b8fd Repaired linux-wave.do 2022-01-31 12:54:18 -06:00
Ross Thompson
4422e2f91c Repaired wavefile and fixed modelsim warning. 2022-01-31 12:34:17 -06:00
Ross Thompson
c2b2fae98d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-31 12:17:37 -06:00
Ross Thompson
f4e62bcb54 Cleanup busdp. 2022-01-31 12:17:07 -06:00
Ross Thompson
31da37dd0f Moved lsu virtual memory logic into separate module. 2022-01-31 11:56:03 -06:00
Ross Thompson
9cd502d0af Encapsulated dtim. 2022-01-31 11:23:55 -06:00
Ross Thompson
c939eb20eb Removed unused signals in the LSU. 2022-01-31 10:35:35 -06:00
Ross Thompson
5fe30ff8a9 Moved atomic logic to own module. 2022-01-31 10:28:12 -06:00
Ross Thompson
a4f6653cd8 Encapsulated the bus data path into a separate module. 2022-01-31 10:15:48 -06:00
Kip Macsai-Goren
242b27705d added machine info test that uses new test library 2022-01-31 05:54:43 +00:00
David Harris
090533cfe9 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
Ross Thompson
ac50a36aac LSU and IFU cleanup. 2022-01-28 15:26:06 -06:00
Ross Thompson
2e00186eea Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
Ross Thompson
42d60235f0 Clean up of mmu instances in IFU and LSU. 2022-01-28 14:02:05 -06:00
Ross Thompson
c5e0024e9f Moved spills to own module. 2022-01-28 13:40:35 -06:00
Ross Thompson
06209c417f Cleaned up the InstrMisalignedFault. 2022-01-28 13:19:24 -06:00
Ross Thompson
862bf2faae Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
d15cb64bdf Relocated the misalignment faults. 2022-01-27 16:03:00 -06:00
David Harris
30cc27e719 IFU cleanup 2022-01-27 17:18:55 +00:00
David Harris
5ab06fef20 IFU cleanup 2022-01-27 16:41:57 +00:00
David Harris
bdd5796f3a Optimized out second adder from IFU for PC+2 2022-01-27 16:06:24 +00:00
David Harris
7f91170bab Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00