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Preparing to make a major change to the cache's write enables.

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This commit is contained in:
Ross Thompson 2022-02-08 09:47:01 -06:00
parent 5c9e23527d
commit e2191e3637
2 changed files with 11 additions and 8 deletions
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7
pipelined/src/cache/cache.sv vendored
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@ -121,8 +121,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
// Array of cache ways, along with victim, hit, dirty, and read merging logic
cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](
.clk, .reset, .RAdr, .PAdr,
.WriteEnable(SRAMWayWriteEnable),
.WriteWordEnable(SRAMWordEnable),
.SRAMWayWriteEnable,
.SRAMWordEnable,
.TagWriteEnable(SRAMLineWayWriteEnable),
.WriteData(SRAMWriteData),
.SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay),
@ -157,9 +157,12 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
/////////////////////////////////////////////////////////////////////////////////////////////
// *** Ross considering restructuring
// move decoder and wordwritenable into cacheway.
onehotdecoder #(LOGWPL) adrdec(
.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded; // OR
assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0; // AND
assign SRAMWordWayWriteEnable = SRAMWordWriteEnable ? WayHit : '0; // AND
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWayWriteEnable), .d1(VictimWay),

12
pipelined/src/cache/cacheway.sv vendored
View File

@ -37,8 +37,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
input logic [$clog2(NUMLINES)-1:0] RAdr,
input logic [`PA_BITS-1:0] PAdr,
input logic WriteEnable,
input logic [LINELEN/`XLEN-1:0] WriteWordEnable,
input logic SRAMWayWriteEnable,
input logic [LINELEN/`XLEN-1:0] SRAMWordEnable,
input logic TagWriteEnable,
input logic [LINELEN-1:0] WriteData,
input logic SetValid,
@ -68,7 +68,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
logic [$clog2(NUMLINES)-1:0] RAdrD;
logic SetValidD, ClearValidD;
logic SetDirtyD, ClearDirtyD;
logic WriteEnableD;
logic SRAMWayWriteEnableD;
/////////////////////////////////////////////////////////////////////////////////////////////
// Tag Array
@ -93,7 +93,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr),
.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
.WriteEnable(SRAMWayWriteEnable & SRAMWordEnable[words]));
end
// AND portion of distributed read multiplexers
@ -112,8 +112,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
end
// *** consider revisiting whether these delays are the best option?
flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable},
{SetValidD, ClearValidD, WriteEnableD});
flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, SRAMWayWriteEnable},
{SetValidD, ClearValidD, SRAMWayWriteEnableD});
assign Valid = ValidBits[RAdrD];
/////////////////////////////////////////////////////////////////////////////////////////////