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Clean up of mmu instances in IFU and LSU.

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This commit is contained in:
Ross Thompson 2022-01-28 14:02:05 -06:00
parent c5e0024e9f
commit 42d60235f0
2 changed files with 32 additions and 37 deletions
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59
pipelined/src/ifu/ifu.sv
View File

@ -130,41 +130,38 @@ module ifu (
assign {SelNextSpillF, CompressedF} = 0;
end
assign PCFExt = {2'b00, PCFSpill};
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
immu(.PAdr(PCFExt[`PA_BITS-1:0]),
.VAdr(PCFSpill),
.Size(2'b10),
.PTE(PTE),
.PageTypeWriteVal(PageType),
.TLBWrite(ITLBWriteF),
.TLBFlush(ITLBFlushF),
.PhysicalAddress(PCPF),
.TLBMiss(ITLBMissF),
.InstrPageFaultF,
.ExecuteAccessF(1'b1),
.AtomicAccessM(1'b0),
.ReadAccessM(1'b0),
.WriteAccessM(1'b0),
.LoadAccessFaultM(),
.StoreAmoAccessFaultM(),
.LoadPageFaultM(), .StoreAmoPageFaultM(),
.LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
.DisableTranslation(1'b0), // *** is there a better name
.Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(),
////////////////////////////////////////////////////////////////////////////////////////////////
// Memory management
////////////////////////////////////////////////////////////////////////////////////////////////
.clk, .reset,
.SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
.STATUS_MPP,
.PrivilegeModeW,
.InstrAccessFaultF,
.PMPCFG_ARRAY_REGW,
.PMPADDR_ARRAY_REGW
);
if(`ZICSR_SUPPORTED == 1) begin : immu
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .DisableTranslation(1'b0),
.PAdr(PCFExt[`PA_BITS-1:0]),
.VAdr(PCFSpill),
.Size(2'b10),
.PTE(PTE),
.PageTypeWriteVal(PageType),
.TLBWrite(ITLBWriteF),
.TLBFlush(ITLBFlushF),
.PhysicalAddress(PCPF),
.TLBMiss(ITLBMissF),
.Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(),
.InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
.InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
.LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
.AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0),
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
end else begin
assign {ITLBMissF, InstrAccessFaultF} = '0;
assign InstrPageFaultF = '0;
assign PCPF = PCF;
assign CacheableF = '1;
end
// conditional
// 1. ram // controlled by `MEM_IROM
// 2. cache // `MEM_ICACHE

10
pipelined/src/lsu/lsu.sv
View File

@ -181,15 +181,13 @@ module lsu (
.TLBFlush(DTLBFlushM),
.PhysicalAddress(LSUPAdrM),
.TLBMiss(DTLBMissM),
.Cacheable(CacheableM),
.Idempotent(), .AtomicAllowed(),
.Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(),
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAmoAccessFaultM,
.InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM,
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), // **** change this to just use PreLSURWM
.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
);
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
// *** lsumisaligned lsumisaligned(Funct3M, IEUAdrM, MemRW, LoadMisalignedFaultM, StoreAmoMisalignedFaultM);
// *** lump into lsumislaigned module
@ -201,9 +199,9 @@ module lsu (
end else begin
assign {DTLBMissM, LoadAccessFaultM, StoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
assign LSUPAdrM = PreLSUPAdrM;
assign CacheableM = 1;
assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
assign LSUPAdrM = PreLSUPAdrM;
assign CacheableM = '1;
end
assign LSUStallM = DCacheStallM | InterlockStall | BusStall;