forked from Github_Repos/cvw
IFU cleanup
This commit is contained in:
David Harris
parent
5ab06fef20
commit
30cc27e719
@ -111,12 +111,15 @@ module ifu (
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logic ICacheFetchLine;
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logic BusStall;
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logic ICacheStallF, IFUCacheBusStallF;
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logic IgnoreRequest;
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logic CPUBusy;
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(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF;
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localparam integer SPILLTHRESHOLD = `MEM_ICACHE ? `ICACHE_LINELENINBITS/32 : 1;
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Spill Support *** add other banners
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////////////////////////////////////////////////////////////////////////////////////////////////
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if(`C_SUPPORTED) begin : SpillSupport
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logic [`XLEN-1:0] PCPlus2F;
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logic TakeSpillF;
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@ -156,7 +159,6 @@ module ifu (
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assign SelNextSpillF = (CurrState == STATE_SPILL_READY & TakeSpillF) |
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(CurrState == STATE_SPILL_SPILL & IFUCacheBusStallF);
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assign SpillSaveF = (CurrState == STATE_SPILL_READY) & TakeSpillF;
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flopenr #(16) SpillInstrReg(.clk(clk),
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.en(SpillSaveF),
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@ -189,13 +191,13 @@ module ifu (
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.PhysicalAddress(PCPF),
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.TLBMiss(ITLBMissF),
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.TLBPageFault(ITLBInstrPageFaultF),
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.ExecuteAccessF(1'b1), // ***dh -- this should eventually change to only true if an instruction fetch is occurring
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.ExecuteAccessF(1'b1),
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.AtomicAccessM(1'b0),
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.ReadAccessM(1'b0),
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.WriteAccessM(1'b0),
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.LoadAccessFaultM(),
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.StoreAccessFaultM(),
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.DisableTranslation(1'b0),
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.DisableTranslation(1'b0), // *** is there a better name
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.Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(),
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.clk, .reset,
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@ -216,6 +218,9 @@ module ifu (
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// If we have `MEM_IROM we don't have the bus controller
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// otherwise we have the bus controller and either a cache or a passthrough.
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// *** make this area look like LSU, including moving I$. Hide localparams in submodules when feasible
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localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LOGWPL = `MEM_ICACHE ? $clog2(WORDSPERLINE) : 1;
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localparam integer LINELEN = `MEM_ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
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@ -259,7 +264,7 @@ module ifu (
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assign IFUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIFUBusAdr;
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busfsm #(WordCountThreshold, LOGWPL, `MEM_ICACHE)
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busfsm(.clk, .reset, .IgnoreRequest,
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busfsm(.clk, .reset, .IgnoreRequest(ITLBMissF),
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.LSURWM(2'b10), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0),
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.LSUBusAck(IFUBusAck),
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.CPUBusy, .CacheableM(CacheableF),
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@ -268,37 +273,38 @@ module ifu (
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end
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// *** in same generate with bus
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if(`MEM_ICACHE) begin : icache
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logic [1:0] IFURWF;
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assign IFURWF = CacheableF ? 2'b10 : 2'b00;
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logic [`XLEN-1:0] FinalInstrRawF_FIXME;
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0))
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icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .CacheMemWriteData(ICacheMemWriteData) , .CacheBusAck(ICacheBusAck),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .ReadDataWord(FinalInstrRawF_FIXME),
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.CacheFetchLine(ICacheFetchLine),
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.CacheWriteLine(),
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.ReadDataLineSets(),
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.CacheMiss(ICacheMiss),
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.CacheAccess(ICacheAccess),
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.FinalWriteData('0),
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.RW(IFURWF),
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.Atomic(2'b00),
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.FlushCache(1'b0),
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.NextAdr(PCNextFSpill[11:0]),
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.PAdr(PCPF),
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.CacheCommitted(),
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.InvalidateCacheM(InvalidateICacheM));
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logic [1:0] IFURWF;
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assign IFURWF = CacheableF ? 2'b10 : 2'b00;
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logic [`XLEN-1:0] FinalInstrRawF_FIXME;
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0))
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icache(.clk, .reset, .CPUBusy, .IgnoreRequest(ITLBMissF), .CacheMemWriteData(ICacheMemWriteData) , .CacheBusAck(ICacheBusAck),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .ReadDataWord(FinalInstrRawF_FIXME),
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.CacheFetchLine(ICacheFetchLine),
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.CacheWriteLine(),
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.ReadDataLineSets(),
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.CacheMiss(ICacheMiss),
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.CacheAccess(ICacheAccess),
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.FinalWriteData('0),
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.RW(IFURWF),
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.Atomic(2'b00),
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.FlushCache(1'b0),
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.NextAdr(PCNextFSpill[11:0]),
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.PAdr(PCPF),
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.CacheCommitted(),
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.InvalidateCacheM(InvalidateICacheM));
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assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
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assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
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end else begin
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assign ICacheFetchLine = 0;
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assign ICacheBusAdr = 0;
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assign ICacheStallF = 0;
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if(!`MEM_IROM) assign FinalInstrRawF = 0;
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assign ICacheFetchLine = 0;
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assign ICacheBusAdr = 0;
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assign ICacheStallF = 0;
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if(!`MEM_IROM) assign FinalInstrRawF = 0; // *** move
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assign ICacheAccess = CacheableF;
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assign ICacheMiss = CacheableF;
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end
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@ -311,24 +317,17 @@ module ifu (
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// select between dcache and direct from the BUS. Always selected if no dcache.
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// handled in the busfsm.
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mux2 #(32) UnCachedInstrMux(.d0(FinalInstrRawF),
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.d1(ICacheMemWriteData[31:0]),
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.s(SelUncachedAdr),
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.y(InstrRawF));
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mux2 #(32) UnCachedInstrMux(.d0(FinalInstrRawF), .d1(ICacheMemWriteData[31:0]), .s(SelUncachedAdr), .y(InstrRawF));
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assign IFUCacheBusStallF = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallF | SelNextSpillF;
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assign CPUBusy = StallF & ~SelNextSpillF;
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//assign IgnoreRequest = ITLBMissF | ExceptionM | PendingInterruptM;
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// this is a difference with the dcache.
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// uses interlock fsm.
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assign IgnoreRequest = ITLBMissF;
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flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
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assign PrivilegedChangePCM = RetM | TrapM;
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// *** move unnecessary muxes into BPRED_ENABLED
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
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mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
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// The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE.
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@ -338,13 +337,12 @@ module ifu (
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(PCBPWrongInvalidate));
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mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
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assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
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flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
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// branch and jump predictor
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if (`BPRED_ENABLED) begin : bpred
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// *** move the rest of this hardware into branch predictor including instruction class registers
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logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), .d(BPPredWrongE), .q(BPPredWrongM));
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@ -414,17 +412,15 @@ module ifu (
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flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
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assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM;
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assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path
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// *** likely leave TrapMisalignedFaultM out of here. Don't implement full spec because
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// *** it seems silly to have a misaligned trap handler and it adds to the critical path.
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// ***later revisit more detail
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// Instruction and PC/PCLink pipeline registers
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flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE);
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flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM);
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flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
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flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
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// seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL.
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// either have ALU compute PC+2/4 and feed into ALUResult input of ResultMux or
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// have dedicated adder in Mem stage based on PCM + 2 or 4
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// *** redo this
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flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
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flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
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endmodule
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