forked from Github_Repos/cvw
t push
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
1d5c8a7b98
@ -174,7 +174,7 @@ add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/MulDi
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/DivBusyE
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add wave -noupdate -group icache -color Gold /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/CurrState
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/BasePAdrF
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||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/WayHit
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/HitWay
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/genblk1/cachereplacementpolicy/EncVicWay
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||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/VictimWay
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||||
@ -251,7 +251,7 @@ add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipel
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add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/InstrReadF
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||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/InstrAckF
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||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/ICacheMemWriteData
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||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/ICacheBusWriteData
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||||
add wave -noupdate -group AHB -color Gold /testbench/dut/wallypipelinedsoc/core/ebu/BusState
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||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/NextBusState
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/wallypipelinedsoc/core/ebu/AtomicMaskedM
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||||
@ -285,7 +285,7 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipeline
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SelAdrM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataBlockM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/DCacheMemWriteData
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/DCacheBusWriteData
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FlushWay
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimDirty
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VDWriteEnableWay
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@ -349,23 +349,23 @@ add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearValid
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetDirty
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearDirty
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||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/WayHit}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/HitWay}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/Valid}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/Dirty}
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||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/ReadTag}
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||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/HitWay}
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||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/Valid}
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||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/ReadTag}
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||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/HitWay
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||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataBlockWayMaskedM
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||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataWordM
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||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataWordMuxM
|
||||
@ -385,7 +385,7 @@ add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /t
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||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataM
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||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/DCacheStallM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FlushAdrFlag
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||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FetchCount
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||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FetchCountFlag
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||||
|
||||
@ -183,12 +183,12 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLB
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
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||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
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||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/WayHit
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||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
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||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
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||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
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||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
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||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
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||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheMemWriteData
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||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusWriteData
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
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||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
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||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
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@ -211,9 +211,9 @@ add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA
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||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA
|
||||
add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
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add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/WayHit
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||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FSMLineWriteEn
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||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FSMWordWriteEn
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||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
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||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest
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add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
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@ -227,7 +227,7 @@ add wave -noupdate -group lsu -group dcache -expand -group flush /testbench/dut/
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add wave -noupdate -group lsu -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
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add wave -noupdate -group lsu -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
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||||
add wave -noupdate -group lsu -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
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add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData
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add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
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add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
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||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
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@ -298,23 +298,23 @@ add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -
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add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
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||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/WayHit}
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||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WayHit}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/WayHit}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/WayHit}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/WayHit
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
||||
@ -327,11 +327,11 @@ add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM
|
||||
add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/WayHit
|
||||
add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
|
||||
@ -176,7 +176,7 @@ add wave -noupdate -group muldiv /testbench/dut/core/mdu/MulDivResultW
|
||||
add wave -noupdate -group muldiv /testbench/dut/core/mdu/DivBusyE
|
||||
add wave -noupdate -group icache -color Gold /testbench/dut/core/ifu/bus/icache/controller/CurrState
|
||||
add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/BasePAdrF
|
||||
add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/WayHit
|
||||
add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/HitWay
|
||||
add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/VictimWay
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/SetValid}
|
||||
@ -211,7 +211,7 @@ add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/b
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/InstrReadF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/InstrAckF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/ICacheMemWriteData
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/ICacheBusWriteData
|
||||
add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM
|
||||
@ -244,7 +244,7 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SelAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/ReadDataBlockM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/DCacheMemWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/DCacheBusWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetDirty}
|
||||
@ -304,23 +304,23 @@ add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordMuxM
|
||||
@ -340,7 +340,7 @@ add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/ReadDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/DCacheStallM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/FlushAdrFlag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu.bus.dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/FetchCount
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/FetchCountFlag
|
||||
|
||||
File diff suppressed because one or more lines are too long
66
pipelined/src/cache/cache.sv
vendored
66
pipelined/src/cache/cache.sv
vendored
@ -56,7 +56,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
|
||||
output logic CacheWriteLine,
|
||||
input logic CacheBusAck,
|
||||
output logic [`PA_BITS-1:0] CacheBusAdr,
|
||||
input logic [LINELEN-1:0] CacheMemWriteData,
|
||||
input logic [LINELEN-1:0] CacheBusWriteData,
|
||||
output logic [LINELEN-1:0] ReadDataLine);
|
||||
|
||||
// Cache parameters
|
||||
@ -68,16 +68,16 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
|
||||
localparam WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam FlushAdrThreshold = NUMLINES - 1;
|
||||
|
||||
logic [1:0] SelAdr;
|
||||
logic SelAdr;
|
||||
logic [SETLEN-1:0] RAdr;
|
||||
logic [LINELEN-1:0] CacheWriteData;
|
||||
logic SetValid, ClearValid;
|
||||
logic SetDirty, ClearDirty;
|
||||
logic ClearValid;
|
||||
logic ClearDirty;
|
||||
logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
|
||||
logic [NUMWAYS-1:0] WayHit;
|
||||
logic [NUMWAYS-1:0] HitWay, HitWaySaved, HitWayFinal;
|
||||
logic CacheHit;
|
||||
logic FSMWordWriteEn;
|
||||
logic FSMLineWriteEn;
|
||||
logic SetDirty;
|
||||
logic SetValid;
|
||||
logic [NUMWAYS-1:0] VictimWay;
|
||||
logic [NUMWAYS-1:0] VictimDirtyWay;
|
||||
logic VictimDirty;
|
||||
@ -97,10 +97,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
|
||||
logic LRUWriteEn;
|
||||
logic SelFlush;
|
||||
logic ResetOrFlushAdr, ResetOrFlushWay;
|
||||
logic [NUMWAYS-1:0] WayHitSaved, WayHitFinal;
|
||||
logic [NUMWAYS-1:0] SelectedWay;
|
||||
logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
|
||||
logic [NUMWAYS-1:0] WriteWordWayEn, WriteLineWayEn;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Read Path
|
||||
@ -110,19 +108,19 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
|
||||
// and FlushAdr when handling D$ flushes
|
||||
mux3 #(SETLEN) AdrSelMux(
|
||||
.d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr),
|
||||
.s(SelAdr), .y(RAdr));
|
||||
.s({SelFlush, SelAdr}), .y(RAdr));
|
||||
|
||||
// Array of cache ways, along with victim, hit, dirty, and read merging logic
|
||||
cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](
|
||||
.clk, .reset, .RAdr, .PAdr, .WriteWordWayEn, .WriteLineWayEn, .CacheWriteData,
|
||||
.clk, .reset, .RAdr, .PAdr, .CacheWriteData,
|
||||
.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
|
||||
.FlushWay, .SelFlush, .ReadDataLineWay, .WayHit, .VictimDirtyWay, .VictimTagWay,
|
||||
.InvalidateAll(InvalidateCacheM));
|
||||
.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay,
|
||||
.Invalidate(InvalidateCacheM));
|
||||
if(NUMWAYS > 1) begin:vict
|
||||
cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
|
||||
.clk, .reset, .WayHit(WayHitFinal), .VictimWay, .PAdr, .RAdr, .LRUWriteEn);
|
||||
.clk, .reset, .HitWay(HitWayFinal), .VictimWay, .PAdr, .RAdr, .LRUWriteEn);
|
||||
end else assign VictimWay = 1'b1; // one hot.
|
||||
assign CacheHit = | WayHit;
|
||||
assign CacheHit = | HitWay;
|
||||
assign VictimDirty = | VictimDirtyWay;
|
||||
// ReadDataLineWay is a 2d array of cache line len by number of ways.
|
||||
// Need to OR together each way in a bitwise manner.
|
||||
@ -130,69 +128,59 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
|
||||
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine));
|
||||
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
|
||||
|
||||
|
||||
// Because of the sram clocked read when the ieu is stalled the read data maybe lost.
|
||||
// There are two ways to resolve. 1. We can replay the read of the sram or we can save
|
||||
// the data. Replay is eaiser but creates a longer critical path.
|
||||
// save/restore only wayhit and readdata.
|
||||
if(!`REPLAY) begin
|
||||
flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHit, WayHitSaved);
|
||||
mux2 #(NUMWAYS) saverestoremux(WayHit, WayHitSaved, restore, WayHitFinal);
|
||||
end else assign WayHitFinal = WayHit;
|
||||
flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, HitWay, HitWaySaved);
|
||||
mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal);
|
||||
end else assign HitWayFinal = HitWay;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Write Path: Write data and address. Muxes between writes from bus and writes from CPU.
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
|
||||
.d1(CacheMemWriteData), .s(FSMLineWriteEn), .y(CacheWriteData));
|
||||
.d1(CacheBusWriteData), .s(SetValid), .y(CacheWriteData));
|
||||
mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||
.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
|
||||
.s({SelFlush, SelEvict}),
|
||||
.y(CacheBusAdr));
|
||||
.s({SelFlush, SelEvict}), .y(CacheBusAdr));
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Flush address and way generation during flush
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
assign ResetOrFlushAdr = reset | FlushAdrCntRst;
|
||||
flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr),
|
||||
.en(FlushAdrCntEn), .d(FlushAdrP1), .q(FlushAdr));
|
||||
flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn),
|
||||
.d(FlushAdrP1), .q(FlushAdr));
|
||||
assign FlushAdrP1 = FlushAdr + 1'b1;
|
||||
assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]);
|
||||
|
||||
assign ResetOrFlushWay = reset | FlushWayCntRst;
|
||||
flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay),
|
||||
.en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}),
|
||||
.d(NextFlushWay), .q(FlushWay));
|
||||
flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn),
|
||||
.val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay));
|
||||
assign FlushWayFlag = FlushWay[NUMWAYS-1];
|
||||
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Write Path: Write Enables
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// *** change to structural
|
||||
mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, {SelFlush, FSMLineWriteEn}, SelectedWay);
|
||||
mux3 #(NUMWAYS) selectwaymux(HitWayFinal, VictimWay, FlushWay,
|
||||
{SelFlush, SetValid}, SelectedWay);
|
||||
assign SetValidWay = SetValid ? SelectedWay : '0;
|
||||
assign ClearValidWay = ClearValid ? SelectedWay : '0;
|
||||
assign SetDirtyWay = SetDirty ? SelectedWay : '0;
|
||||
assign ClearDirtyWay = ClearDirty ? SelectedWay : '0;
|
||||
assign WriteWordWayEn = FSMWordWriteEn ? SelectedWay : '0;
|
||||
assign WriteLineWayEn = FSMLineWriteEn ? SelectedWay : '0;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Cache FSM
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
|
||||
.RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM,
|
||||
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
|
||||
.CacheMiss, .CacheAccess, .SelAdr, .SetValid,
|
||||
.ClearValid, .SetDirty, .ClearDirty, .FSMWordWriteEn,
|
||||
.FSMLineWriteEn, .SelEvict, .SelFlush,
|
||||
.CacheMiss, .CacheAccess, .SelAdr,
|
||||
.ClearValid, .ClearDirty, .SetDirty,
|
||||
.SetValid, .SelEvict, .SelFlush,
|
||||
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
|
||||
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
|
||||
.save, .restore,
|
||||
|
||||
265
pipelined/src/cache/cachefsm.sv
vendored
265
pipelined/src/cache/cachefsm.sv
vendored
@ -32,78 +32,74 @@
|
||||
|
||||
module cachefsm
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic reset,
|
||||
// inputs from IEU
|
||||
input logic [1:0] RW,
|
||||
input logic [1:0] Atomic,
|
||||
input logic FlushCache,
|
||||
input logic [1:0] RW,
|
||||
input logic [1:0] Atomic,
|
||||
input logic FlushCache,
|
||||
// hazard inputs
|
||||
input logic CPUBusy,
|
||||
input logic CPUBusy,
|
||||
// interlock fsm
|
||||
input logic IgnoreRequestTLB,
|
||||
input logic IgnoreRequestTrapM,
|
||||
input logic IgnoreRequestTLB,
|
||||
input logic IgnoreRequestTrapM,
|
||||
// Bus inputs
|
||||
input logic CacheBusAck,
|
||||
input logic CacheBusAck,
|
||||
// dcache internals
|
||||
input logic CacheHit,
|
||||
input logic VictimDirty,
|
||||
input logic FlushAdrFlag,
|
||||
input logic FlushWayFlag,
|
||||
input logic CacheHit,
|
||||
input logic VictimDirty,
|
||||
input logic FlushAdrFlag,
|
||||
input logic FlushWayFlag,
|
||||
|
||||
// hazard outputs
|
||||
output logic CacheStall,
|
||||
output logic CacheStall,
|
||||
// counter outputs
|
||||
output logic CacheMiss,
|
||||
output logic CacheAccess,
|
||||
output logic CacheMiss,
|
||||
output logic CacheAccess,
|
||||
// Bus outputs
|
||||
output logic CacheCommitted,
|
||||
output logic CacheWriteLine,
|
||||
output logic CacheFetchLine,
|
||||
output logic CacheCommitted,
|
||||
output logic CacheWriteLine,
|
||||
output logic CacheFetchLine,
|
||||
|
||||
// dcache internals
|
||||
output logic [1:0] SelAdr,
|
||||
output logic SetValid,
|
||||
output logic ClearValid,
|
||||
output logic SetDirty,
|
||||
output logic ClearDirty,
|
||||
output logic FSMWordWriteEn,
|
||||
output logic FSMLineWriteEn,
|
||||
output logic SelEvict,
|
||||
output logic LRUWriteEn,
|
||||
output logic SelFlush,
|
||||
output logic FlushAdrCntEn,
|
||||
output logic FlushWayCntEn,
|
||||
output logic FlushAdrCntRst,
|
||||
output logic FlushWayCntRst,
|
||||
output logic save,
|
||||
output logic restore);
|
||||
output logic SelAdr,
|
||||
output logic ClearValid,
|
||||
output logic ClearDirty,
|
||||
output logic SetDirty,
|
||||
output logic SetValid,
|
||||
output logic SelEvict,
|
||||
output logic LRUWriteEn,
|
||||
output logic SelFlush,
|
||||
output logic FlushAdrCntEn,
|
||||
output logic FlushWayCntEn,
|
||||
output logic FlushAdrCntRst,
|
||||
output logic FlushWayCntRst,
|
||||
output logic save,
|
||||
output logic restore);
|
||||
|
||||
logic [1:0] PreSelAdr;
|
||||
logic resetDelay;
|
||||
logic Read, Write, AMO;
|
||||
logic AMO;
|
||||
logic DoAMO, DoRead, DoWrite, DoFlush;
|
||||
logic DoAMOHit, DoReadHit, DoWriteHit;
|
||||
logic DoAMOMiss, DoReadMiss, DoWriteMiss;
|
||||
logic FlushFlag;
|
||||
logic DoAnyUpdateHit, DoAnyHit;
|
||||
logic DoAnyMiss;
|
||||
logic FlushFlag, FlushWayAndNotAdrFlag;
|
||||
|
||||
typedef enum logic [3:0] {STATE_READY,
|
||||
|
||||
STATE_MISS_FETCH_WDV,
|
||||
STATE_MISS_FETCH_DONE,
|
||||
STATE_MISS_EVICT_DIRTY,
|
||||
STATE_MISS_WRITE_CACHE_LINE,
|
||||
STATE_MISS_READ_WORD,
|
||||
STATE_MISS_READ_WORD_DELAY,
|
||||
STATE_MISS_WRITE_WORD,
|
||||
|
||||
STATE_CPU_BUSY,
|
||||
STATE_CPU_BUSY_FINISH_AMO,
|
||||
|
||||
STATE_FLUSH,
|
||||
STATE_FLUSH_CHECK,
|
||||
STATE_FLUSH_INCR,
|
||||
STATE_FLUSH_WRITE_BACK,
|
||||
STATE_FLUSH_CLEAR_DIRTY} statetype;
|
||||
typedef enum logic [3:0] {STATE_READY, // hit states
|
||||
// miss states
|
||||
STATE_MISS_FETCH_WDV,
|
||||
STATE_MISS_FETCH_DONE,
|
||||
STATE_MISS_EVICT_DIRTY,
|
||||
STATE_MISS_WRITE_CACHE_LINE,
|
||||
STATE_MISS_READ_WORD,
|
||||
STATE_MISS_READ_WORD_DELAY,
|
||||
STATE_MISS_WRITE_WORD,
|
||||
// cpu stalled replay/restore state
|
||||
STATE_CPU_BUSY,
|
||||
// flush cache
|
||||
STATE_FLUSH,
|
||||
STATE_FLUSH_CHECK,
|
||||
STATE_FLUSH_INCR,
|
||||
STATE_FLUSH_WRITE_BACK,
|
||||
STATE_FLUSH_CLEAR_DIRTY} statetype;
|
||||
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
logic IgnoreRequest;
|
||||
@ -112,21 +108,15 @@ module cachefsm
|
||||
// if the command is used in the READY state then the cache needs to be able to supress
|
||||
// using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB.
|
||||
|
||||
// need to re organize all of these. Low priority though.
|
||||
assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation.
|
||||
assign AMO = Atomic[1] & (&RW);
|
||||
assign DoAMO = AMO & ~IgnoreRequest;
|
||||
assign DoAMOHit = DoAMO & CacheHit;
|
||||
assign DoAMOMiss = DoAMO & ~CacheHit;
|
||||
assign Read = RW[1];
|
||||
assign DoRead = Read & ~IgnoreRequest;
|
||||
assign DoReadHit = DoRead & CacheHit;
|
||||
assign DoReadMiss = DoRead & ~CacheHit;
|
||||
assign Write = RW[0];
|
||||
assign DoWrite = Write & ~IgnoreRequest;
|
||||
assign DoWriteHit = DoWrite & CacheHit;
|
||||
assign DoWriteMiss = DoWrite & ~CacheHit;
|
||||
assign DoRead = RW[1] & ~IgnoreRequest;
|
||||
assign DoWrite = RW[0] & ~IgnoreRequest;
|
||||
|
||||
assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit;
|
||||
assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit;
|
||||
assign DoAnyHit = DoAnyUpdateHit | (DoRead & CacheHit);
|
||||
assign FlushFlag = FlushAdrFlag & FlushWayFlag;
|
||||
|
||||
// outputs for the performance counters.
|
||||
@ -137,7 +127,6 @@ module cachefsm
|
||||
// PCNextF will no longer be pointing to the correct address.
|
||||
// But PCF will be the reset vector.
|
||||
flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
|
||||
assign SelAdr = resetDelay ? 2'b01 : PreSelAdr;
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) CurrState <= #1 STATE_READY;
|
||||
@ -146,54 +135,49 @@ module cachefsm
|
||||
always_comb begin
|
||||
NextState = STATE_READY;
|
||||
case (CurrState)
|
||||
STATE_READY: if(IgnoreRequest) NextState = STATE_READY;
|
||||
else if(DoFlush) NextState = STATE_FLUSH;
|
||||
else if(DoAMOHit & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; // change
|
||||
else if(DoReadHit & CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else if(DoWriteHit & CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else if(DoReadMiss | DoWriteMiss | DoAMOMiss) NextState = STATE_MISS_FETCH_WDV; // change
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE;
|
||||
else NextState = STATE_MISS_FETCH_WDV;
|
||||
STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
|
||||
else NextState = STATE_MISS_WRITE_CACHE_LINE;
|
||||
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD;
|
||||
STATE_MISS_READ_WORD: if (Write & ~AMO) NextState = STATE_MISS_WRITE_WORD;
|
||||
else NextState = STATE_MISS_READ_WORD_DELAY;
|
||||
STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||
else if(CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
|
||||
else NextState = STATE_MISS_EVICT_DIRTY;
|
||||
STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_CPU_BUSY_FINISH_AMO: if(CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||
else NextState = STATE_READY;
|
||||
STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
|
||||
STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK;
|
||||
else if (FlushFlag) NextState = STATE_READY;
|
||||
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
|
||||
else NextState = STATE_FLUSH_CHECK;
|
||||
STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK;
|
||||
STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY;
|
||||
else NextState = STATE_FLUSH_WRITE_BACK;
|
||||
STATE_FLUSH_CLEAR_DIRTY: if(FlushAdrFlag & FlushWayFlag) NextState = STATE_READY;
|
||||
else if (FlushWayFlag) NextState = STATE_FLUSH_INCR;
|
||||
else NextState = STATE_FLUSH_CHECK;
|
||||
default: NextState = STATE_READY;
|
||||
STATE_READY: if(IgnoreRequest) NextState = STATE_READY;
|
||||
else if(DoFlush) NextState = STATE_FLUSH;
|
||||
else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_FETCH_DONE;
|
||||
else NextState = STATE_MISS_FETCH_WDV;
|
||||
STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
|
||||
else NextState = STATE_MISS_WRITE_CACHE_LINE;
|
||||
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD;
|
||||
STATE_MISS_READ_WORD: if(RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD;
|
||||
else NextState = STATE_MISS_READ_WORD_DELAY;
|
||||
STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
|
||||
else NextState = STATE_MISS_EVICT_DIRTY;
|
||||
STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
|
||||
STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK;
|
||||
else if(FlushFlag) NextState = STATE_READY;
|
||||
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
|
||||
else NextState = STATE_FLUSH_CHECK;
|
||||
STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK;
|
||||
STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY;
|
||||
else NextState = STATE_FLUSH_WRITE_BACK;
|
||||
STATE_FLUSH_CLEAR_DIRTY: if(FlushFlag) NextState = STATE_READY;
|
||||
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
|
||||
else NextState = STATE_FLUSH_CHECK;
|
||||
default: NextState = STATE_READY;
|
||||
endcase
|
||||
end
|
||||
|
||||
// com back to CPU
|
||||
assign CacheCommitted = CurrState != STATE_READY;
|
||||
assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) |
|
||||
assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAnyMiss)) |
|
||||
(CurrState == STATE_MISS_FETCH_WDV) |
|
||||
(CurrState == STATE_MISS_FETCH_DONE) |
|
||||
(CurrState == STATE_MISS_EVICT_DIRTY) |
|
||||
(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
|
||||
(CurrState == STATE_MISS_READ_WORD) |
|
||||
(CurrState == STATE_MISS_EVICT_DIRTY) |
|
||||
(CurrState == STATE_FLUSH) |
|
||||
(CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) |
|
||||
(CurrState == STATE_FLUSH_INCR) |
|
||||
@ -201,18 +185,13 @@ module cachefsm
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
|
||||
// write enables internal to cache
|
||||
assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
|
||||
assign ClearValid = '0;
|
||||
assign SetDirty = (CurrState == STATE_READY & DoAMO) |
|
||||
(CurrState == STATE_READY & DoWrite) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY & AMO) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD);
|
||||
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
|
||||
assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) |
|
||||
assign SetDirty = (CurrState == STATE_READY & DoAnyUpdateHit) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY & AMO) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD);
|
||||
assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE);
|
||||
assign LRUWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit)) |
|
||||
assign ClearValid = '0;
|
||||
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
|
||||
assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD);
|
||||
// Flush and eviction controls
|
||||
@ -220,42 +199,38 @@ module cachefsm
|
||||
assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
|
||||
(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) |
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
|
||||
assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayFlag & ~FlushAdrFlag) |
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayFlag & ~FlushAdrFlag);
|
||||
assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag;
|
||||
assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayAndNotAdrFlag) |
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayAndNotAdrFlag);
|
||||
assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) |
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~FlushFlag);
|
||||
assign FlushAdrCntRst = (CurrState == STATE_READY);
|
||||
assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
|
||||
// Bus interface controls
|
||||
assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss));
|
||||
assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss);
|
||||
assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) |
|
||||
(CurrState == STATE_FLUSH_CHECK & VictimDirty);
|
||||
// handle cpu stall.
|
||||
assign restore = ((CurrState == STATE_CPU_BUSY) | (CurrState == STATE_CPU_BUSY_FINISH_AMO)) & ~`REPLAY;
|
||||
assign save = ((CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit) & CPUBusy) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | Read) & CPUBusy) |
|
||||
assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY;
|
||||
assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | RW[1]) & CPUBusy) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
|
||||
|
||||
// **** can this be simplified?
|
||||
assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss.
|
||||
(CurrState == STATE_READY & (AMO & CacheHit)) |
|
||||
(CurrState == STATE_READY & (Read & CacheHit) & (CPUBusy & `REPLAY)) |
|
||||
(CurrState == STATE_READY & (Write & CacheHit)) |
|
||||
(CurrState == STATE_MISS_FETCH_WDV) |
|
||||
(CurrState == STATE_MISS_FETCH_DONE) |
|
||||
(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
|
||||
(CurrState == STATE_MISS_READ_WORD) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD) |
|
||||
(CurrState == STATE_MISS_EVICT_DIRTY) |
|
||||
(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |
|
||||
(CurrState == STATE_CPU_BUSY_FINISH_AMO)) ? 2'b01 :
|
||||
((CurrState == STATE_FLUSH) |
|
||||
(CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) |
|
||||
(CurrState == STATE_FLUSH_INCR) |
|
||||
(CurrState == STATE_FLUSH_WRITE_BACK) |
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag))) ? 2'b10 :
|
||||
2'b00;
|
||||
|
||||
assign SelAdr = (CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss.
|
||||
// use the raw requests as we don't want IgnoreRequestTrapM in the critical path
|
||||
(CurrState == STATE_READY & ((AMO | RW[0]) & CacheHit)) | // changes if store delay hazard removed
|
||||
(CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) |
|
||||
|
||||
(CurrState == STATE_MISS_FETCH_WDV) |
|
||||
(CurrState == STATE_MISS_FETCH_DONE) |
|
||||
(CurrState == STATE_MISS_EVICT_DIRTY) |
|
||||
(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
|
||||
(CurrState == STATE_MISS_READ_WORD) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD) |
|
||||
|
||||
(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |
|
||||
resetDelay;
|
||||
|
||||
endmodule // cachefsm
|
||||
|
||||
44
pipelined/src/cache/cachereplacementpolicy.sv
vendored
44
pipelined/src/cache/cachereplacementpolicy.sv
vendored
@ -32,7 +32,7 @@
|
||||
module cachereplacementpolicy
|
||||
#(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)(
|
||||
input logic clk, reset,
|
||||
input logic [NUMWAYS-1:0] WayHit,
|
||||
input logic [NUMWAYS-1:0] HitWay,
|
||||
output logic [NUMWAYS-1:0] VictimWay,
|
||||
input logic [`PA_BITS-1:0] PAdr,
|
||||
input logic [SETLEN-1:0] RAdr,
|
||||
@ -67,7 +67,7 @@ module cachereplacementpolicy
|
||||
genvar index;
|
||||
if(NUMWAYS == 2) begin : PseudoLRU
|
||||
assign LRUEn[0] = 1'b0;
|
||||
assign NewReplacement[0] = WayHit[1];
|
||||
assign NewReplacement[0] = HitWay[1];
|
||||
assign VictimWay[1] = ~LineReplacementBits[0];
|
||||
assign VictimWay[0] = LineReplacementBits[0];
|
||||
end else if (NUMWAYS == 4) begin : PseudoLRU
|
||||
@ -84,15 +84,15 @@ module cachereplacementpolicy
|
||||
assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1];
|
||||
assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1];
|
||||
|
||||
// New LRU bits which are updated is function only of the WayHit.
|
||||
// New LRU bits which are updated is function only of the HitWay.
|
||||
// However the not updated bits come from the old LRU.
|
||||
assign LRUEn[2] = |WayHit;
|
||||
assign LRUEn[1] = WayHit[3] | WayHit[2];
|
||||
assign LRUEn[0] = WayHit[1] | WayHit[0];
|
||||
assign LRUEn[2] = |HitWay;
|
||||
assign LRUEn[1] = HitWay[3] | HitWay[2];
|
||||
assign LRUEn[0] = HitWay[1] | HitWay[0];
|
||||
|
||||
assign LRUMask[2] = WayHit[1] | WayHit[0];
|
||||
assign LRUMask[1] = WayHit[2];
|
||||
assign LRUMask[0] = WayHit[0];
|
||||
assign LRUMask[2] = HitWay[1] | HitWay[0];
|
||||
assign LRUMask[1] = HitWay[2];
|
||||
assign LRUMask[0] = HitWay[0];
|
||||
|
||||
mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, LRUMask, LRUEn, NewReplacement);
|
||||
end
|
||||
@ -101,21 +101,21 @@ module cachereplacementpolicy
|
||||
|
||||
// selects
|
||||
assign LRUEn[6] = 1'b1;
|
||||
assign LRUEn[5] = WayHit[7] | WayHit[6] | WayHit[5] | WayHit[4];
|
||||
assign LRUEn[4] = WayHit[7] | WayHit[6];
|
||||
assign LRUEn[3] = WayHit[5] | WayHit[4];
|
||||
assign LRUEn[2] = WayHit[3] | WayHit[2] | WayHit[1] | WayHit[0];
|
||||
assign LRUEn[1] = WayHit[3] | WayHit[2];
|
||||
assign LRUEn[0] = WayHit[1] | WayHit[0];
|
||||
assign LRUEn[5] = HitWay[7] | HitWay[6] | HitWay[5] | HitWay[4];
|
||||
assign LRUEn[4] = HitWay[7] | HitWay[6];
|
||||
assign LRUEn[3] = HitWay[5] | HitWay[4];
|
||||
assign LRUEn[2] = HitWay[3] | HitWay[2] | HitWay[1] | HitWay[0];
|
||||
assign LRUEn[1] = HitWay[3] | HitWay[2];
|
||||
assign LRUEn[0] = HitWay[1] | HitWay[0];
|
||||
|
||||
// mask
|
||||
assign LRUMask[6] = WayHit[7] | WayHit[6] | WayHit[5] | WayHit[4];
|
||||
assign LRUMask[5] = WayHit[7] | WayHit[6];
|
||||
assign LRUMask[4] = WayHit[7];
|
||||
assign LRUMask[3] = WayHit[5];
|
||||
assign LRUMask[2] = WayHit[3] | WayHit[2];
|
||||
assign LRUMask[1] = WayHit[2];
|
||||
assign LRUMask[0] = WayHit[0];
|
||||
assign LRUMask[6] = HitWay[7] | HitWay[6] | HitWay[5] | HitWay[4];
|
||||
assign LRUMask[5] = HitWay[7] | HitWay[6];
|
||||
assign LRUMask[4] = HitWay[7];
|
||||
assign LRUMask[3] = HitWay[5];
|
||||
assign LRUMask[2] = HitWay[3] | HitWay[2];
|
||||
assign LRUMask[1] = HitWay[2];
|
||||
assign LRUMask[0] = HitWay[0];
|
||||
|
||||
for(index = 0; index < NUMWAYS-1; index++)
|
||||
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
|
||||
|
||||
54
pipelined/src/cache/cacheway.sv
vendored
54
pipelined/src/cache/cacheway.sv
vendored
@ -37,21 +37,20 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
|
||||
input logic [$clog2(NUMLINES)-1:0] RAdr,
|
||||
input logic [`PA_BITS-1:0] PAdr,
|
||||
input logic WriteWordWayEn,
|
||||
input logic WriteLineWayEn,
|
||||
input logic [LINELEN-1:0] CacheWriteData,
|
||||
input logic SetValidWay,
|
||||
input logic ClearValidWay,
|
||||
input logic SetDirtyWay,
|
||||
input logic ClearDirtyWay,
|
||||
input logic SelEvict,
|
||||
input logic VictimWay,
|
||||
input logic InvalidateAll,
|
||||
input logic SelFlush,
|
||||
input logic VictimWay,
|
||||
input logic FlushWay,
|
||||
input logic Invalidate,
|
||||
|
||||
|
||||
output logic [LINELEN-1:0] ReadDataLineWay,
|
||||
output logic WayHit,
|
||||
output logic HitWay,
|
||||
output logic VictimDirtyWay,
|
||||
output logic [TAGLEN-1:0] VictimTagWay);
|
||||
|
||||
@ -59,28 +58,25 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
localparam LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam LOGXLENBYTES = $clog2(`XLEN/8);
|
||||
|
||||
logic [NUMLINES-1:0] ValidBits;
|
||||
logic [NUMLINES-1:0] DirtyBits;
|
||||
logic [LINELEN-1:0] ReadDataLine;
|
||||
logic [TAGLEN-1:0] ReadTag;
|
||||
logic Valid;
|
||||
logic Dirty;
|
||||
logic SelData;
|
||||
logic SelTag;
|
||||
|
||||
logic [$clog2(NUMLINES)-1:0] RAdrD;
|
||||
|
||||
logic [2**LOGWPL-1:0] MemPAdrDecoded;
|
||||
logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn;
|
||||
logic [NUMLINES-1:0] ValidBits;
|
||||
logic [NUMLINES-1:0] DirtyBits;
|
||||
logic [LINELEN-1:0] ReadDataLine;
|
||||
logic [TAGLEN-1:0] ReadTag;
|
||||
logic Valid;
|
||||
logic Dirty;
|
||||
logic SelData;
|
||||
logic SelTag;
|
||||
logic [$clog2(NUMLINES)-1:0] RAdrD;
|
||||
logic [2**LOGWPL-1:0] MemPAdrDecoded;
|
||||
logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Write Enable demux
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
onehotdecoder #(LOGWPL) adrdec(
|
||||
.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
|
||||
// If writing the whole line set all write enables to 1, else only set the correct word.
|
||||
assign SelectedWriteWordEn = WriteLineWayEn ? '1 : WriteWordWayEn ? MemPAdrDecoded : '0; // OR-AND
|
||||
assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Tag Array
|
||||
@ -88,12 +84,13 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
|
||||
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk,
|
||||
.Adr(RAdr), .ReadData(ReadTag),
|
||||
.CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineWayEn));
|
||||
.CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay));
|
||||
|
||||
// AND portion of distributed tag multiplexer
|
||||
assign SelTag = SelFlush ? FlushWay : VictimWay;
|
||||
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
|
||||
assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux
|
||||
assign VictimDirtyWay = SelTag & Dirty & Valid;
|
||||
assign HitWay = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Data Array
|
||||
@ -109,8 +106,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
end
|
||||
|
||||
// AND portion of distributed read multiplexers
|
||||
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
|
||||
mux3 #(1) selecteddatamux(WayHit, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);
|
||||
mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);
|
||||
assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux.
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
@ -118,9 +114,9 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
always_ff @(posedge clk) begin // Valid bit array,
|
||||
if (reset | InvalidateAll) ValidBits <= #1 '0;
|
||||
else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1;
|
||||
else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0;
|
||||
if (reset | Invalidate) ValidBits <= #1 '0;
|
||||
else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1;
|
||||
else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0;
|
||||
end
|
||||
flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
|
||||
assign Valid = ValidBits[RAdrD];
|
||||
@ -132,8 +128,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
// Dirty bits
|
||||
if (DIRTY_BITS) begin:dirty
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
|
||||
else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1;
|
||||
if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
|
||||
else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1;
|
||||
else if (ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0;
|
||||
end
|
||||
assign Dirty = DirtyBits[RAdrD];
|
||||
|
||||
@ -185,7 +185,7 @@ module ifu (
|
||||
localparam integer LINELEN = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS : `XLEN;
|
||||
localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
|
||||
logic [LINELEN-1:0] ReadDataLine;
|
||||
logic [LINELEN-1:0] ICacheMemWriteData;
|
||||
logic [LINELEN-1:0] ICacheBusWriteData;
|
||||
logic [`PA_BITS-1:0] ICacheBusAdr;
|
||||
logic ICacheBusAck;
|
||||
logic save,restore;
|
||||
@ -199,7 +199,7 @@ module ifu (
|
||||
.WordCount(), .LSUBusHWDATA(),
|
||||
.DCacheFetchLine(ICacheFetchLine),
|
||||
.DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck),
|
||||
.DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF),
|
||||
.DCacheBusWriteData(ICacheBusWriteData), .LSUPAdrM(PCPF),
|
||||
.FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF[31:0]),
|
||||
.IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
|
||||
.BusStall, .BusCommittedM());
|
||||
@ -212,7 +212,7 @@ module ifu (
|
||||
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
|
||||
.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0))
|
||||
icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0),
|
||||
.CacheMemWriteData(ICacheMemWriteData), .CacheBusAck(ICacheBusAck),
|
||||
.CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck),
|
||||
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
|
||||
.CacheFetchLine(ICacheFetchLine),
|
||||
.CacheWriteLine(), .ReadDataLine(ReadDataLine),
|
||||
|
||||
@ -52,7 +52,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
|
||||
input logic DCacheFetchLine,
|
||||
input logic DCacheWriteLine,
|
||||
output logic DCacheBusAck,
|
||||
output logic [LINELEN-1:0] DCacheMemWriteData,
|
||||
output logic [LINELEN-1:0] DCacheBusWriteData,
|
||||
|
||||
// lsu interface
|
||||
input logic [`PA_BITS-1:0] LSUPAdrM,
|
||||
@ -77,7 +77,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
|
||||
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
||||
flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)),
|
||||
.d(LSUBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
.d(LSUBusHRDATA), .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
end
|
||||
|
||||
|
||||
@ -88,7 +88,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
|
||||
else assign LSUBusHWDATA = '0;
|
||||
mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M),
|
||||
.s(SelUncachedAdr), .y(LSUBusSize));
|
||||
mux2 #(WORDLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheMemWriteData[WORDLEN-1:0]),
|
||||
mux2 #(WORDLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheBusWriteData[WORDLEN-1:0]),
|
||||
.s(SelUncachedAdr), .y(ReadDataWordMuxM));
|
||||
|
||||
busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup Icache? must fix.
|
||||
|
||||
@ -185,7 +185,7 @@ module lsu (
|
||||
localparam integer LINELEN = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS : `XLEN;
|
||||
localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
|
||||
logic [LINELEN-1:0] ReadDataLineM;
|
||||
logic [LINELEN-1:0] DCacheMemWriteData;
|
||||
logic [LINELEN-1:0] DCacheBusWriteData;
|
||||
logic [`PA_BITS-1:0] DCacheBusAdr;
|
||||
logic DCacheWriteLine;
|
||||
logic DCacheFetchLine;
|
||||
@ -200,7 +200,7 @@ module lsu (
|
||||
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
|
||||
.WordCount, .LSUBusWriteCrit,
|
||||
.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
|
||||
.DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM,
|
||||
.DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .FinalAMOWriteDataM,
|
||||
.ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
|
||||
.BusStall, .BusCommittedM);
|
||||
|
||||
@ -218,7 +218,7 @@ module lsu (
|
||||
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
|
||||
.IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM),
|
||||
.CacheBusAdr(DCacheBusAdr), .ReadDataLine(ReadDataLineM),
|
||||
.CacheMemWriteData(DCacheMemWriteData), .CacheFetchLine(DCacheFetchLine),
|
||||
.CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine),
|
||||
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
|
||||
|
||||
subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread(
|
||||
|
||||
Loading…
Reference in New Issue
Block a user