forked from Github_Repos/cvw
Fixed subtle and infrequenct bug.
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
This commit is contained in:
Ross Thompson
parent
689c32215f
commit
6d12010d02
@ -37,11 +37,11 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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@ -50,21 +50,21 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/ExpectedPCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/MepcExpected
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -expand -group {Execution Stage} /testbench/textE
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add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/textM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
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add wave -noupdate -group {Execution Stage} /testbench/MepcExpected
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -group {Execution Stage} /testbench/textE
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add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -group {Memory Stage} /testbench/checkInstrM
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add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -group {Memory Stage} /testbench/textM
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add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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@ -119,12 +119,21 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/if
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/core/PCF
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add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/core/PCE
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add wave -noupdate -group PCS /testbench/dut/core/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
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add wave -noupdate -expand -label {Contributors: GHRMuxSel} -group {Contributors: sim:/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
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add wave -noupdate -expand -label {Contributors: GHRMuxSel} -group {Contributors: sim:/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
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add wave -noupdate -expand -label {Contributors: GHRMuxSel} -group {Contributors: sim:/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
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add wave -noupdate -expand -label {Contributors: GHRMuxSel} -group {Contributors: sim:/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
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add wave -noupdate -expand -label {Contributors: GHRMuxSel} -group {Contributors: sim:/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
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add wave -noupdate -expand -label {Contributors: GHRMuxSel} -group {Contributors: sim:/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassD
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add wave -noupdate -expand -label {Contributors: GHRMuxSel} -group {Contributors: sim:/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassF
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add wave -noupdate -expand -label {Contributors: GHRMuxSel} -group {Contributors: sim:/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/core/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
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@ -165,29 +174,33 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/Write
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAck
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusHRDATA
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
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add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
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add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/WayHit
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add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
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add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
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add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
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add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
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add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheMemWriteData
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add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
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add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
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add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
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add wave -noupdate -expand -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusRead
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAdr
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAck
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusHRDATA
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add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/busdp/busfsm/BusStall
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add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/busdp/busfsm/IgnoreRequest
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add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/busdp/busfsm/LSURWM
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add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
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add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
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add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
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add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
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add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
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add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
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add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
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add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
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add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/WayHit
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add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
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add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
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add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
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add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
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add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheMemWriteData
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add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
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add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
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add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
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add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
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add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall
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@ -494,8 +507,18 @@ add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I
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add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
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add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
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add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrD
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add wave -noupdate /testbench/dut/core/ifu/InstrRawD
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add wave -noupdate /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
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add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillSaveF
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add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
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add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/TakeSpillF
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add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
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add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/IFUCacheBusStallF
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 7} {86251 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1}
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WaveRestoreCursors {{Cursor 7} {35 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 314
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@ -511,4 +534,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {0 ns} {105085 ns}
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WaveRestoreZoom {0 ns} {452 ns}
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@ -125,8 +125,8 @@ module ifu (
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if(`C_SUPPORTED) begin : SpillSupport
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spillsupport spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF,
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.IFUCacheBusStallF, .PCNextFSpill, .PCFSpill, .SelNextSpillF,
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.PostSpillInstrRawF, .CompressedF);
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.IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill,
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.SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
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end else begin : NoSpillSupport
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assign PCNextFSpill = PCNextF;
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assign PCFSpill = PCF;
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@ -41,6 +41,7 @@ module spillsupport (
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input logic [`XLEN-1:0] PCNextF,
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input logic [31:0] InstrRawF,
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input logic IFUCacheBusStallF,
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input logic ITLBMissF,
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output logic [`XLEN-1:0] PCNextFSpill,
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output logic [`XLEN-1:0] PCFSpill,
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output logic SelNextSpillF,
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@ -71,15 +72,15 @@ module spillsupport (
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if (reset) CurrState <= #1 STATE_SPILL_READY;
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else CurrState <= #1 NextState;
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assign TakeSpillF = SpillF & ~IFUCacheBusStallF;
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assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~ITLBMissF;
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always_comb begin
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case (CurrState)
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STATE_SPILL_READY: if (TakeSpillF) NextState = STATE_SPILL_SPILL;
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else NextState = STATE_SPILL_READY;
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STATE_SPILL_READY: if (TakeSpillF) NextState = STATE_SPILL_SPILL;
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else NextState = STATE_SPILL_READY;
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STATE_SPILL_SPILL: if(IFUCacheBusStallF | StallF) NextState = STATE_SPILL_SPILL;
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else NextState = STATE_SPILL_READY;
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default: NextState = STATE_SPILL_READY;
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else NextState = STATE_SPILL_READY;
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default: NextState = STATE_SPILL_READY;
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endcase
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end
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@ -76,7 +76,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
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genvar index;
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for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
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flopenr #(`XLEN) fb(.clk, .reset, .en(LSUBusAck & LSUBusRead & (index == WordCount)),
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flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)),
|
||||
.d(LSUBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
end
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user