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Got separate module for the sub cache line read.

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This commit is contained in:
Ross Thompson 2022-02-04 16:18:01 -06:00
parent cdd599e340
commit 725852362e
3 changed files with 86 additions and 22 deletions
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26
pipelined/src/cache/cache.sv vendored
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@ -157,27 +157,23 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
// easily build a variable input mux.
// *** move this to LSU and IFU, also remove mux from busdp into LSU.
// *** give this a module name to match block diagram
logic [`XLEN-1:0] ReadDataWordRaw, ReadDataWordSaved;
genvar index;
if(DCACHE == 1) begin: readdata
subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread(
.clk, .reset, .PAdr, .save, .restore,
.ReadDataLine, .ReadDataWord);
// *** only here temporary
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
assign ReadDataLineSets[index] = ReadDataLine[((index+1)*`XLEN)-1: (index*`XLEN)];
end
// variable input mux
assign ReadDataWordRaw = ReadDataLineSets[PAdr[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
end else begin: readdata
logic [31:0] ReadLineSetsF [LINELEN/16-1:0];
logic [31:0] FinalInstrRawF;
for(index = 0; index < LINELEN / 16 - 1; index++)
assign ReadLineSetsF[index] = ReadDataLine[((index+1)*16)+16-1 : (index*16)];
assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadDataLine[LINELEN-1:LINELEN-16]};
assign FinalInstrRawF = ReadLineSetsF[PAdr[$clog2(LINELEN / 32) + 1 : 1]];
if (`XLEN == 64) assign ReadDataWordRaw = {32'b0, FinalInstrRawF};
else assign ReadDataWordRaw = FinalInstrRawF;
end else begin: readdata
logic [31:0] FinalInstrRawF;
subcachelineread #(LINELEN, 32, 16) subcachelineread(
.clk, .reset, .PAdr, .save, .restore,
.ReadDataLine, .ReadDataWord(FinalInstrRawF));
if (`XLEN == 64) assign ReadDataWord = {32'b0, FinalInstrRawF};
else assign ReadDataWord = FinalInstrRawF;
end
flopen #(`XLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved);
mux2 #(`XLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved,
restore, ReadDataWord);
/////////////////////////////////////////////////////////////////////////////////////////////
// Write Path: Write Enables

14
pipelined/src/cache/cachefsm.sv vendored
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@ -181,7 +181,7 @@ module cachefsm
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
//PreSelAdr = 2'b01;
//PreSelAdr = 2'b01; `REPLAY
save = 1'b1;
end
else begin
@ -198,7 +198,7 @@ module cachefsm
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
//PreSelAdr = 2'b01;
//PreSelAdr = 2'b01; `REPLAY
save = 1'b1;
end
else begin
@ -215,7 +215,7 @@ module cachefsm
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
//PreSelAdr = 2'b01;
//PreSelAdr = 2'b01; `REPLAY
save = 1'b1;
end
else begin
@ -276,7 +276,7 @@ module cachefsm
end
STATE_MISS_READ_WORD_DELAY: begin
//PreSelAdr = 2'b01;
//PreSelAdr = 2'b01; `REPLAY
SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
@ -296,7 +296,7 @@ module cachefsm
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
//PreSelAdr = 2'b01;
//PreSelAdr = 2'b01; `REPLAY
save = 1'b1;
end
else begin
@ -312,7 +312,7 @@ module cachefsm
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
//PreSelAdr = 2'b01;
//PreSelAdr = 2'b01; `REPLAY
save = 1'b1;
end
else begin
@ -337,7 +337,7 @@ module cachefsm
restore = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
//PreSelAdr = 2'b01;
//PreSelAdr = 2'b01; `REPLAY
end
else begin
NextState = STATE_READY;

68
pipelined/src/cache/subcachelineread.sv vendored Normal file
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@ -0,0 +1,68 @@
///////////////////////////////////////////
// subcachelineread
//
// Written: Ross Thompson ross1728@gmail.com February 04, 2022
// Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes.
//
// Purpose: Controller for the dcache fsm
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// MIT LICENSE
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
// to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)(
input logic clk,
input logic reset,
input logic [`PA_BITS-1:0] PAdr,
input logic save, restore,
input logic [LINELEN-1:0] ReadDataLine,
output logic [WORDLEN-1:0] ReadDataWord);
localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
localparam PADLEN = WORDLEN-MUXINTERVAL;
// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
// easily build a variable input mux.
// *** move this to LSU and IFU, also remove mux from busdp into LSU.
// *** give this a module name to match block diagram
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved;
if (PADLEN > 0) begin
logic [PADLEN-1:0] Pad;
assign Pad = '0;
assign ReadDataLinePad = {Pad, ReadDataLine};
end else assign ReadDataLinePad = ReadDataLine;
genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)];
end
// variable input mux
assign ReadDataWordRaw = ReadDataLineSets[PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]];
flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved);
mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved,
restore, ReadDataWord);
endmodule