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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-02-08 14:47:15 -06:00
commit 038897f448
207 changed files with 5593 additions and 12075 deletions
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5
.gitignore vendored
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@ -52,4 +52,7 @@ examples/asm/sumtest/sumtest
examples/asm/example/example
examples/C/sum/sum
examples/C/fir/fir
synthDC/hdl/*.sv
linux/devicetree/debug/*
!linux/devicetree/debug/dumpdts.sh
*.dtb

3
.gitmodules vendored
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@ -20,3 +20,6 @@
[submodule "addins/sky130_osu_sc_t18"]
path = addins/sky130_osu_sc_t18
url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t18
[submodule "addins/sky130_osu_sc_t12"]
path = addins/sky130_osu_sc_t12
url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12

1
addins/sky130_osu_sc_t12 Submodule

@ -0,0 +1 @@
Subproject commit f1eef844734f73d3c79d83b82352118263eb7686

4
benchmarks/riscv-coremark/Makefile
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@ -6,8 +6,10 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
work/coremark.bare.riscv.memfile: work/coremark.bare.riscv
work/coremark.bare.riscv.elf.memfile: work/coremark.bare.riscv
riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@
extractFunctionRadix.sh $<.elf.objdump
work/coremark.bare.riscv.objdump: work/coremark.bare.riscv
riscv64-unknown-elf-objdump -D work/coremark.bare.riscv > work/coremark.bare.riscv.objdump

BIN
examples/C/fir/fir
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58
examples/verilog/xz/distributedmux.sv Normal file
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@ -0,0 +1,58 @@
// xz.sv
// David_Harris@hmc.edu 30 January 2022
// Demonstrate impact of x and z.
// load with vsim xz.sv
module testbench();
logic [3:0] d0, d1, d2;
logic s0, s1, s2;
tri [3:0] y;
distributedmux dut(.d0, .d1, .d2, .s0, .s1, .s2, .y);
initial begin
d0 = 4'b0000; d1 = 4'b0101; // d2 unknown (xxxx)
s0 = 0; s1 = 0; s2 = 0;
#10; // y should be floating
s0 = 1;
#10; //y should be driven to 0000
s0 = 0; s1 = 1;
#10; // y should be driven to 0101
s0 = 1;
#10; // y should be driven to 0x0x because of contention on bits 0 and 2
s0 = 0; s1 = 0; s2 = 1;
#10; // y should be driven to unknown because d2 is unknown
end
endmodule
module tristate #(parameter WIDTH=32) (
input logic [WIDTH-1:0] a,
input logic en,
output logic [WIDTH-1:0] y);
assign y = en ? a : 'z;
endmodule
module distributedmux(
input logic [3:0] d0, d1, d2,
input logic s0, s1, s2,
output tri [3:0] y);
tristate #(4) t0(d0, s0, y);
tristate #(4) t1(d1, s1, y);
tristate #(4) t2(d2, s2, y);
endmodule
module gpio #(parameter WIDTH=16) (
input logic [WIDTH-1:0] GPIOOutVal, GPIOEn,
output logic [WIDTH-1:0] GPIOInVal,
inout tri [WIDTH-1:0] GPIOPin);
assign GPIOInVal = GPIOPin;
tristate #(1) ts[WIDTH-1:0](GPIOOutVal, GPIOEn, GPIOPin);
endmodule
module silly(output logic [128:0] y);
assign y = 'bz;
endmodule

19
examples/verilog/xz/xz.sv Normal file
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@ -0,0 +1,19 @@
// xz.sv
// David_Harris@hmc.edu 30 January 2022
// Demonstrate impact of x and z.
// load with vsim xz.sv
module xz(
output logic w, x, y, z);
logic p, q, r;
// let p be undriven
assign q = 1'bz;
assign r = 1'bx;
assign w = q & 1'b1;
assign x = q | 1'b1;
endmodule

645
linux/add_wally_to_QEMU.patch
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@ -1,645 +0,0 @@
From 61696744ed1197c9435b85a4ac5610090faa3179 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Wed, 26 Jan 2022 14:43:11 +0000
Subject: [PATCH] add Wally model to QEMU
---
configs/devices/riscv64-softmmu/default.mak | 1 +
hw/riscv/Kconfig | 7 +
hw/riscv/meson.build | 1 +
hw/riscv/wally.c | 501 ++++++++++++++++++++
include/hw/riscv/wally.h | 79 +++
5 files changed, 589 insertions(+)
create mode 100644 hw/riscv/wally.c
create mode 100644 include/hw/riscv/wally.h
diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/riscv64-softmmu/default.mak
index bc69301fa4..396ebb82a1 100644
--- a/configs/devices/riscv64-softmmu/default.mak
+++ b/configs/devices/riscv64-softmmu/default.mak
@@ -14,3 +14,4 @@ CONFIG_SIFIVE_U=y
CONFIG_RISCV_VIRT=y
CONFIG_MICROCHIP_PFSOC=y
CONFIG_SHAKTI_C=y
+CONFIG_WALLY=y
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index d2d869aaad..a7ed6ae06f 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -81,3 +81,10 @@ config SPIKE
select MSI_NONBROKEN
select RISCV_ACLINT
select SIFIVE_PLIC
+
+config WALLY
+ bool
+ select SERIAL
+ select RISCV_ACLINT
+ select SIFIVE_PLIC
+ select SIFIVE_TEST
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index ab6cae57ea..b468f2c87c 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -9,5 +9,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
+riscv_ss.add(when: 'CONFIG_WALLY', if_true: files('wally.c'))
hw_arch += {'riscv': riscv_ss}
diff --git a/hw/riscv/wally.c b/hw/riscv/wally.c
new file mode 100644
index 0000000000..25792dd04c
--- /dev/null
+++ b/hw/riscv/wally.c
@@ -0,0 +1,501 @@
+/*
+ * QEMU RISC-V Wally Board
+ * Modified from Virt Board
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ * *** What should we say for copyright?
+ *
+ * RISC-V machine with 16550a UART and VirtIO MMIO
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
+#include "hw/char/serial.h"
+#include "target/riscv/cpu.h"
+#include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/wally.h"
+#include "hw/riscv/boot.h"
+#include "hw/riscv/numa.h"
+#include "hw/intc/riscv_aclint.h"
+#include "hw/intc/sifive_plic.h"
+#include "hw/misc/sifive_test.h"
+#include "chardev/char.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/sysemu.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
+
+static const MemMapEntry wally_memmap[] = {
+ [WALLY_MROM] = { 0x1000, 0xf000 },
+ [WALLY_CLINT] = { 0x2000000, 0x10000 },
+ [WALLY_PLIC] = { 0xc000000, WALLY_PLIC_SIZE(WALLY_CPUS_MAX * 2) },
+ [WALLY_UART0] = { 0x10000000, 0x100 },
+ [WALLY_DRAM] = { 0x80000000, 0x0 },
+};
+
+static void create_fdt_socket_cpus(WallyState *s, int socket,
+ char *clust_name, uint32_t *phandle,
+ bool is_32_bit, uint32_t *intc_phandles)
+{
+ int cpu;
+ uint32_t cpu_phandle;
+ MachineState *mc = MACHINE(s);
+ char *name, *cpu_name, *core_name, *intc_name;
+
+ for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
+ cpu_phandle = (*phandle)++;
+
+ cpu_name = g_strdup_printf("/cpus/cpu@%d",
+ s->soc[socket].hartid_base + cpu);
+ qemu_fdt_add_subnode(mc->fdt, cpu_name);
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+ (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
+ name = riscv_isa_string(&s->soc[socket].harts[cpu]);
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
+ g_free(name);
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
+ qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
+ s->soc[socket].hartid_base + cpu);
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
+ riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
+ qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
+
+ intc_phandles[cpu] = (*phandle)++;
+
+ intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
+ qemu_fdt_add_subnode(mc->fdt, intc_name);
+ qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
+ intc_phandles[cpu]);
+ qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+ "riscv,cpu-intc");
+ qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
+
+ core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
+ qemu_fdt_add_subnode(mc->fdt, core_name);
+ qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
+
+ g_free(core_name);
+ g_free(intc_name);
+ g_free(cpu_name);
+ }
+}
+
+static void create_fdt_socket_memory(WallyState *s,
+ const MemMapEntry *memmap, int socket)
+{
+ char *mem_name;
+ uint64_t addr, size;
+ MachineState *mc = MACHINE(s);
+
+ addr = memmap[WALLY_DRAM].base + riscv_socket_mem_offset(mc, socket);
+ size = riscv_socket_mem_size(mc, socket);
+ mem_name = g_strdup_printf("/memory@%lx", (long)addr);
+ qemu_fdt_add_subnode(mc->fdt, mem_name);
+ qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
+ addr >> 32, addr, size >> 32, size);
+ qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
+ riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
+ g_free(mem_name);
+}
+
+static void create_fdt_socket_clint(WallyState *s,
+ const MemMapEntry *memmap, int socket,
+ uint32_t *intc_phandles)
+{
+ int cpu;
+ char *clint_name;
+ uint32_t *clint_cells;
+ unsigned long clint_addr;
+ MachineState *mc = MACHINE(s);
+ static const char * const clint_compat[2] = {
+ "sifive,clint0", "riscv,clint0"
+ };
+
+ clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
+ clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
+ clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
+ }
+
+ clint_addr = memmap[WALLY_CLINT].base + (memmap[WALLY_CLINT].size * socket);
+ clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
+ qemu_fdt_add_subnode(mc->fdt, clint_name);
+ qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
+ (char **)&clint_compat,
+ ARRAY_SIZE(clint_compat));
+ qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
+ 0x0, clint_addr, 0x0, memmap[WALLY_CLINT].size);
+ qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
+ clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+ riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
+ g_free(clint_name);
+
+ g_free(clint_cells);
+}
+
+
+static void create_fdt_socket_plic(WallyState *s,
+ const MemMapEntry *memmap, int socket,
+ uint32_t *phandle, uint32_t *intc_phandles,
+ uint32_t *plic_phandles)
+{
+ int cpu;
+ char *plic_name;
+ uint32_t *plic_cells;
+ unsigned long plic_addr;
+ MachineState *mc = MACHINE(s);
+ static const char * const plic_compat[2] = {
+ "sifive,plic-1.0.0", "riscv,plic0"
+ };
+
+ plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
+ plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
+ plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+ }
+
+ plic_phandles[socket] = (*phandle)++;
+ plic_addr = memmap[WALLY_PLIC].base + (memmap[WALLY_PLIC].size * socket);
+ plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
+ qemu_fdt_add_subnode(mc->fdt, plic_name);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ "#address-cells", FDT_PLIC_ADDR_CELLS);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ "#interrupt-cells", FDT_PLIC_INT_CELLS);
+ qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
+ (char **)&plic_compat,
+ ARRAY_SIZE(plic_compat));
+ qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
+ plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+ qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
+ 0x0, plic_addr, 0x0, memmap[WALLY_PLIC].size);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", WALLYIO_NDEV);
+ riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
+ plic_phandles[socket]);
+ g_free(plic_name);
+
+ g_free(plic_cells);
+}
+
+static void create_fdt_sockets(WallyState *s, const MemMapEntry *memmap,
+ bool is_32_bit, uint32_t *phandle)
+{
+ int socket;
+ char *clust_name;
+ uint32_t *intc_phandles;
+ MachineState *mc = MACHINE(s);
+ uint32_t xplic_phandles[MAX_NODES];
+
+ qemu_fdt_add_subnode(mc->fdt, "/cpus");
+ qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
+ qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
+ qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
+
+ for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
+ qemu_fdt_add_subnode(mc->fdt, clust_name);
+
+ intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts);
+
+ create_fdt_socket_cpus(s, socket, clust_name, phandle,
+ is_32_bit, intc_phandles);
+
+ create_fdt_socket_memory(s, memmap, socket);
+
+ create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+
+ create_fdt_socket_plic(s, memmap, socket, phandle,
+ intc_phandles, xplic_phandles);
+
+ g_free(intc_phandles);
+ g_free(clust_name);
+ }
+ riscv_socket_fdt_write_distance_matrix(mc, mc->fdt);
+}
+
+static void create_fdt_uart(WallyState *s, const MemMapEntry *memmap)
+{
+ char *name;
+ MachineState *mc = MACHINE(s);
+
+ name = g_strdup_printf("/soc/uart@%lx", (long)memmap[WALLY_UART0].base);
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ 0x0, memmap[WALLY_UART0].base,
+ 0x0, memmap[WALLY_UART0].size);
+ qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
+
+ qemu_fdt_add_subnode(mc->fdt, "/chosen");
+ qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
+ g_free(name);
+}
+
+static void create_fdt(WallyState *s, const MemMapEntry *memmap,
+ uint64_t mem_size, const char *cmdline, bool is_32_bit)
+{
+ MachineState *mc = MACHINE(s);
+ uint32_t phandle = 1;
+
+ if (mc->dtb) {
+ mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
+ if (!mc->fdt) {
+ error_report("load_device_tree() failed");
+ exit(1);
+ }
+ goto update_bootargs;
+ } else {
+ mc->fdt = create_device_tree(&s->fdt_size);
+ if (!mc->fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
+ }
+
+ qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-wally,qemu");
+ qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-wally");
+ qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
+
+ qemu_fdt_add_subnode(mc->fdt, "/soc");
+ qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
+ qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
+ qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
+
+ create_fdt_sockets(s, memmap, is_32_bit, &phandle);
+ create_fdt_uart(s, memmap);
+
+update_bootargs:
+ if (cmdline) {
+ qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
+ }
+}
+
+static void wally_machine_init(MachineState *machine)
+{
+ const MemMapEntry *memmap = wally_memmap;
+ WallyState *s = RISCV_WALLY_MACHINE(machine);
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+ char *plic_hart_config, *soc_name;
+ target_ulong start_addr = memmap[WALLY_DRAM].base;
+ target_ulong firmware_end_addr, kernel_start_addr;
+ uint32_t fdt_load_addr;
+ uint64_t kernel_entry;
+ DeviceState *mmio_plic, *wallyio_plic, *pcie_plic;
+ int i, base_hartid, hart_count;
+
+ /* Check socket count limit */
+ if (WALLY_SOCKETS_MAX < riscv_socket_count(machine)) {
+ error_report("number of sockets/nodes should be less than %d",
+ WALLY_SOCKETS_MAX);
+ exit(1);
+ }
+
+ /* Initialize sockets */
+ mmio_plic = wallyio_plic = pcie_plic = NULL;
+ for (i = 0; i < riscv_socket_count(machine); i++) {
+ if (!riscv_socket_check_hartids(machine, i)) {
+ error_report("discontinuous hartids in socket%d", i);
+ exit(1);
+ }
+
+ base_hartid = riscv_socket_first_hartid(machine, i);
+ if (base_hartid < 0) {
+ error_report("can't find hartid base for socket%d", i);
+ exit(1);
+ }
+
+ hart_count = riscv_socket_hart_count(machine, i);
+ if (hart_count < 0) {
+ error_report("can't find hart count for socket%d", i);
+ exit(1);
+ }
+
+ soc_name = g_strdup_printf("soc%d", i);
+ object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
+ TYPE_RISCV_HART_ARRAY);
+ g_free(soc_name);
+ object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
+ machine->cpu_type, &error_abort);
+ object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
+ base_hartid, &error_abort);
+ object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
+ hart_count, &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+
+ /* Per-socket CLINT */
+ riscv_aclint_swi_create(
+ memmap[WALLY_CLINT].base + i * memmap[WALLY_CLINT].size,
+ base_hartid, hart_count, false);
+ riscv_aclint_mtimer_create(
+ memmap[WALLY_CLINT].base + i * memmap[WALLY_CLINT].size +
+ RISCV_ACLINT_SWI_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
+
+ /* Per-socket PLIC hart topology configuration string */
+ plic_hart_config = riscv_plic_hart_config_string(hart_count);
+
+ /* Per-socket PLIC */
+ s->plic[i] = sifive_plic_create(
+ memmap[WALLY_PLIC].base + i * memmap[WALLY_PLIC].size,
+ plic_hart_config, hart_count, base_hartid,
+ WALLY_PLIC_NUM_SOURCES,
+ WALLY_PLIC_NUM_PRIORITIES,
+ WALLY_PLIC_PRIORITY_BASE,
+ WALLY_PLIC_PENDING_BASE,
+ WALLY_PLIC_ENABLE_BASE,
+ WALLY_PLIC_ENABLE_STRIDE,
+ WALLY_PLIC_CONTEXT_BASE,
+ WALLY_PLIC_CONTEXT_STRIDE,
+ memmap[WALLY_PLIC].size);
+ g_free(plic_hart_config);
+
+ /* Try to use different PLIC instance based device type */
+ if (i == 0) {
+ mmio_plic = s->plic[i];
+ }
+ }
+
+ if (riscv_is_32bit(&s->soc[0])) {
+#if HOST_LONG_BITS == 64
+ /* limit RAM size in a 32-bit system */
+ if (machine->ram_size > 10 * GiB) {
+ machine->ram_size = 10 * GiB;
+ error_report("Limiting RAM size to 10 GiB");
+ }
+#endif
+ }
+
+ /* register system main memory (actual RAM) */
+ memory_region_add_subregion(system_memory, memmap[WALLY_DRAM].base,
+ machine->ram);
+
+ /* create device tree */
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+ riscv_is_32bit(&s->soc[0]));
+
+ /* boot rom */
+ memory_region_init_rom(mask_rom, NULL, "wally_board.mrom",
+ memmap[WALLY_MROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[WALLY_MROM].base,
+ mask_rom);
+
+ if (riscv_is_32bit(&s->soc[0])) {
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
+ RISCV32_BIOS_BIN, start_addr, NULL);
+ } else {
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
+ RISCV64_BIOS_BIN, start_addr, NULL);
+ }
+
+ if (machine->kernel_filename) {
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
+ firmware_end_addr);
+
+ kernel_entry = riscv_load_kernel(machine->kernel_filename,
+ kernel_start_addr, NULL);
+
+ if (machine->initrd_filename) {
+ hwaddr start;
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
+ machine->ram_size, kernel_entry,
+ &start);
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
+ end);
+ }
+ } else {
+ /*
+ * If dynamic firmware is used, it doesn't know where is the next mode
+ * if kernel argument is not set.
+ */
+ kernel_entry = 0;
+ }
+
+ /* Compute the fdt load address in dram */
+ fdt_load_addr = riscv_load_fdt(memmap[WALLY_DRAM].base,
+ machine->ram_size, machine->fdt);
+ /* load the reset vector */
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
+ wally_memmap[WALLY_MROM].base,
+ wally_memmap[WALLY_MROM].size, kernel_entry,
+ fdt_load_addr, machine->fdt);
+
+ serial_mm_init(system_memory, memmap[WALLY_UART0].base,
+ 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
+ serial_hd(0), DEVICE_LITTLE_ENDIAN);
+}
+
+static void wally_machine_instance_init(Object *obj)
+{
+}
+
+static void wally_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "Wally SoC";
+ mc->init = wally_machine_init;
+ mc->max_cpus = WALLY_CPUS_MAX;
+ mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+ mc->pci_allow_0_address = true;
+ mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
+ mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
+ mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
+ mc->numa_mem_supported = false;
+ mc->default_ram_id = "wally_board.ram";
+
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+}
+
+static const TypeInfo wally_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("wally"),
+ .parent = TYPE_MACHINE,
+ .class_init = wally_machine_class_init,
+ .instance_init = wally_machine_instance_init,
+ .instance_size = sizeof(WallyState),
+};
+
+static void wally_machine_init_register_types(void)
+{
+ type_register_static(&wally_machine_typeinfo);
+}
+
+type_init(wally_machine_init_register_types)
diff --git a/include/hw/riscv/wally.h b/include/hw/riscv/wally.h
new file mode 100644
index 0000000000..80f2cc15dc
--- /dev/null
+++ b/include/hw/riscv/wally.h
@@ -0,0 +1,79 @@
+/*
+ * QEMU RISC-V Wally machine interface
+ * Modified from VirtIO model
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ * *** What should we say for copyright?
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_WALLY_H
+#define HW_RISCV_WALLY_H
+
+#include "hw/riscv/riscv_hart.h"
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define WALLY_CPUS_MAX 8
+#define WALLY_SOCKETS_MAX 8
+
+#define TYPE_RISCV_WALLY_MACHINE MACHINE_TYPE_NAME("wally")
+typedef struct WallyState WallyState;
+DECLARE_INSTANCE_CHECKER(WallyState, RISCV_WALLY_MACHINE,
+ TYPE_RISCV_WALLY_MACHINE)
+
+struct WallyState {
+ /*< private >*/
+ MachineState parent;
+
+ /*< public >*/
+ RISCVHartArrayState soc[WALLY_SOCKETS_MAX];
+ DeviceState *plic[WALLY_SOCKETS_MAX];
+
+ int fdt_size;
+ bool have_aclint;
+};
+
+enum {
+ WALLY_MROM,
+ WALLY_CLINT,
+ WALLY_PLIC,
+ WALLY_UART0,
+ WALLY_DRAM,
+};
+
+enum {
+ UART0_IRQ = 10,
+ WALLYIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
+};
+
+#define WALLY_PLIC_NUM_SOURCES 127
+#define WALLY_PLIC_NUM_PRIORITIES 7
+#define WALLY_PLIC_PRIORITY_BASE 0x04
+#define WALLY_PLIC_PENDING_BASE 0x1000
+#define WALLY_PLIC_ENABLE_BASE 0x2000
+#define WALLY_PLIC_ENABLE_STRIDE 0x80
+#define WALLY_PLIC_CONTEXT_BASE 0x200000
+#define WALLY_PLIC_CONTEXT_STRIDE 0x1000
+#define WALLY_PLIC_SIZE(__num_context) \
+ (WALLY_PLIC_CONTEXT_BASE + (__num_context) * WALLY_PLIC_CONTEXT_STRIDE)
+
+#define FDT_PCI_ADDR_CELLS 3
+#define FDT_PCI_INT_CELLS 1
+#define FDT_PLIC_ADDR_CELLS 0
+#define FDT_PLIC_INT_CELLS 1
+#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
+ FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
+
+#endif
--
2.27.0

0
tests/linux-testgen/buildroot-config-src/busybox.config → linux/buildroot-config-src/busybox.config
View File

0
tests/linux-testgen/buildroot-config-src/linux.config → linux/buildroot-config-src/linux.config
View File

57
tests/linux-testgen/buildroot-config-src/main.config → linux/buildroot-config-src/main.config
View File

@ -1,8 +1,13 @@
#
# Automatically generated file; DO NOT EDIT.
# Buildroot -g73f9753-dirty Configuration
# Buildroot 2021.05 Configuration
#
BR2_HAVE_DOT_CONFIG=y
BR2_HOST_GCC_AT_LEAST_4_9=y
BR2_HOST_GCC_AT_LEAST_5=y
BR2_HOST_GCC_AT_LEAST_6=y
BR2_HOST_GCC_AT_LEAST_7=y
BR2_HOST_GCC_AT_LEAST_8=y
#
# Target options
@ -101,7 +106,6 @@ BR2_ENABLE_DEBUG=y
# BR2_DEBUG_1 is not set
# BR2_DEBUG_2 is not set
BR2_DEBUG_3=y
# BR2_ENABLE_RUNTIME_DEBUG is not set
# BR2_STRIP_strip is not set
# BR2_OPTIMIZE_0 is not set
# BR2_OPTIMIZE_1 is not set
@ -165,11 +169,9 @@ BR2_KERNEL_HEADERS_AS_KERNEL=y
# BR2_KERNEL_HEADERS_5_10 is not set
# BR2_KERNEL_HEADERS_5_11 is not set
# BR2_KERNEL_HEADERS_5_12 is not set
# BR2_KERNEL_HEADERS_5_13 is not set
# BR2_KERNEL_HEADERS_VERSION is not set
# BR2_KERNEL_HEADERS_CUSTOM_TARBALL is not set
# BR2_KERNEL_HEADERS_CUSTOM_GIT is not set
# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_13 is not set
# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_12 is not set
# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_11 is not set
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_10=y
@ -250,7 +252,6 @@ BR2_BINUTILS_EXTRA_CONFIG_OPTIONS=""
# BR2_GCC_VERSION_8_X is not set
# BR2_GCC_VERSION_9_X is not set
BR2_GCC_VERSION_10_X=y
# BR2_GCC_VERSION_11_X is not set
BR2_GCC_VERSION="10.3.0"
BR2_EXTRA_GCC_CONFIG_OPTIONS=""
# BR2_TOOLCHAIN_BUILDROOT_CXX is not set
@ -368,10 +369,7 @@ BR2_TARGET_GENERIC_PASSWD_METHOD="sha-256"
BR2_INIT_BUSYBOX=y
# BR2_INIT_SYSV is not set
# BR2_INIT_OPENRC is not set
#
# systemd needs a glibc toolchain w/ SSP, headers >= 3.10, host and target gcc >= 5
#
# BR2_INIT_SYSTEMD is not set
# BR2_INIT_NONE is not set
# BR2_ROOTFS_DEVICE_CREATION_STATIC is not set
BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_DEVTMPFS=y
@ -656,7 +654,6 @@ BR2_PACKAGE_GDB_ARCH_SUPPORTS=y
# BR2_PACKAGE_IOZONE is not set
# BR2_PACKAGE_KTAP is not set
# BR2_PACKAGE_LATENCYTOP is not set
# BR2_PACKAGE_LIBBPF is not set
# BR2_PACKAGE_LMBENCH is not set
BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y
# BR2_PACKAGE_LTP_TESTSUITE is not set
@ -668,7 +665,6 @@ BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y
# BR2_PACKAGE_NETSNIFF_NG is not set
# BR2_PACKAGE_NMON is not set
# BR2_PACKAGE_PAX_UTILS is not set
# BR2_PACKAGE_POKE is not set
# BR2_PACKAGE_PV is not set
# BR2_PACKAGE_RAMSMP is not set
# BR2_PACKAGE_RAMSPEED is not set
@ -950,10 +946,6 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
# apitrace needs a toolchain w/ C++, wchar, dynamic library, threads, gcc >= 4.9
#
#
# mupdf needs a toolchain w/ C++, gcc >= 4.8
#
#
# vte needs a toolchain w/ wchar, threads, C++, gcc >= 4.8
#
@ -1161,10 +1153,6 @@ BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y
# BR2_PACKAGE_USB_MODESWITCH is not set
# BR2_PACKAGE_USB_MODESWITCH_DATA is not set
#
# usbguard needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8
#
#
# usbmount requires udev to be enabled
#
@ -1185,24 +1173,19 @@ BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y
BR2_PACKAGE_HOST_ERLANG_ARCH_SUPPORTS=y
# BR2_PACKAGE_EXECLINE is not set
# BR2_PACKAGE_FICL is not set
# BR2_PACKAGE_GUILE is not set
# BR2_PACKAGE_HASERL is not set
# BR2_PACKAGE_JANET is not set
# BR2_PACKAGE_JIMTCL is not set
# BR2_PACKAGE_LUA is not set
BR2_PACKAGE_PROVIDES_HOST_LUAINTERPRETER="host-lua"
# BR2_PACKAGE_MICROPYTHON is not set
# BR2_PACKAGE_MOARVM is not set
BR2_PACKAGE_HOST_MONO_ARCH_SUPPORTS=y
BR2_PACKAGE_HOST_OPENJDK_BIN_ARCH_SUPPORTS=y
# BR2_PACKAGE_PERL is not set
# BR2_PACKAGE_PHP is not set
# BR2_PACKAGE_PYTHON is not set
# BR2_PACKAGE_PYTHON3 is not set
#
# quickjs needs a glibc or musl toolchain w/ gcc >= 4.9, host gcc >= 4.9, dynamic library
#
# BR2_PACKAGE_QUICKJS is not set
# BR2_PACKAGE_RUBY is not set
# BR2_PACKAGE_TCL is not set
@ -1928,7 +1911,6 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
# czmq needs a toolchain w/ C++, threads
#
# BR2_PACKAGE_DAQ is not set
# BR2_PACKAGE_DAQ3 is not set
# BR2_PACKAGE_DAVICI is not set
# BR2_PACKAGE_ENET is not set
@ -2024,7 +2006,6 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
#
# libpjsip needs a toolchain w/ C++, threads
#
# BR2_PACKAGE_LIBPSL is not set
# BR2_PACKAGE_LIBRELP is not set
# BR2_PACKAGE_LIBRSYNC is not set
# BR2_PACKAGE_LIBSHAIRPLAY is not set
@ -2167,7 +2148,6 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
#
# bctoolbox needs a toolchain w/ C++, threads
#
# BR2_PACKAGE_BDWGC is not set
#
# belr needs a toolchain w/ threads, C++
@ -2260,8 +2240,6 @@ BR2_PACKAGE_LIBABSEIL_CPP_ARCH_SUPPORTS=y
# libabseil-cpp needs a toolchain w/ gcc >= 4.9, C++, threads, dynamic library
#
# BR2_PACKAGE_LIBARGTABLE2 is not set
BR2_PACKAGE_LIBATOMIC_OPS_ARCH_SUPPORTS=y
# BR2_PACKAGE_LIBATOMIC_OPS is not set
# BR2_PACKAGE_LIBAVL is not set
# BR2_PACKAGE_LIBB64 is not set
# BR2_PACKAGE_LIBBACKTRACE is not set
@ -2317,7 +2295,6 @@ BR2_PACKAGE_LIBNSPR_ARCH_SUPPORT=y
# BR2_PACKAGE_LIBPTHREAD_STUBS is not set
# BR2_PACKAGE_LIBPTHSEM is not set
# BR2_PACKAGE_LIBPWQUALITY is not set
# BR2_PACKAGE_LIBQB is not set
#
# libsigc++ needs a toolchain w/ C++, gcc >= 4.8
@ -3063,7 +3040,6 @@ BR2_PACKAGE_INITSCRIPTS=y
#
# sdbusplus needs systemd and a toolchain w/ C++, gcc >= 7
#
# BR2_PACKAGE_SEATD is not set
# BR2_PACKAGE_SMACK is not set
#
@ -3147,7 +3123,6 @@ BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG=y
# BR2_PACKAGE_HOST_ANDROID_TOOLS is not set
# BR2_PACKAGE_HOST_ASN1C is not set
# BR2_PACKAGE_HOST_BABELTRACE2 is not set
# BR2_PACKAGE_HOST_BMAP_TOOLS is not set
# BR2_PACKAGE_HOST_BTRFS_PROGS is not set
# BR2_PACKAGE_HOST_CHECKPOLICY is not set
# BR2_PACKAGE_HOST_CHECKSEC is not set
@ -3155,12 +3130,10 @@ BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG=y
# BR2_PACKAGE_HOST_CRAMFS is not set
# BR2_PACKAGE_HOST_CRYPTSETUP is not set
# BR2_PACKAGE_HOST_DBUS_PYTHON is not set
#
# host dfu-util needs a toolchain w/ host gcc >= 4.9
#
# BR2_PACKAGE_HOST_DFU_UTIL is not set
# BR2_PACKAGE_HOST_DOS2UNIX is not set
# BR2_PACKAGE_HOST_DOSFSTOOLS is not set
# BR2_PACKAGE_HOST_DOXYGEN is not set
# BR2_PACKAGE_HOST_DTC is not set
BR2_PACKAGE_HOST_E2FSPROGS=y
# BR2_PACKAGE_HOST_E2TOOLS is not set
@ -3197,10 +3170,7 @@ BR2_PACKAGE_HOST_KMOD=y
# BR2_PACKAGE_HOST_MTD is not set
# BR2_PACKAGE_HOST_MTOOLS is not set
# BR2_PACKAGE_HOST_ODB is not set
#
# host openocd needs a toolchain w/ host gcc >= 4.9
#
# BR2_PACKAGE_HOST_OPENOCD is not set
# BR2_PACKAGE_HOST_OPKG_UTILS is not set
# BR2_PACKAGE_HOST_PARTED is not set
BR2_PACKAGE_HOST_PATCHELF=y
@ -3225,10 +3195,7 @@ BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y
# BR2_PACKAGE_HOST_QEMU_LINUX_USER_MODE is not set
# BR2_PACKAGE_HOST_QEMU_VDE2 is not set
# BR2_PACKAGE_HOST_QEMU_VIRTFS is not set
#
# USB passthrough support needs a toolchain w/ host gcc >= 4.9
#
# BR2_PACKAGE_HOST_QEMU_USB is not set
# BR2_PACKAGE_HOST_QORIQ_RCW is not set
# BR2_PACKAGE_HOST_RAUC is not set
BR2_PACKAGE_HOST_RUSTC_ARCH_SUPPORTS=y

80
linux/buildroot-scripts/start-buildroot-session.sh Executable file
View File

@ -0,0 +1,80 @@
script_dir=$(readlink -f ./)
personal_config=$(readlink -f ../buildroot-config-src)
shared_config=$RISCV/buildroot-config-src
if [ -d "$shared_config" ]; then
echo "Hold the horses, friend!" >&2
echo "There is already a buildroot-config-src folder in \$RISCV" >&2
if [ ! -f "$shared_config/.owner" ]; then
echo "Oy vey -- it was improperly created too!" >&2
echo "I see no .owner file in it!" >&2
echo "Maybe just delete it." >&2
exit 1
fi
owner=$(cat $shared_config/.owner)
echo "It was created by $owner." >&2
echo "Please contact them before overwriting their source files." >&2
exit 1
fi
echo "Starting new buildroot session"
# Copy configs to shared location
echo "Elevate permissions to copy ../buildroot-config-src to \$RISCV"
sudo cp -r "$personal_config" "$shared_config"
sudo chown -R cad $shared_config
# Document who created these configs
whoami>.owner
sudo mv .owner $shared_config
# Copy over main.config
echo "Copying main.config to buildroot/.config."
sudo cp $shared_config/main.config $RISCV/buildroot/.config
sudo chown cad $RISCV/buildroot/.config
echo "=============================================="
echo "I'm about to sign you in as cad."
echo ""
echo "You can go straight to the \$RISCV/buildroot"
echo "and run \`make\` if you want."
echo ""
echo "You can also run:"
echo " * \`make menuconfig\`"
echo " * \`make linux-menuconfig\`"
echo " * \`make busybox-menuconfig\`"
echo "but if you do, you have to make extra certain"
echo "that you LOAD and SAVE configs from/to "
echo "\$RISCV/buildroot-config-src."
echo ""
echo "Run \`exit\` to sign out when you are done."
echo "And then any configs that were modified in"
echo "\$RISCV/buildroot-config-src will be copied"
echo "back to ../buildroot-config-src."
echo "=============================================="
read -p "Press any key to sign in as cad" -n1 -s
echo ""
cd $RISCV
sudo su cad
cd $script_dir
echo ""
echo "Ending buildroot session"
if [ ! -d "$shared_config" ]; then
echo "Warning: $shared_config has already been deleted."
exit 0
fi
if [ ! -f "$shared_config/.owner" ]; then
echo "Oy vey -- no .owner file found.">&2
echo "Not sure whether to delete $shared_config.">&2
exit 1
fi
owner=$(cat "$shared_config"/.owner)
if [ $owner != $(whoami) ]; then
echo "Whoah there! It seems $owner created $shared_config.">&2
echo "Ask them before deleting their work.">&2
exit 1
fi
echo "Copying modified configs from \$RISCV/buildroot-config-src back to ../buildroot-config-src."
for file in $personal_config/*; do
file=$(basename $file)
cp $shared_config/$file $personal_config/$file
done
echo "Elevate permissions to remove personal configs from shared location."
sudo rm -r $shared_config

6
linux/devicetree/debug/dumpdts.sh Executable file
View File

@ -0,0 +1,6 @@
#!/bin/bash
machine=virt
qemu-system-riscv64 -M $machine,dumpdtb=$machine.dtb -bios $RISCV/buildroot/output/images/fw_jump.elf
dtc -I dtb -O dts $machine.dtb > $machine.dts

75
linux/devicetree/virt-trimmed.dts Normal file
View File

@ -0,0 +1,75 @@
/dts-v1/;
/ {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "riscv-virtio-trimmed";
model = "riscv-virtio-trimmed,qemu";
chosen {
linux,initrd-end = <0x85c43a00>;
linux,initrd-start = <0x84200000>;
bootargs = "root=/dev/vda ro";
stdout-path = "/soc/uart@10000000";
};
memory@80000000 {
device_type = "memory";
reg = <0x00 0x80000000 0x00 0x8000000>;
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
timebase-frequency = <0x989680>;
cpu@0 {
phandle = <0x01>;
device_type = "cpu";
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
mmu-type = "riscv,sv48";
interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x02>;
};
};
};
soc {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "simple-bus";
ranges;
uart@10000000 {
interrupts = <0x0a>;
interrupt-parent = <0x03>;
clock-frequency = <0x384000>;
reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a";
};
plic@c000000 {
phandle = <0x03>;
riscv,ndev = <0x35>;
reg = <0x00 0xc000000 0x00 0x210000>;
interrupts-extended = <0x02 0x0b 0x02 0x09>;
interrupt-controller;
compatible = "sifive,plic-1.0.0\0riscv,plic0";
#interrupt-cells = <0x01>;
#address-cells = <0x00>;
};
clint@2000000 {
interrupts-extended = <0x02 0x03 0x02 0x07>;
reg = <0x00 0x2000000 0x00 0x10000>;
compatible = "sifive,clint0\0riscv,clint0";
};
};
};

25
linux/testvector-generation/genTrace.gdb Executable file
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@ -0,0 +1,25 @@
define genTrace
# Arguments
set $tcpPort=$arg0
set $vmlinux=$arg1
# GDB config
set pagination off
set logging overwrite on
set logging redirect on
set confirm off
# Connect to QEMU session
eval "target extended-remote :%d",$tcpPort
# Symbol Files
eval "file %s",$vmlinux
# Run until Linux login prompt
b do_idle
ignore 1 2
c
kill
q
end

43
linux/testvector-generation/genTrace.sh Executable file
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@ -0,0 +1,43 @@
#!/bin/bash
tcpPort=1234
imageDir=$RISCV/buildroot/output/images
outDir=$RISCV/linux-testvectors
recordFile="$outDir/all.qemu"
traceFile="$outDir/all.txt"
read -p "Warning: running this script will overwrite the contents of:
* $recordFile
* $traceFile
Would you like to proceed? (y/n) " -n 1 -r
echo
if [[ $REPLY =~ ^[Yy]$ ]]
then
# Create Output Directory
sudo mkdir -p $outDir
sudo chown cad $outDir
sudo touch $recordFile
sudo touch $traceFile
sudo chmod a+rw $recordFile
sudo chmod a+rw $traceFile
# Compile Devicetree from Source
dtc -I dts -O dtb ../devicetree/virt-trimmed.dts > ../devicetree/virt-trimmed.dtb
# QEMU Simulation
(qemu-system-riscv64 \
-M virt -dtb ../devicetree/virt-trimmed.dtb \
-nographic -serial /dev/null \
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile \
-d nochain,cpu,in_asm \
-gdb tcp::$tcpPort -S \
2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py | ./remove_dup.awk > $traceFile) \
& riscv64-unknown-elf-gdb -quiet -x genTrace.gdb -ex "genTrace $tcpPort \"$imageDir/vmlinux\""
# Cleanup
sudo chown cad $recordFile
sudo chown cad $traceFile
sudo chmod o-w $recordFile
sudo chmod o-w $traceFile
fi

220
linux/testvector-generation/parseGDBtoTrace.py Executable file
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@ -0,0 +1,220 @@
#! /usr/bin/python3
import sys, fileinput, re
# Ross Thompson
# July 27, 2021
# Rewrite of the linux trace parser.
InstrStartDelim = '=>'
InstrEndDelim = '-----'
#InputFile = 'noparse.txt'
#InputFile = sys.stdin
#InputFile = 'temp.txt'
#OutputFile = 'parsedAll.txt'
HUMAN_READABLE = False
def toDict(lst):
'Converts the list of register values to a dictionary'
dct= {}
for item in lst:
regTup = item.split()
dct[regTup[0]] = int(regTup[2], 10)
del dct['pc']
return dct
def whichClass(text, Regs):
'Which instruction class?'
#print(text, Regs)
if text[0:2] == 'ld' or text[0:2] == 'lw' or text[0:2] == 'lh' or text[0:2] == 'lb':
return ('load', WhatAddr(text, Regs), None, WhatMemDestSource(text))
elif text[0:2] == 'sd' or text[0:2] == 'sw' or text[0:2] == 'sh' or text[0:2] == 'sb':
return ('store', WhatAddr(text, Regs), WhatMemDestSource(text), None)
elif text[0:3] == 'amo':
return ('amo', WhatAddrAMO(text, Regs), WhatMemDestSource(text), WhatMemDestSource(text))
elif text[0:2] == 'lr':
return ('lr', WhatAddrLR(text, Regs), None, WhatMemDestSource(text))
elif text[0:2] == 'sc':
return ('sc', WhatAddrSC(text, Regs), WhatMemDestSource(text), None)
else:
return ('other', None, None, None)
def whatChanged(dct0, dct1):
'Compares two dictionaries of instrution registers and indicates which registers changed'
dct = {}
for key in dct0:
if (dct1[key] != dct0[key]):
dct[key] = dct1[key]
return dct
def WhatMemDestSource(text):
''''What is the destination register. Used to compute where the read data is
on a load or the write data on a store.'''
return text.split()[1].split(',')[0]
def WhatAddr(text, Regs):
'What is the data memory address?'
Imm = text.split(',')[1]
(Imm, Src) = Imm.split('(')
Imm = int(Imm.strip(), 10)
Src = Src.strip(')').strip()
RegVal = Regs[Src]
return Imm + RegVal
def WhatAddrAMO(text, Regs):
'What is the data memory address?'
Src = text.split('(')[1]
Src = Src.strip(')').strip()
return Regs[Src]
def WhatAddrLR(text, Regs):
'What is the data memory address?'
Src = text.split('(')[1]
Src = Src.strip(')').strip()
return Regs[Src]
def WhatAddrSC(text, Regs):
'What is the data memory address?'
Src = text.split('(')[1]
Src = Src.strip(')').strip()
return Regs[Src]
def PrintInstr(instr, fp):
if instr[2] == None:
return
ChangedRegisters = instr[4]
GPR = ''
CSR = []
for key in ChangedRegisters:
# filter out csr which are not checked.
if(key in RegNumber):
if(RegNumber[key] < 32):
# GPR
if(HUMAN_READABLE):
GPR = '{:-2d} {:016x}'.format(RegNumber[key], ChangedRegisters[key])
else:
GPR = '{:d} {:x}'.format(RegNumber[key], ChangedRegisters[key])
else:
if(HUMAN_READABLE):
CSR.extend([key, '{:016x}'.format(ChangedRegisters[key])])
else:
CSR.extend([key, '{:x}'.format(ChangedRegisters[key])])
CSRStr = ' '.join(CSR)
#print(instr)
if (HUMAN_READABLE == True):
fp.write('{:016x} {:08x} {:25s}'.format(instr[0], instr[1], instr[2]))
if(len(GPR) != 0):
fp.write(' GPR {}'.format(GPR))
if(instr[3] == 'load' or instr[3] == 'lr'):
fp.write(' MemR {:016x} {:016x} {:016x}'.format(instr[5], 0, instr[7]))
if(instr[3] == 'store'):
fp.write('\t\t\t MemW {:016x} {:016x} {:016x}'.format(instr[5], instr[6], 0))
if(len(CSR) != 0):
fp.write(' CSR {}'.format(CSRStr))
else:
fp.write('{:x} {:x} {:s}'.format(instr[0], instr[1], instr[2].replace(' ', '_')))
if(len(GPR) != 0):
fp.write(' GPR {}'.format(GPR))
if(instr[3] == 'load' or instr[3] == 'lr'):
fp.write(' MemR {:x} {:x} {:x}'.format(instr[5], 0, instr[7]))
if(instr[3] == 'store'):
fp.write(' MemW {:x} {:x} {:x}'.format(instr[5], instr[6], 0))
if(len(CSR) != 0):
fp.write(' CSR {}'.format(CSRStr))
fp.write('\n')
# reg number
RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45}
# initial state
CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0}, {}, None, None, None]
#with open (InputFile, 'r') as InputFileFP:
#lines = InputFileFP.readlines()
lineNum = 0
StartLine = 0
EndLine = 0
numInstrs = 0
#instructions = []
MemAdr = 0
lines = []
interrupts=open('interrupts.txt','w')
interrupts.close()
for line in fileinput.input('-'):
if line.startswith('riscv_cpu_do_interrupt'):
with open('interrupts.txt','a') as interrupts:
interrupts.write(str(numInstrs)+': '+line.strip('riscv_cpu_do_interrupt'))
break
lines.insert(lineNum, line)
if InstrStartDelim in line:
lineNum = 0
StartLine = lineNum
elif InstrEndDelim in line:
EndLine = lineNum
(InstrBits, text) = lines[StartLine].split(':')
InstrBits = int(InstrBits.strip('=> '), 16)
text = text.strip()
PC = int(lines[StartLine+1].split(':')[0][2:], 16)
Regs = toDict(lines[StartLine+2:EndLine])
(Class, Addr, WriteReg, ReadReg) = whichClass(text, Regs)
#print("CWR", Class, WriteReg, ReadReg)
PreviousInstr = CurrentInstr
Changed = whatChanged(PreviousInstr[4], Regs)
if (ReadReg !=None): ReadData = ReadReg
else: ReadData = None
if (WriteReg !=None): WriteData = WriteReg
else: WriteData = None
CurrentInstr = [PC, InstrBits, text, Class, Regs, Changed, Addr, WriteData, ReadData]
#print(CurrentInstr[0:4], PreviousInstr[5], CurrentInstr[6:7], PreviousInstr[8])
# pc, instrbits, text and class come from the last line.
MoveInstrToRegWriteLst = PreviousInstr[0:4]
# updated registers come from the current line.
MoveInstrToRegWriteLst.append(CurrentInstr[5]) # destination regs
# memory address if present comes from the last line.
MoveInstrToRegWriteLst.append(PreviousInstr[6]) # MemAdrM
# write data from the previous line
#MoveInstrToRegWriteLst.append(PreviousInstr[7]) # WriteDataM
if (PreviousInstr[7] != None):
MoveInstrToRegWriteLst.append(Regs[PreviousInstr[7]]) # WriteDataM
else:
MoveInstrToRegWriteLst.append(None)
# read data from the current line
#MoveInstrToRegWriteLst.append(PreviousInstr[8]) # ReadDataM
if (PreviousInstr[8] != None):
MoveInstrToRegWriteLst.append(Regs[PreviousInstr[8]]) # ReadDataM
else:
MoveInstrToRegWriteLst.append(None)
lines.clear()
#instructions.append(MoveInstrToRegWriteLst)
PrintInstr(MoveInstrToRegWriteLst, sys.stdout)
numInstrs +=1
if (numInstrs % 1e4 == 0):
sys.stderr.write('Trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n')
sys.stderr.flush()
lineNum += 1
#for instruction in instructions[1::]:
#with open(OutputFile, 'w') as OutputFileFP:
# print('opened file')

148
linux/testvector-generation/parseQemuToGDB.py Executable file
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@ -0,0 +1,148 @@
#! /usr/bin/python3
import fileinput, sys
sys.stderr.write("reminder: parse_qemu.py takes input from stdin\n")
parseState = "idle"
beginPageFault = 0
inPageFault = 0
endPageFault = 0
CSRs = {}
pageFaultCSRs = {}
regs = {}
pageFaultRegs = {}
instrs = {}
instrCount = 0
returnAdr = 0
def printPC(l):
global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, instrCount
if not inPageFault:
inst = l.split()
if len(inst) > 3:
print(f'=> {inst[1]}:\t{inst[2]} {inst[3]}')
else:
print(f'=> {inst[1]}:\t{inst[2]}')
print(f'{inst[0]} 0x{inst[1]}')
instrCount += 1
if ((instrCount % 100000) == 0):
sys.stderr.write("QEMU parser reached "+str(instrCount)+" instrs\n")
def printCSRs():
global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs
if not inPageFault:
for (csr,val) in CSRs.items():
print('{}{}{:#x} {}'.format(csr, ' '*(15-len(csr)), val, val))
print('-----')
def parseCSRs(l):
global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs
if l.strip() and (not l.startswith("Disassembler")) and (not l.startswith("Please")):
# If we've hit the register file
if l.startswith(' x0/zero'):
parseState = "regFile"
if not inPageFault:
instr = instrs[CSRs["pc"]]
printPC(instr)
parseRegs(l)
# If we've hit a CSR
else:
csr = l.split()[0]
val = int(l.split()[1],16)
# Commented out this conditional because the pageFault instrs don't corrupt CSRs
#if inPageFault:
# Not sure if these CSRs should be updated or not during page fault.
#if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"):
# We do update some CSRs
# CSRs[csr] = val
#else:
# Others we preserve until changed later
# pageFaultCSRs[csr] = val
#elif pageFaultCSRs and (csr in pageFaultCSRs):
# if (val != pageFaultCSRs[csr]):
# del pageFaultCSRs[csr]
# CSRs[csr] = val
#else:
# CSRs[csr] = val
#
# However SEPC and STVAL do get corrupted upon exiting
if endPageFault and ((csr == 'sepc') or (csr == 'stval')):
CSRs[csr] = returnAdr
pageFaultCSRs[csr] = val
elif pageFaultCSRs and (csr in pageFaultCSRs):
if (val != pageFaultCSRs[csr]):
del pageFaultCSRs[csr]
CSRs[csr] = val
else:
CSRs[csr] = val
def parseRegs(l):
global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, pageFaultRegs
if "pc" in l:
printCSRs()
# New non-disassembled instruction
parseState = "CSRs"
parseCSRs(l)
elif l.startswith('--------'):
# End of disassembled instruction
printCSRs()
parseState = "idle"
else:
s = l.split()
for i in range(0,len(s),2):
if '/' in s[i]:
reg = s[i].split('/')[1]
val = int(s[i+1], 16)
if inPageFault:
pageFaultRegs[reg] = val
else:
if pageFaultRegs and (reg in pageFaultRegs):
if (val != pageFaultRegs[reg]):
del pageFaultRegs[reg]
regs[reg] = val
else:
regs[reg] = val
val = regs[reg]
print('{}{}{:#x} {}'.format(reg, ' '*(15-len(reg)), val, val))
else:
sys.stderr.write("Whoops. Expected a list of reg file regs; got:\n"+l)
#############
# Main Code #
#############
interrupt_line=""
for l in fileinput.input():
#sys.stderr.write(l)
if l.startswith('riscv_cpu_do_interrupt'):
sys.stderr.write(l)
interrupt_line = l.strip('\n')
continue
elif l.startswith('qemu-system-riscv64: QEMU: Terminated via GDBstub'):
break
elif l.startswith('IN:'):
# New disassembled instr
if len(interrupt_line)>0:
print(interrupt_line)
interrupt_line=""
parseState = "instr"
elif (parseState == "instr") and l.startswith('0x'):
# New instruction
if len(interrupt_line)>0:
print(interrupt_line)
interrupt_line=""
if "out of bounds" in l:
sys.stderr.write("Detected QEMU page fault error\n")
beginPageFault = not inPageFault
if beginPageFault:
returnAdr = int(l.split()[0][2:-1], 16)
sys.stderr.write('Saving SEPC of '+hex(returnAdr)+'\n')
inPageFault = 1
else:
endPageFault = inPageFault
inPageFault = 0
adr = int(l.split()[0][2:-1], 16)
instrs[adr] = l
parseState = "CSRs"
elif parseState == "CSRs":
parseCSRs(l)
elif parseState == "regFile":
parseRegs(l)

20
linux/testvector-generation/remove_dup.awk Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/awk -f
BEGIN{
old = "first"
}
{
if($1 != old){
if(old != "first"){
print oldAll
}
}
old=$1
oldAll=$0
}
END{
print oldAll
}

542
linux/wallyVirtIO.patch
View File

@ -1,542 +0,0 @@
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4a3cd2599a..39b46e3122 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
+#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/boards.h"
@@ -44,19 +45,10 @@
#include "hw/display/ramfb.h"
static const MemMapEntry virt_memmap[] = {
- [VIRT_DEBUG] = { 0x0, 0x100 },
[VIRT_MROM] = { 0x1000, 0xf000 },
- [VIRT_TEST] = { 0x100000, 0x1000 },
- [VIRT_RTC] = { 0x101000, 0x1000 },
[VIRT_CLINT] = { 0x2000000, 0x10000 },
- [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
[VIRT_UART0] = { 0x10000000, 0x100 },
- [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
- [VIRT_FW_CFG] = { 0x10100000, 0x18 },
- [VIRT_FLASH] = { 0x20000000, 0x4000000 },
- [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
- [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
[VIRT_DRAM] = { 0x80000000, 0x0 },
};
@@ -67,139 +59,23 @@ static const MemMapEntry virt_memmap[] = {
/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
-static MemMapEntry virt_high_pcie_memmap;
-
#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
-static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
- const char *name,
- const char *alias_prop_name)
-{
- /*
- * Create a single flash device. We use the same parameters as
- * the flash devices on the ARM virt board.
- */
- DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
-
- qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
- qdev_prop_set_uint8(dev, "width", 4);
- qdev_prop_set_uint8(dev, "device-width", 2);
- qdev_prop_set_bit(dev, "big-endian", false);
- qdev_prop_set_uint16(dev, "id0", 0x89);
- qdev_prop_set_uint16(dev, "id1", 0x18);
- qdev_prop_set_uint16(dev, "id2", 0x00);
- qdev_prop_set_uint16(dev, "id3", 0x00);
- qdev_prop_set_string(dev, "name", name);
-
- object_property_add_child(OBJECT(s), name, OBJECT(dev));
- object_property_add_alias(OBJECT(s), alias_prop_name,
- OBJECT(dev), "drive");
-
- return PFLASH_CFI01(dev);
-}
-
-static void virt_flash_create(RISCVVirtState *s)
-{
- s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
- s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
-}
-
-static void virt_flash_map1(PFlashCFI01 *flash,
- hwaddr base, hwaddr size,
- MemoryRegion *sysmem)
-{
- DeviceState *dev = DEVICE(flash);
-
- assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
- assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
- qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-
- memory_region_add_subregion(sysmem, base,
- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
- 0));
-}
-
-static void virt_flash_map(RISCVVirtState *s,
- MemoryRegion *sysmem)
-{
- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
- hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
-
- virt_flash_map1(s->flash[0], flashbase, flashsize,
- sysmem);
- virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
- sysmem);
-}
-
-static void create_pcie_irq_map(void *fdt, char *nodename,
- uint32_t plic_phandle)
-{
- int pin, dev;
- uint32_t
- full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
- uint32_t *irq_map = full_irq_map;
-
- /* This code creates a standard swizzle of interrupts such that
- * each device's first interrupt is based on it's PCI_SLOT number.
- * (See pci_swizzle_map_irq_fn())
- *
- * We only need one entry per interrupt in the table (not one per
- * possible slot) seeing the interrupt-map-mask will allow the table
- * to wrap to any number of devices.
- */
- for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
- int devfn = dev * 0x8;
-
- for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
- int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
- int i = 0;
-
- irq_map[i] = cpu_to_be32(devfn << 8);
-
- i += FDT_PCI_ADDR_CELLS;
- irq_map[i] = cpu_to_be32(pin + 1);
-
- i += FDT_PCI_INT_CELLS;
- irq_map[i++] = cpu_to_be32(plic_phandle);
-
- i += FDT_PLIC_ADDR_CELLS;
- irq_map[i] = cpu_to_be32(irq_nr);
-
- irq_map += FDT_INT_MAP_WIDTH;
- }
- }
-
- qemu_fdt_setprop(fdt, nodename, "interrupt-map",
- full_irq_map, sizeof(full_irq_map));
-
- qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
- 0x1800, 0, 0, 0x7);
-}
-
static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
uint64_t mem_size, const char *cmdline, bool is_32_bit)
{
void *fdt;
- int i, cpu, socket;
+ //int i, cpu, socket;
+ int cpu, socket;
MachineState *mc = MACHINE(s);
uint64_t addr, size;
uint32_t *clint_cells, *plic_cells;
unsigned long clint_addr, plic_addr;
uint32_t plic_phandle[MAX_NODES];
- uint32_t cpu_phandle, intc_phandle, test_phandle;
+ uint32_t cpu_phandle, intc_phandle;
uint32_t phandle = 1, plic_mmio_phandle = 1;
- uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
char *mem_name, *cpu_name, *core_name, *intc_name;
char *name, *clint_name, *plic_name, *clust_name;
- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
- hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
- static const char * const clint_compat[2] = {
- "sifive,clint0", "riscv,clint0"
- };
- static const char * const plic_compat[2] = {
- "sifive,plic-1.0.0", "riscv,plic0"
- };
if (mc->dtb) {
fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
@@ -305,8 +181,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
(memmap[VIRT_CLINT].size * socket);
clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
qemu_fdt_add_subnode(fdt, clint_name);
- qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
- (char **)&clint_compat, ARRAY_SIZE(clint_compat));
+ qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
qemu_fdt_setprop_cells(fdt, clint_name, "reg",
0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
@@ -322,8 +197,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
"#address-cells", FDT_PLIC_ADDR_CELLS);
qemu_fdt_setprop_cell(fdt, plic_name,
"#interrupt-cells", FDT_PLIC_INT_CELLS);
- qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
- (char **)&plic_compat, ARRAY_SIZE(plic_compat));
+ qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
@@ -342,95 +216,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
for (socket = 0; socket < riscv_socket_count(mc); socket++) {
if (socket == 0) {
plic_mmio_phandle = plic_phandle[socket];
- plic_virtio_phandle = plic_phandle[socket];
- plic_pcie_phandle = plic_phandle[socket];
- }
- if (socket == 1) {
- plic_virtio_phandle = plic_phandle[socket];
- plic_pcie_phandle = plic_phandle[socket];
- }
- if (socket == 2) {
- plic_pcie_phandle = plic_phandle[socket];
}
}
riscv_socket_fdt_write_distance_matrix(mc, fdt);
- for (i = 0; i < VIRTIO_COUNT; i++) {
- name = g_strdup_printf("/soc/virtio_mmio@%lx",
- (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
- qemu_fdt_setprop_cells(fdt, name, "reg",
- 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
- 0x0, memmap[VIRT_VIRTIO].size);
- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
- plic_virtio_phandle);
- qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
- g_free(name);
- }
-
- name = g_strdup_printf("/soc/pci@%lx",
- (long) memmap[VIRT_PCIE_ECAM].base);
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
- qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
- qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
- qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
- qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
- qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
- qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
- memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
- qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
- qemu_fdt_setprop_cells(fdt, name, "reg", 0,
- memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
- qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
- 1, FDT_PCI_RANGE_IOPORT, 2, 0,
- 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
- 1, FDT_PCI_RANGE_MMIO,
- 2, memmap[VIRT_PCIE_MMIO].base,
- 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
- 1, FDT_PCI_RANGE_MMIO_64BIT,
- 2, virt_high_pcie_memmap.base,
- 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
-
- create_pcie_irq_map(fdt, name, plic_pcie_phandle);
- g_free(name);
-
- test_phandle = phandle++;
- name = g_strdup_printf("/soc/test@%lx",
- (long)memmap[VIRT_TEST].base);
- qemu_fdt_add_subnode(fdt, name);
- {
- static const char * const compat[3] = {
- "sifive,test1", "sifive,test0", "syscon"
- };
- qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat,
- ARRAY_SIZE(compat));
- }
- qemu_fdt_setprop_cells(fdt, name, "reg",
- 0x0, memmap[VIRT_TEST].base,
- 0x0, memmap[VIRT_TEST].size);
- qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
- test_phandle = qemu_fdt_get_phandle(fdt, name);
- g_free(name);
-
- name = g_strdup_printf("/soc/reboot");
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
- g_free(name);
-
- name = g_strdup_printf("/soc/poweroff");
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
- g_free(name);
-
name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
@@ -445,102 +235,12 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
g_free(name);
- name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
- qemu_fdt_setprop_cells(fdt, name, "reg",
- 0x0, memmap[VIRT_RTC].base,
- 0x0, memmap[VIRT_RTC].size);
- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
- qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
- g_free(name);
-
- name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
- qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
- 2, flashbase, 2, flashsize,
- 2, flashbase + flashsize, 2, flashsize);
- qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
- g_free(name);
-
update_bootargs:
if (cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
}
-static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
- hwaddr ecam_base, hwaddr ecam_size,
- hwaddr mmio_base, hwaddr mmio_size,
- hwaddr high_mmio_base,
- hwaddr high_mmio_size,
- hwaddr pio_base,
- DeviceState *plic)
-{
- DeviceState *dev;
- MemoryRegion *ecam_alias, *ecam_reg;
- MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
- qemu_irq irq;
- int i;
-
- dev = qdev_new(TYPE_GPEX_HOST);
-
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-
- ecam_alias = g_new0(MemoryRegion, 1);
- ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
- memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
- ecam_reg, 0, ecam_size);
- memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
-
- mmio_alias = g_new0(MemoryRegion, 1);
- mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
- memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
- mmio_reg, mmio_base, mmio_size);
- memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
-
- /* Map high MMIO space */
- high_mmio_alias = g_new0(MemoryRegion, 1);
- memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
- mmio_reg, high_mmio_base, high_mmio_size);
- memory_region_add_subregion(get_system_memory(), high_mmio_base,
- high_mmio_alias);
-
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
-
- for (i = 0; i < GPEX_NUM_IRQS; i++) {
- irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
-
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
- gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
- }
-
- return dev;
-}
-
-static FWCfgState *create_fw_cfg(const MachineState *mc)
-{
- hwaddr base = virt_memmap[VIRT_FW_CFG].base;
- hwaddr size = virt_memmap[VIRT_FW_CFG].size;
- FWCfgState *fw_cfg;
- char *nodename;
-
- fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
- &address_space_memory);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
-
- nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
- qemu_fdt_add_subnode(mc->fdt, nodename);
- qemu_fdt_setprop_string(mc->fdt, nodename,
- "compatible", "qemu,fw-cfg-mmio");
- qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
- 2, base, 2, size);
- qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
- g_free(nodename);
- return fw_cfg;
-}
-
static void virt_machine_init(MachineState *machine)
{
const MemMapEntry *memmap = virt_memmap;
@@ -554,7 +254,7 @@ static void virt_machine_init(MachineState *machine)
target_ulong firmware_end_addr, kernel_start_addr;
uint32_t fdt_load_addr;
uint64_t kernel_entry;
- DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
+ DeviceState *mmio_plic;
int i, j, base_hartid, hart_count;
/* Check socket count limit */
@@ -565,7 +265,7 @@ static void virt_machine_init(MachineState *machine)
}
/* Initialize sockets */
- mmio_plic = virtio_plic = pcie_plic = NULL;
+ mmio_plic = NULL;
for (i = 0; i < riscv_socket_count(machine); i++) {
if (!riscv_socket_check_hartids(machine, i)) {
error_report("discontinuous hartids in socket%d", i);
@@ -634,15 +334,6 @@ static void virt_machine_init(MachineState *machine)
/* Try to use different PLIC instance based device type */
if (i == 0) {
mmio_plic = s->plic[i];
- virtio_plic = s->plic[i];
- pcie_plic = s->plic[i];
- }
- if (i == 1) {
- virtio_plic = s->plic[i];
- pcie_plic = s->plic[i];
- }
- if (i == 2) {
- pcie_plic = s->plic[i];
}
}
@@ -654,13 +345,6 @@ static void virt_machine_init(MachineState *machine)
error_report("Limiting RAM size to 10 GiB");
}
#endif
- virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
- virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
- } else {
- virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
- virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
- virt_high_pcie_memmap.base =
- ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
}
/* register system main memory (actual RAM) */
@@ -681,10 +365,12 @@ static void virt_machine_init(MachineState *machine)
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV32_BIOS_BIN, start_addr, NULL);
+ "opensbi-riscv32-generic-fw_dynamic.bin",
+ start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV64_BIOS_BIN, start_addr, NULL);
+ "opensbi-riscv64-generic-fw_dynamic.bin",
+ start_addr, NULL);
}
if (machine->kernel_filename) {
@@ -712,21 +398,6 @@ static void virt_machine_init(MachineState *machine)
kernel_entry = 0;
}
- if (drive_get(IF_PFLASH, 0, 0)) {
- /*
- * Pflash was supplied, let's overwrite the address we jump to after
- * reset to the base of the flash.
- */
- start_addr = virt_memmap[VIRT_FLASH].base;
- }
-
- /*
- * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
- * tree cannot be altered and we get FDT_ERR_NOSPACE.
- */
- s->fw_cfg = create_fw_cfg(machine);
- rom_set_fw(s->fw_cfg);
-
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
machine->ram_size, machine->fdt);
@@ -736,41 +407,10 @@ static void virt_machine_init(MachineState *machine)
virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, machine->fdt);
- /* SiFive Test MMIO device */
- sifive_test_create(memmap[VIRT_TEST].base);
-
- /* VirtIO MMIO devices */
- for (i = 0; i < VIRTIO_COUNT; i++) {
- sysbus_create_simple("virtio-mmio",
- memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
- qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
- }
-
- gpex_pcie_init(system_memory,
- memmap[VIRT_PCIE_ECAM].base,
- memmap[VIRT_PCIE_ECAM].size,
- memmap[VIRT_PCIE_MMIO].base,
- memmap[VIRT_PCIE_MMIO].size,
- virt_high_pcie_memmap.base,
- virt_high_pcie_memmap.size,
- memmap[VIRT_PCIE_PIO].base,
- DEVICE(pcie_plic));
-
- serial_mm_init(system_memory, memmap[VIRT_UART0].base,
+ serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
- sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
- qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
-
- virt_flash_create(s);
-
- for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
- /* Map legacy -drive if=pflash to machine properties */
- pflash_cfi01_legacy_drive(s->flash[i],
- drive_get(IF_PFLASH, 0, i));
- }
- virt_flash_map(s, system_memory);
}
static void virt_machine_instance_init(Object *obj)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 991a6bb760..401028b8d9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -269,6 +269,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
+
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
}

13
pipelined/config/buildroot/wally-config.vh
View File

@ -29,8 +29,6 @@
`define FPGA 1
`define QEMU 1
`define BUILDROOT 1
`define BUSYBEAR 0
`define LINUX_FIX_READ {'h10000005}
`define LINUX_TEST_VECTORS "../../tests/linux-testgen/linux-testvectors/"
// RV32 or RV64: XLEN = 32 or 64
@ -50,11 +48,9 @@
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0
`define MEM_DCACHE 1
`define MEM_IROM 0
`define MEM_ICACHE 1
`define MEM_VIRTMEM 1
`define DMEM `MEM_CACHE
`define IMEM `MEM_CACHE
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
@ -66,7 +62,6 @@
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
@ -129,3 +124,5 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define REPLAY 0

135
pipelined/config/busybear/wally-config.vh
View File

@ -1,135 +0,0 @@
//////////////////////////////////////////
// busybear-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 1
`define LINUX_FIX_READ {'h10000005}
`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/"
//`define LINUX_TEST_VECTORS "../../../busybear_boot/"
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
`define MISA (32'h0014112D)
`define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 1
`define ZICOUNTERS_SUPPORTED 1
`define COUNTERS 32
`define DESIGN_COMPILER 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0
`define MEM_DCACHE 1
`define MEM_IROM 0
`define MEM_ICACHE 1
`define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 2048
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 1
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16
// Address space
`define RESET_VECTOR 64'h0000000000001000
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define BOOTROM_SUPPORTED 1'b1
//`define BOOTROM_BASE 56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
//`define BOOTROM_RANGE 56'h00003FFF
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTROM_RANGE 56'h00000FFF
`define RAM_SUPPORTED 1'b1
`define RAM_BASE 56'h80000000
`define RAM_RANGE 56'h07FFFFFF
`define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 56'h80000000
`define EXT_MEM_RANGE 56'h07FFFFFF
`define CLINT_SUPPORTED 1'b1
`define CLINT_BASE 56'h02000000
`define CLINT_RANGE 56'h0000FFFF
`define GPIO_SUPPORTED 1'b1
`define GPIO_BASE 56'h10060000
`define GPIO_RANGE 56'h000000FF
`define UART_SUPPORTED 1'b1
`define UART_BASE 56'h10000000
`define UART_RANGE 56'h00000007
`define PLIC_SUPPORTED 1'b1
`define PLIC_BASE 56'h0C000000
`define PLIC_RANGE 56'h03FFFFFF
`define SDC_SUPPORTED 1'b0
`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h0000001F
// Bus Interface width
`define AHBW 64
// Test modes
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 0
// Hardware configuration
//`define UART_PRESCALE 1
`define UART_PRESCALE 0
// Interrupt configuration
`define PLIC_NUM_SRC 53
`define PLIC_UART_ID 4
`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPRED_ENABLED 1

14
pipelined/config/fpga/wally-config.vh
View File

@ -29,11 +29,8 @@
`define FPGA 1
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 0
`define DESIGN_COMPILER 0
//`define LINUX_TEST_VECTORS "/courses/e190ax/buildroot_boot/"
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
@ -50,11 +47,9 @@
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0
`define MEM_DCACHE 1
`define MEM_IROM 0
`define MEM_ICACHE 1
`define MEM_VIRTMEM 1
`define DMEM `MEM_CACHE
`define IMEM `MEM_CACHE
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
@ -66,7 +61,6 @@
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
@ -136,3 +130,5 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 1
`define REPLAY 0

32
pipelined/config/rv32e/wally-config.vh
View File

@ -29,8 +29,6 @@
`define FPGA 0
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
@ -41,21 +39,20 @@
// E
`define MISA (32'h00000010)
`define ZICSR_SUPPORTED 1
`define ZICSR_SUPPORTED 0
`define ZIFENCEI_SUPPORTED 0
`define COUNTERS 32
`define COUNTERS 0
`define ZICOUNTERS_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0
`define MEM_DCACHE 0
`define MEM_IROM 0
`define MEM_ICACHE 0
`define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
// *** replace with MEM_BUS
`define DMEM `MEM_BUS
`define IMEM `MEM_BUS
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 0
// TLB configuration. Entries should be a power of 2
`define ITLB_ENTRIES 0
@ -66,14 +63,13 @@
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
`define DIV_BITSPERCYCLE 1
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0
@ -93,16 +89,16 @@
`define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 34'h80000000
`define EXT_MEM_RANGE 34'h07FFFFFF
`define CLINT_SUPPORTED 1'b1
`define CLINT_SUPPORTED 1'b0
`define CLINT_BASE 34'h02000000
`define CLINT_RANGE 34'h0000FFFF
`define GPIO_SUPPORTED 1'b1
`define GPIO_SUPPORTED 1'b0
`define GPIO_BASE 34'h10060000
`define GPIO_RANGE 34'h000000FF
`define UART_SUPPORTED 1'b1
`define UART_SUPPORTED 1'b0
`define UART_BASE 34'h10000000
`define UART_RANGE 34'h00000007
`define PLIC_SUPPORTED 1'b1
`define PLIC_SUPPORTED 1'b0
`define PLIC_BASE 34'h0C000000
`define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b0
@ -129,6 +125,8 @@
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
`define BPRED_ENABLED 1
`define BPRED_ENABLED 0
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define REPLAY 0

1024
pipelined/config/rv32etim/BTBPredictor.txt
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1024
pipelined/config/rv32etim/twoBitPredictor.txt
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134
pipelined/config/rv32etim/wally-config.vh
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@ -1,134 +0,0 @@
//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 32
// IEEE 754 compliance
`define IEEE754 0
// E, M, C
`define MISA (32'h00001014)
`define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 0
`define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 1
`define MEM_DCACHE 0
`define MEM_IROM 1
`define MEM_ICACHE 0
`define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
`define ITLB_ENTRIES 0
`define DTLB_ENTRIES 0
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 1
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0
// Address space
`define RESET_VECTOR 32'h80000000
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h000000FF
`define RAM_SUPPORTED 1'b1
`define RAM_BASE 34'h80000000
`define RAM_RANGE 34'h000003FF
`define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 34'h80000000
`define EXT_MEM_RANGE 34'h07FFFFFF
`define CLINT_SUPPORTED 1'b1
`define CLINT_BASE 34'h02000000
`define CLINT_RANGE 34'h0000FFFF
`define GPIO_SUPPORTED 1'b1
`define GPIO_BASE 34'h10060000
`define GPIO_RANGE 34'h000000FF
`define UART_SUPPORTED 1'b1
`define UART_BASE 34'h10000000
`define UART_RANGE 34'h00000007
`define PLIC_SUPPORTED 1'b1
`define PLIC_BASE 34'h0C000000
`define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b0
`define SDC_BASE 34'h00012100
`define SDC_RANGE 34'h0000001F
// Bus Interface width
`define AHBW 32
// Test modes
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 1
// Hardware configuration
`define UART_PRESCALE 1
// Interrupt configuration
`define PLIC_NUM_SRC 4
// comment out the following if >=32 sources
`define PLIC_NUM_SRC_LT_32
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
`define BPRED_ENABLED 0
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0

15
pipelined/config/rv32gc/wally-config.vh
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@ -29,8 +29,6 @@
`define FPGA 0
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
@ -49,11 +47,9 @@
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0
`define MEM_DCACHE 1
`define MEM_IROM 0
`define MEM_ICACHE 1
`define MEM_VIRTMEM 1
`define DMEM `MEM_CACHE
`define IMEM `MEM_CACHE
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
@ -65,7 +61,6 @@
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
@ -75,7 +70,7 @@
`define DIV_BITSPERCYCLE 4
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16
`define PMP_ENTRIES 64
// Address space
`define RESET_VECTOR 32'h80000000
@ -131,3 +126,5 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define REPLAY 0

19
pipelined/config/rv32ic/wally-config.vh
View File

@ -29,8 +29,6 @@
`define FPGA 0
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
@ -49,11 +47,9 @@
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0
`define MEM_DCACHE 0
`define MEM_IROM 0
`define MEM_ICACHE 0
`define MEM_VIRTMEM 0
`define DMEM `MEM_TIM
`define IMEM `MEM_TIM
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
@ -65,7 +61,6 @@
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
@ -95,13 +90,13 @@
`define CLINT_SUPPORTED 1'b1
`define CLINT_BASE 34'h02000000
`define CLINT_RANGE 34'h0000FFFF
`define GPIO_SUPPORTED 1'b1
`define GPIO_SUPPORTED 1'b0
`define GPIO_BASE 34'h10060000
`define GPIO_RANGE 34'h000000FF
`define UART_SUPPORTED 1'b1
`define UART_SUPPORTED 1'b0
`define UART_BASE 34'h10000000
`define UART_RANGE 34'h00000007
`define PLIC_SUPPORTED 1'b1
`define PLIC_SUPPORTED 1'b0
`define PLIC_BASE 34'h0C000000
`define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b0
@ -131,3 +126,5 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define REPLAY 0

1024
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1024
pipelined/config/rv32tim/twoBitPredictor.txt
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133
pipelined/config/rv32tim/wally-config.vh
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@ -1,133 +0,0 @@
//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 32
// IEEE 754 compliance
`define IEEE754 0
`define MISA (32'h00000104)
`define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 0
`define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 1
`define MEM_DCACHE 0
`define MEM_IROM 1
`define MEM_ICACHE 0
`define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
`define ITLB_ENTRIES 0
`define DTLB_ENTRIES 0
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0
// Address space
`define RESET_VECTOR 32'h80000000
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h00000FFF
`define RAM_SUPPORTED 1'b1
`define RAM_BASE 34'h80000000
`define RAM_RANGE 34'h07FFFFFF
`define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 34'h80000000
`define EXT_MEM_RANGE 34'h07FFFFFF
`define CLINT_SUPPORTED 1'b1
`define CLINT_BASE 34'h02000000
`define CLINT_RANGE 34'h0000FFFF
`define GPIO_SUPPORTED 1'b1
`define GPIO_BASE 34'h10060000
`define GPIO_RANGE 34'h000000FF
`define UART_SUPPORTED 1'b1
`define UART_BASE 34'h10000000
`define UART_RANGE 34'h00000007
`define PLIC_SUPPORTED 1'b1
`define PLIC_BASE 34'h0C000000
`define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b0
`define SDC_BASE 34'h00012100
`define SDC_RANGE 34'h0000001F
// Bus Interface width
`define AHBW 32
// Test modes
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 1
// Hardware configuration
`define UART_PRESCALE 1
// Interrupt configuration
`define PLIC_NUM_SRC 4
// comment out the following if >=32 sources
`define PLIC_NUM_SRC_LT_32
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0

13
pipelined/config/rv64BP/wally-config.vh
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@ -30,8 +30,6 @@
// RV32 or RV64: XLEN = 32 or 64
`define FPGA 0
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
@ -51,11 +49,9 @@
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0
`define MEM_DCACHE 1
`define MEM_IROM 0
`define MEM_ICACHE 1
`define MEM_VIRTMEM 1
`define DMEM `MEM_CACHE
`define IMEM `MEM_CACHE
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
@ -67,7 +63,6 @@
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
@ -134,3 +129,5 @@
//`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE
`define TESTSBP 1
`define REPLAY 0

12
pipelined/config/rv64gc/wally-config.vh
View File

@ -29,8 +29,6 @@
`define FPGA 0
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
@ -50,11 +48,9 @@
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0
`define MEM_DCACHE 1
`define MEM_IROM 0
`define MEM_ICACHE 1
`define MEM_VIRTMEM 1
`define DMEM `MEM_CACHE
`define IMEM `MEM_CACHE
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
@ -66,7 +62,6 @@
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
@ -135,3 +130,4 @@
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define REPLAY 0

22
pipelined/config/rv64ic/wally-config.vh
View File

@ -29,8 +29,6 @@
`define FPGA 0
`define QEMU 0
`define BUILDROOT 0
`define BUSYBEAR 0
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
@ -42,31 +40,28 @@
// MISA RISC-V configuration per specification
`define MISA (32'h00000104)
`define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 0
`define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 1
`define ZICOUNTERS_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0
`define MEM_DCACHE 1
`define MEM_IROM 0
`define MEM_ICACHE 1
`define MEM_VIRTMEM 1
`define DMEM `MEM_TIM
`define IMEM `MEM_TIM
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
`define ITLB_ENTRIES 0
`define DTLB_ENTRIES 0
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
@ -76,7 +71,7 @@
`define DIV_BITSPERCYCLE 4
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64
`define PMP_ENTRIES 0
// Address space
`define RESET_VECTOR 64'h0000000080000000
@ -135,3 +130,4 @@
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define REPLAY 0

4
pipelined/config/shared/wally-constants.vh
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@ -50,3 +50,7 @@
`define SV39 8
`define SV48 9
`define MEM_BUS 1
`define MEM_TIM 2
`define MEM_CACHE 3

31
pipelined/regression/Makefile
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@ -11,29 +11,36 @@ make all:
# *** Build old tests/imperas-riscv-tests for now;
# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
# Also delete bin/exe2memfile at that point
make -C ../../tests/imperas-riscv-tests
make -C ../../tests/imperas-riscv-tests XLEN=64
cd ../../tests/imperas-riscv-tests; exe2memfile.pl work/*/*.elf
make -C ../../tests/imperas-riscv-tests --jobs
make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs
#cd ../../tests/imperas-riscv-tests; exe2memfile.pl work/*/*.elf
#cd ../../tests/imperas-riscv-tests; extractFunctionRadix.sh work/*/*.elf.objdump
# Build riscv-arch-test 64 and 32-bit versions
make -C ../../addins/riscv-arch-test
make -C ../../addins/riscv-arch-test XLEN=32
cd ../../addins/riscv-arch-test; elf2hex.sh
make -C ../../addins/riscv-arch-test --jobs
make -C ../../addins/riscv-arch-test XLEN=32 --jobs
#cd ../../addins/riscv-arch-test; elf2hex.sh
#cd ../../addins/riscv-arch-test; extractFunctionRadix.sh work/*/*/*.elf.objdump
# extractFunctionRadix. ***
# Build wally-riscv-arch-test
make -C ../../tests/wally-riscv-arch-test/
make -C ../../tests/wally-riscv-arch-test/ XLEN=32
cd ../../tests/wally-riscv-arch-test; elf2hex.sh
make -C ../../tests/wally-riscv-arch-test/ --jobs
make -C ../../tests/wally-riscv-arch-test/ XLEN=32 --jobs
# build the memfiles and address files.
make -f makefile-memfile wally-sim-files --jobs
#cd ../../tests/wally-riscv-arch-test; elf2hex.sh
#cd ../../tests/wally-riscv-arch-test; extractFunctionRadix.sh work/*/*/*.elf.objdump
# ***extractFunctionRadix
# Only compile Imperas tests if they are installed locally.
# They are usually a symlink to $RISCV/imperas-riscv-tests and only
# get compiled there manually during installation
# make -C ../../addins/imperas-riscv-tests
# make -C ../../addins/imperas-riscv-tests XLEN=64
# cd ../../addins/imperas-riscv-tests; elf2hex.sh
#make -C ../../addins/imperas-riscv-tests
#make -C ../../addins/imperas-riscv-tests XLEN=64
#cd ../../addins/imperas-riscv-tests; elf2hex.sh
#cd ../../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump
# Link Linux test vectors (fix this later***)
#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh

240
pipelined/regression/fpga-wave.do
View File

@ -178,55 +178,55 @@ add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/i
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/genblk1/cachereplacementpolicy/EncVicWay
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/VictimWay
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/SetValid}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/WriteWordEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/SetValid}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/SetValid}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/DirtyBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/SetValid}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/WriteWordEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/SetValid}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/SetValid}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/DirtyBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/NextState
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/ITLBMissF
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/ITLBWriteF
@ -290,81 +290,81 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipeline
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimDirty
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VDWriteEnableWay
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/WriteWordEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/WriteWordEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetValid
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearValid
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataBlockWayMaskedM
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataWordM

2
pipelined/regression/lint-wally
View File

@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`
basepath=$(dirname $0)/..
for config in rv64gc rv32gc rv32ic; do
for config in rv32e rv64gc rv32gc rv32ic ; do
echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
echo "Exiting after $config lint due to errors or warnings"

148
pipelined/regression/linux-wave.do
View File

@ -226,85 +226,85 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/IgnoreRequest
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteWordEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ClearDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/VDWriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/WriteWordEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/ClearDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/VDWriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetValid
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearValid
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetDirty
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearDirty
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/RAdr
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/ReadDataWord
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag

37
pipelined/regression/makefile-memfile Normal file
View File

@ -0,0 +1,37 @@
ROOT := ../..
SUFFIX := work
ARCHDIR := $(ROOT)/addins/riscv-arch-test
WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test
IMPERASDIR := $(ROOT)/tests/imperas-riscv-tests
ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX)
ELFFILES ?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf")
MEMFILES ?= $(ELFFILES:.elf=.elf.memfile)
ADDRFILES ?= $(ELFFILES:.elf=.elf.objdump.addr)
print:
echo "files in $(ALLDIRS) are $(ELFFILES)."
echo "memfiles are $(MEMFILES)"
.PHONY: all wally-sim-files
all: wally-sim-files
wally-sim-files: $(MEMFILES) $(ADDRFILES)
echo "$@"
# notes to self on how this works.
# The find command locates all of the *.elf files in directory DIR1. A list of .memfiles and
# .addr files are generated from the .elf. These are used as targets.
# % is a wildcard in a make target which is then referenced as % in the depenecies and $*
# in the recipe.
# because elf2hex requires a bit width we use findstring to figure out if the compiled directory
# is XLEN=64 or 32. This is hacky and will likely break in the future.
# the .addr is a separate target so make can split into more jobs and more parallism.
%.elf.memfile: %.elf
riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@
%.elf.objdump.addr: %.elf.objdump
extractFunctionRadix.sh $<
.PHONY: clean
clean:

16
pipelined/regression/regression-wally
View File

@ -48,17 +48,17 @@ def getBuildrootTC(short):
INSTR_LIMIT = 100000 # multiple of 100000
MAX_EXPECTED = 246000000
if short:
BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do "+str(INSTR_LIMIT)+" 1 0\n!"
BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot "+str(INSTR_LIMIT)+" 1 0\n!"
BRgrepstr=str(INSTR_LIMIT)+" instructions"
else:
BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do 0 1 0\n!"
BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot 0 1 0\n!"
BRgrepstr=str(MAX_EXPECTED)+" instructions"
return TestCase(name="buildroot",variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
tc = TestCase(
name="buildroot-checkpoint",
variant="rv6gc",
cmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do 400100000 400000001 400000000\n!",
variant="rv64gc",
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot-checkpoint 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config?
grepstr="400100000 instructions")
configs.append(tc)
@ -88,12 +88,12 @@ for test in tests32ic:
grepstr="All tests ran without failures")
configs.append(tc)
tests32tim = ["arch32i", "arch32c", "imperas32i", "imperas32c"]
for test in tests32tim:
tests32e = ["wally32e"]
for test in tests32e:
tc = TestCase(
name=test,
variant="rv32tim",
cmd="vsim > {} -c <<!\ndo wally-pipelined-tim-batch.do rv32tim "+test+"\n!",
variant="rv32e",
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32e "+test+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)

2
pipelined/regression/sim-buildroot
View File

@ -30,4 +30,4 @@ echo "INSTR_LIMIT = ${INSTR_LIMIT}"
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
echo "CHECKPOINT = ${CHECKPOINT}"
vsim -do "do ./wally-buildroot.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"
vsim -do "do ./wally-pipelined.do buildroot buildroot $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"

8
pipelined/regression/sim-buildroot-batch
View File

@ -30,6 +30,10 @@ echo "INSTR_LIMIT = ${INSTR_LIMIT}"
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
echo "CHECKPOINT = ${CHECKPOINT}"
#vsim -c <<!
#do wally-buildroot-batch.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
#!
# *** change config from buildroot to rv64gc
vsim -c <<!
do wally-buildroot-batch.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
!
do wally-pipelined-batch.do buildroot buildroot $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
!

2
pipelined/regression/sim-wally
View File

@ -1,2 +1,2 @@
vsim -do "do wally-pipelined.do rv32tim arch32i"
vsim -do "do wally-pipelined.do rv32e wally32e"

4
pipelined/regression/sim-wally-batch
View File

@ -1,3 +1 @@
vsim -c <<!
do wally-pipelined-batch.do rv64gc wally64priv
!
vsim -c -do "do wally-pipelined-batch.do rv32e wally32e"

39
pipelined/regression/wally-buildroot-batch.do
View File

@ -1,39 +0,0 @@
# wally-pipelined.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-pipelined.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-pipelined.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work-buildroot] {
vdel -all -lib work-buildroot
}
vlib work-buildroot
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
vlog -lint +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
vopt work.testbench -G INSTR_LIMIT=$1 -G INSTR_WAVEON=$2 -G CHECKPOINT=$3 -o workopt
vsim workopt -suppress 8852,12070
run -all
run -all
exec ./slack-notifier/slack-notifier.py
quit

44
pipelined/regression/wally-buildroot.do
View File

@ -1,44 +0,0 @@
# wally-pipelined.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-pipelined.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-pipelined.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work-buildroot] {
vdel -all -lib work-buildroot
}
vlib work-buildroot
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt +acc work.testbench -G INSTR_LIMIT=$1 -G INSTR_WAVEON=$2 -G CHECKPOINT=$3 -o workopt
vsim workopt -suppress 8852,12070
#-- Run the Simulation
run -all
do linux-wave.do
add log -recursive /*
run -all
exec ./slack-notifier/slack-notifier.py
#quit

32
pipelined/regression/wally-pipelined-batch.do
View File

@ -32,19 +32,31 @@ vlib work_${1}_${2}
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
#vsim -coverage -lib work_$2 workopt_$2
run -all
run -all
exec ./slack-notifier/slack-notifier.py
quit
} else {
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
#vsim -coverage -lib work_$2 workopt_$2
run -all
quit
}
run -all
#coverage report -file wally-pipelined-coverage.txt
# These aren't doing anything helpful
#coverage report -memory
#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
quit

50
pipelined/regression/wally-pipelined-tim-batch.do
View File

@ -1,50 +0,0 @@
# wally-pipelined-batch.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Usage: do wally-pipelined-batch.do <config> <testcases>
# Example: do wally-pipelined-batch.do rv32ic imperas-32i
# Use this wally-pipelined-batch.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-pipelined-batch.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-pipelined-batch.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work_${1}_${2}] {
vdel -lib work_${1}_${2} -all
}
vlib work_${1}_${2}
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-tim.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
#vsim -coverage -lib work_$2 workopt_$2
run -all
#coverage report -file wally-pipelined-coverage.txt
# These aren't doing anything helpful
#coverage report -memory
#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
quit

56
pipelined/regression/wally-pipelined-tim.do
View File

@ -1,56 +0,0 @@
# wally-pipelined.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
# Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-pipelined.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-pipelined.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
#switch $argc {
# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
#}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-tim.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
vopt +acc work.testbench -G TEST=$2 -o workopt
vsim workopt
view wave
-- display input and output signals as hexidecimal values
#do ./wave-dos/peripheral-waves.do
add log -recursive /*
do wave.do
-- Run the Simulation
#run 3600
run -all
#quit
#noview ../testbench/testbench-imperas.sv
noview ../testbench/testbench.sv
view wave

55
pipelined/regression/wally-pipelined.do
View File

@ -29,28 +29,41 @@ vlib work
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
#switch $argc {
# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
#}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
vopt +acc work.testbench -G TEST=$2 -o workopt
vsim workopt
if {$2 eq "buildroot"} {
vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
view wave
-- display input and output signals as hexidecimal values
#do ./wave-dos/peripheral-waves.do
add log -recursive /*
do wave.do
-- Run the Simulation
#run 3600
run -all
#quit
#noview ../testbench/testbench-imperas.sv
noview ../testbench/testbench.sv
view wave
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt +acc work.testbench -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o workopt
vsim workopt -suppress 8852,12070
#-- Run the Simulation
run -all
do linux-wave.do
add log -recursive /*
run -all
exec ./slack-notifier/slack-notifier.py
} else {
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
vsim workopt +nowarn3829
view wave
#-- display input and output signals as hexidecimal values
#do ./wave-dos/peripheral-waves.do
add log -recursive /*
do wave.do
#-- Run the Simulation
#run 3600
run -all
noview ../testbench/testbench.sv
view wave
}

166
pipelined/regression/wave-coremark.do
View File

@ -178,18 +178,18 @@ add wave -noupdate -group icache -color Gold /testbench/dut/core/ifu/bus/icache/
add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/BasePAdrF
add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/WayHit
add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/VictimWay
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/SetValid}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/ifu/bus/icache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/ValidBits}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/SetValid}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/CacheTagMem/StoredData}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/ValidBits}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/controller/NextState
add wave -noupdate -group icache /testbench/dut/core/ifu/ITLBMissF
add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/ITLBWriteF
@ -245,81 +245,81 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SelAdrM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/ReadDataBlockM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/DCacheMemWriteData
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/WriteWordEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WriteWordEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetValid
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearValid
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataBlockWayMaskedM
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordM

246
pipelined/regression/wave.do
View File

@ -1,9 +1,9 @@
onerror {resume}
quietly virtual function -install /testbench/dut/core/ifu -env /testbench/dut/core/ifu { &{/testbench/dut/core/ifu/BPPredWrongM, /testbench/dut/core/ifu/InvalidateICacheM }} temp
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset
add wave -noupdate /testbench/reset_ext
add wave -noupdate /testbench/memfilename
add wave -noupdate /testbench/dut/core/SATP_REGW
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
@ -55,6 +55,7 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
@ -118,10 +119,7 @@ add wave -noupdate -group PCS /testbench/PCW
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredPCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/SelBPPredF
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM
add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
@ -193,129 +191,129 @@ add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu.bus.dcache/dcache/cachefsm/CurrState
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMLineWriteEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWordWriteEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWayWriteEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWordEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMLineWayWriteEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SelAdr
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMLineWriteEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMWordWriteEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMWayWriteEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMWordEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMLineWayWriteEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/SelReplayCPURequest
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/RAdr
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/RAdrD}
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ClearDirty}
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ClearDirtyD}
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu.bus.dcache/dcache/FlushAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/FlushWay
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirtyWay
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD}
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirty}
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyD}
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu.bus.dcache/dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteWordEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ClearDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/VDWriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetValid
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearValid
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/RAdr
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/ReadDataWord
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimWay
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirtyWay
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/RW
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/NextAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/PAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/Atomic
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/FlushCache
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheStall
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WriteWordEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearDirty}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/VDWriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu.bus.dcache/dcache/CacheHit
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheFetchLine
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheWriteLine
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheBusAck
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/FlushWay
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
@ -437,7 +435,7 @@ add wave -noupdate /testbench/dut/core/priv/priv/csr/MEPC_REGW
add wave -noupdate /testbench/dut/core/lsu/bus/busdp/LocalLSUBusAdr
add wave -noupdate /testbench/dut/core/lsu/bus/busdp/busfsm/DCacheFetchLine
add wave -noupdate /testbench/dut/core/lsu/bus/busdp/busfsm/DCacheWriteLine
add wave -noupdate -expand -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
add wave -noupdate -expand -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusRead
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAdr
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAck
@ -478,7 +476,7 @@ add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -
add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 7} {3836 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1}
WaveRestoreCursors {{Cursor 7} {6451242 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1}
quietly wave cursor active 1
configure wave -namecolwidth 250
configure wave -valuecolwidth 314
@ -494,4 +492,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {3733 ns} {4093 ns}
WaveRestoreZoom {593782 ns} {7438712 ns}

307
pipelined/src/cache/cache.sv vendored
View File

@ -28,234 +28,189 @@
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module cache #(parameter integer LINELEN,
parameter integer NUMLINES,
parameter integer NUMWAYS,
parameter integer DCACHE = 1)
(input logic clk,
input logic reset,
module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
input logic clk,
input logic reset,
// cpu side
input logic CPUBusy,
input logic [1:0] RW,
input logic [1:0] Atomic,
input logic FlushCache,
input logic InvalidateCacheM,
input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] PAdr, // physical address
input logic [`XLEN-1:0] FinalWriteData,
output logic [`XLEN-1:0] ReadDataWord,
output logic CacheCommitted,
output logic CacheStall,
input logic CPUBusy,
input logic [1:0] RW,
input logic [1:0] Atomic,
input logic FlushCache,
input logic InvalidateCacheM,
input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] PAdr, // physical address
input logic [`XLEN-1:0] FinalWriteData,
output logic CacheCommitted,
output logic CacheStall,
// to performance counters to cpu
output logic CacheMiss,
output logic CacheAccess,
output logic CacheMiss,
output logic CacheAccess,
output logic save, restore,
// lsu control
input logic IgnoreRequest,
input logic IgnoreRequest,
// Bus fsm interface
output logic CacheFetchLine,
output logic CacheWriteLine,
input logic CacheBusAck,
output logic CacheFetchLine,
output logic CacheWriteLine,
input logic CacheBusAck,
output logic [`PA_BITS-1:0] CacheBusAdr,
input logic [LINELEN-1:0] CacheMemWriteData,
output logic [LINELEN-1:0] ReadDataLine);
output logic [`PA_BITS-1:0] CacheBusAdr,
input logic [LINELEN-1:0] CacheMemWriteData,
output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0]);
localparam integer LINEBYTELEN = LINELEN/8;
localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
localparam integer INDEXLEN = $clog2(NUMLINES);
localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
localparam integer WORDSPERLINE = LINELEN/`XLEN;
localparam integer LOGWPL = $clog2(WORDSPERLINE);
localparam integer LOGXLENBYTES = $clog2(`XLEN/8);
localparam integer FlushAdrThreshold = NUMLINES - 1;
// Cache parameters
localparam LINEBYTELEN = LINELEN/8;
localparam OFFSETLEN = $clog2(LINEBYTELEN);
localparam SETLEN = $clog2(NUMLINES);
localparam SETTOP = SETLEN+OFFSETLEN;
localparam TAGLEN = `PA_BITS - SETTOP;
localparam WORDSPERLINE = LINELEN/`XLEN;
localparam LOGWPL = $clog2(WORDSPERLINE);
localparam LOGXLENBYTES = $clog2(`XLEN/8);
localparam FlushAdrThreshold = NUMLINES - 1;
logic [1:0] SelAdr;
logic [INDEXLEN-1:0] RAdr;
logic [SETLEN-1:0] RAdr;
logic [LINELEN-1:0] SRAMWriteData;
logic SetValid, ClearValid;
logic SetDirty, ClearDirty;
logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
logic [NUMWAYS-1:0] WayHit;
logic CacheHit;
logic [LINELEN-1:0] ReadDataLine;
logic [WORDSPERLINE-1:0] SRAMWordEnable;
logic SRAMWordWriteEnable;
logic SRAMLineWriteEnable;
logic [NUMWAYS-1:0] SRAMLineWayWriteEnable;
logic [NUMWAYS-1:0] SRAMWayWriteEnable;
logic [NUMWAYS-1:0] SRAMWordWayWriteEnable;
logic [NUMWAYS-1:0] VictimWay;
logic [NUMWAYS-1:0] VictimDirtyWay;
logic VictimDirty;
logic [2**LOGWPL-1:0] MemPAdrDecoded;
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
logic [TAGLEN-1:0] VictimTag;
logic [INDEXLEN-1:0] FlushAdr;
logic [INDEXLEN-1:0] FlushAdrP1;
logic [SETLEN-1:0] FlushAdr;
logic [SETLEN-1:0] FlushAdrP1;
logic FlushAdrCntEn;
logic FlushAdrCntRst;
logic FlushAdrFlag;
logic FlushWayFlag;
logic FlushWayFlag;
logic [NUMWAYS-1:0] FlushWay;
logic [NUMWAYS-1:0] NextFlushWay;
logic FlushWayCntEn;
logic FlushWayCntRst;
logic VDWriteEnable;
logic SelEvict;
logic LRUWriteEn;
logic [NUMWAYS-1:0] VDWriteEnableWay;
logic SelFlush;
logic ResetOrFlushAdr, ResetOrFlushWay;
logic [NUMWAYS-1:0] WayHitSaved, WayHitRaw;
logic [LINELEN-1:0] ReadDataLineRaw, ReadDataLineSaved;
logic [NUMWAYS-1:0] SelectedWay;
logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
/////////////////////////////////////////////////////////////////////////////////////////////
// Read Path
/////////////////////////////////////////////////////////////////////////////////////////////
// Read Path CPU (IEU) side
mux3 #(INDEXLEN)
AdrSelMux(.d0(NextAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d1(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d2(FlushAdr),
.s(SelAdr),
.y(RAdr));
cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN),
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
.PAdr(PAdr),
.WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable(VDWriteEnableWay),
.WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMLineWayWriteEnable),
.WriteData(SRAMWriteData),
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
.VictimWay, .FlushWay, .SelFlush,
.ReadDataLineWayMasked,
.WayHit, .VictimDirtyWay, .VictimTagWay,
.InvalidateAll(InvalidateCacheM));
// Choose read address (RAdr). Normally use NextAdr, but use PAdr during stalls
// and FlushAdr when handling D$ flushes
mux3 #(SETLEN) AdrSelMux(
.d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr),
.s(SelAdr), .y(RAdr));
// Array of cache ways, along with victim, hit, dirty, and read merging logic
cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](
.clk, .reset, .RAdr, .PAdr,
.SRAMWayWriteEnable,
.SRAMWordEnable,
.TagWriteEnable(SRAMLineWayWriteEnable),
.WriteData(SRAMWriteData),
.SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay),
.SelEvict, .Victim(VictimWay), .Flush(FlushWay),
.SelFlush,
.SelectedReadDataLine(ReadDataLineWay), .WayHit(WayHitRaw), .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay),
.InvalidateAll(InvalidateCacheM));
if(NUMWAYS > 1) begin:vict
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
cachereplacementpolicy(.clk, .reset,
.WayHit,
.VictimWay,
.PAdr(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.RAdr,
.LRUWriteEn);
end else begin:vict
assign VictimWay = 1'b1; // one hot.
end
cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
.clk, .reset, .WayHit, .VictimWay, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .RAdr, .LRUWriteEn);
end else assign VictimWay = 1'b1; // one hot.
assign CacheHit = | WayHit;
assign VictimDirty = | VictimDirtyWay;
// ReadDataLineWayMaskedM is a 2d array of cache line len by number of ways.
// ReadDataLineWay is a 2d array of cache line len by number of ways.
// Need to OR together each way in a bitwise manner.
// Final part of the AO Mux. First is the AND in the cacheway.
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLine));
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine));
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
// easily build a variable input mux.
genvar index;
if(DCACHE == 1) begin: readdata
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
assign ReadDataLineSets[index] = ReadDataLine[((index+1)*`XLEN)-1: (index*`XLEN)];
end
// variable input mux
assign ReadDataWord = ReadDataLineSets[PAdr[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
end else begin: readdata
logic [31:0] ReadLineSetsF [LINELEN/16-1:0];
logic [31:0] FinalInstrRawF;
for(index = 0; index < LINELEN / 16 - 1; index++)
assign ReadLineSetsF[index] = ReadDataLine[((index+1)*16)+16-1 : (index*16)];
assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadDataLine[LINELEN-1:LINELEN-16]};
assign FinalInstrRawF = ReadLineSetsF[PAdr[$clog2(LINELEN / 32) + 1 : 1]];
if (`XLEN == 64) assign ReadDataWord = {32'b0, FinalInstrRawF};
else assign ReadDataWord = FinalInstrRawF;
end
// Write Path CPU (IEU) side
onehotdecoder #(LOGWPL)
adrdec(.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
.decoded(MemPAdrDecoded));
assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded;
// Because of the sram clocked read when the ieu is stalled the read data maybe lost.
// There are two ways to resolve. 1. We can replay the read of the sram or we can save
// the data. Replay is eaiser but creates a longer critical path.
// save/restore only wayhit and readdata.
if(!`REPLAY) begin
flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHitRaw, WayHitSaved);
mux2 #(NUMWAYS) saverestoremux(WayHitRaw, WayHitSaved, restore, WayHit);
end else assign WayHit = WayHitRaw;
assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0;
/////////////////////////////////////////////////////////////////////////////////////////////
// Write Path: Write Enables
/////////////////////////////////////////////////////////////////////////////////////////////
// *** Ross considering restructuring
// move decoder and wordwritenable into cacheway.
onehotdecoder #(LOGWPL) adrdec(
.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded; // OR
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnable ? WayHit : '0),
.d1(VictimWay),
.s(SRAMLineWriteEnable),
.y(SRAMWayWriteEnable));
assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0; // AND
assign SRAMWordWayWriteEnable = SRAMWordWriteEnable ? WayHit : '0; // AND
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWayWriteEnable), .d1(VictimWay),
.s(SRAMLineWriteEnable), .y(SRAMWayWriteEnable));
mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
.d1(CacheMemWriteData),
.s(SRAMLineWriteEnable),
.y(SRAMWriteData));
.d1(CacheMemWriteData), .s(SRAMLineWriteEnable), .y(SRAMWriteData));
mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
.s({SelFlush, SelEvict}),
.y(CacheBusAdr));
mux3 #(`PA_BITS) BaseAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d1({VictimTag, PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
.s({SelFlush, SelEvict}),
.y(CacheBusAdr));
/////////////////////////////////////////////////////////////////////////////////////////////
// Flush address and way generation during flush
/////////////////////////////////////////////////////////////////////////////////////////////
// flush address and way generation.
// increment on 2nd to last way
flopenr #(INDEXLEN)
FlushAdrReg(.clk,
.reset(reset | FlushAdrCntRst),
.en(FlushAdrCntEn),
.d(FlushAdrP1),
.q(FlushAdr));
assign ResetOrFlushAdr = reset | FlushAdrCntRst;
flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr),
.en(FlushAdrCntEn), .d(FlushAdrP1), .q(FlushAdr));
assign FlushAdrP1 = FlushAdr + 1'b1;
assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]);
flopenl #(NUMWAYS)
FlushWayReg(.clk,
.load(reset | FlushWayCntRst),
.en(FlushWayCntEn),
.val({{NUMWAYS-1{1'b0}}, 1'b1}),
.d(NextFlushWay),
.q(FlushWay));
assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};
assign ResetOrFlushWay = reset | FlushWayCntRst;
flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay),
.en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}),
.d(NextFlushWay), .q(FlushWay));
assign FlushWayFlag = FlushWay[NUMWAYS-1];
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
//assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0];
assign FlushWayFlag = FlushWay[NUMWAYS-1];
cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
.RW, .Atomic, .CPUBusy, .IgnoreRequest,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr, .SetValid,
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable,
.SRAMLineWriteEnable, .SelEvict, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
.VDWriteEnable, .LRUWriteEn);
assign SelectedWay = SelFlush ? FlushWay : (SRAMLineWriteEnable ? VictimWay : WayHit);
assign SetValidWay = SetValid ? SelectedWay : '0;
assign ClearValidWay = ClearValid ? SelectedWay : '0;
assign SetDirtyWay = SetDirty ? SelectedWay : '0;
assign ClearDirtyWay = ClearDirty ? SelectedWay : '0;
endmodule // dcache
/////////////////////////////////////////////////////////////////////////////////////////////
// Cache FSM
/////////////////////////////////////////////////////////////////////////////////////////////
cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
.RW, .Atomic, .CPUBusy, .IgnoreRequest,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr, .SetValid,
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable,
.SRAMLineWriteEnable, .SelEvict, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
.save, .restore,
.LRUWriteEn);
endmodule

490
pipelined/src/cache/cachefsm.sv vendored
View File

@ -32,56 +32,58 @@
module cachefsm
(input logic clk,
input logic reset,
input logic reset,
// inputs from IEU
input logic [1:0] RW,
input logic [1:0] Atomic,
input logic FlushCache,
input logic FlushCache,
// hazard inputs
input logic CPUBusy,
input logic CPUBusy,
// interlock fsm
input logic IgnoreRequest,
input logic IgnoreRequest,
// Bus inputs
input logic CacheBusAck,
input logic CacheBusAck,
// dcache internals
input logic CacheHit,
input logic VictimDirty,
input logic FlushAdrFlag,
input logic FlushWayFlag,
input logic CacheHit,
input logic VictimDirty,
input logic FlushAdrFlag,
input logic FlushWayFlag,
// hazard outputs
output logic CacheStall,
output logic CacheStall,
// counter outputs
output logic CacheMiss,
output logic CacheAccess,
output logic CacheMiss,
output logic CacheAccess,
// Bus outputs
output logic CacheCommitted,
output logic CacheWriteLine,
output logic CacheFetchLine,
output logic CacheCommitted,
output logic CacheWriteLine,
output logic CacheFetchLine,
// dcache internals
output logic [1:0] SelAdr,
output logic SetValid,
output logic ClearValid,
output logic SetDirty,
output logic ClearDirty,
output logic SRAMWordWriteEnable,
output logic SRAMLineWriteEnable,
output logic SelEvict,
output logic LRUWriteEn,
output logic SelFlush,
output logic FlushAdrCntEn,
output logic FlushWayCntEn,
output logic FlushAdrCntRst,
output logic FlushWayCntRst,
output logic VDWriteEnable
);
output logic SetValid,
output logic ClearValid,
output logic SetDirty,
output logic ClearDirty,
output logic SRAMWordWriteEnable,
output logic SRAMLineWriteEnable,
output logic SelEvict,
output logic LRUWriteEn,
output logic SelFlush,
output logic FlushAdrCntEn,
output logic FlushWayCntEn,
output logic FlushAdrCntRst,
output logic FlushWayCntRst,
output logic save,
output logic restore);
logic AnyCPUReqM;
logic [1:0] PreSelAdr;
logic resetDelay;
logic DoAMO, DoRead, DoWrite, DoFlush;
logic DoAMOHit, DoReadHit, DoWriteHit;
logic DoAMOMiss, DoReadMiss, DoWriteMiss;
logic FlushFlag;
typedef enum {STATE_READY,
STATE_MISS_FETCH_WDV,
@ -103,11 +105,22 @@ module cachefsm
(* mark_debug = "true" *) statetype CurrState, NextState;
assign AnyCPUReqM = |RW | (|Atomic);
assign DoFlush = FlushCache & ~IgnoreRequest;
assign DoAMO = Atomic[1] & (&RW) & ~IgnoreRequest;
assign DoAMOHit = DoAMO & CacheHit;
assign DoAMOMiss = DoAMOHit & ~CacheHit;
assign DoRead = RW[1] & ~IgnoreRequest;
assign DoReadHit = DoRead & CacheHit;
assign DoReadMiss = DoRead & ~CacheHit;
assign DoWrite = RW[0] & ~IgnoreRequest;
assign DoWriteHit = DoWrite & CacheHit;
assign DoWriteMiss = DoWrite & ~CacheHit;
assign FlushFlag = FlushAdrFlag & FlushWayFlag;
// outputs for the performance counters.
assign CacheAccess = AnyCPUReqM & CurrState == STATE_READY;
assign CacheMiss = CacheAccess & ~CacheHit;
assign CacheAccess = (DoAMO | DoRead | DoWrite) & CurrState == STATE_READY;
assign CacheMiss = CacheAccess & ~CacheHit;
// special case on reset. When the fsm first exists reset the
// PCNextF will no longer be pointing to the correct address.
@ -119,316 +132,113 @@ module cachefsm
if (reset) CurrState <= #1 STATE_READY;
else CurrState <= #1 NextState;
// next state logic and some state ouputs.
always_comb begin
CacheStall = 1'b0;
PreSelAdr = 2'b00;
SetValid = 1'b0;
ClearValid = 1'b0;
SetDirty = 1'b0;
ClearDirty = 1'b0;
SRAMWordWriteEnable = 1'b0;
SRAMLineWriteEnable = 1'b0;
SelEvict = 1'b0;
LRUWriteEn = 1'b0;
SelFlush = 1'b0;
FlushAdrCntEn = 1'b0;
FlushWayCntEn = 1'b0;
FlushAdrCntRst = 1'b0;
FlushWayCntRst = 1'b0;
VDWriteEnable = 1'b0;
NextState = STATE_READY;
CacheFetchLine = 1'b0;
CacheWriteLine = 1'b0;
case (CurrState)
STATE_READY: begin
CacheStall = 1'b0;
PreSelAdr = 2'b00;
SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
// TLB Miss
if(IgnoreRequest) begin
// the LSU arbiter has not yet selected the PTW.
// The CPU needs to be stalled until that happens.
// If we set CacheStall for 1 cycle before going to
// PTW ready the CPU will stall.
// The page table walker asserts it's control 1 cycle
// after the TLBs miss.
PreSelAdr = 2'b01;
NextState = STATE_READY;
end
// Flush dcache to next level of memory
else if(FlushCache) begin
NextState = STATE_FLUSH;
FlushAdrCntRst = 1'b1;
FlushWayCntRst = 1'b1;
CacheStall = 1'b1;
end
// amo hit
else if(Atomic[1] & (&RW) & CacheHit) begin
PreSelAdr = 2'b01;
CacheStall = 1'b0;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
PreSelAdr = 2'b01;
end
else begin
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
end
end
// read hit valid cached
else if(RW[1] & CacheHit) begin
CacheStall = 1'b0;
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
// write hit valid cached
else if (RW[0] & CacheHit) begin
PreSelAdr = 2'b01;
CacheStall = 1'b0;
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
// read or write miss valid cached
else if((|RW) & ~CacheHit) begin
NextState = STATE_MISS_FETCH_WDV;
CacheStall = 1'b1;
CacheFetchLine = 1'b1;
end
else NextState = STATE_READY;
end
STATE_MISS_FETCH_WDV: begin
CacheStall = 1'b1;
PreSelAdr = 2'b01;
if (CacheBusAck) begin
NextState = STATE_MISS_FETCH_DONE;
end else begin
NextState = STATE_MISS_FETCH_WDV;
end
end
STATE_MISS_FETCH_DONE: begin
CacheStall = 1'b1;
PreSelAdr = 2'b01;
if(VictimDirty) begin
NextState = STATE_MISS_EVICT_DIRTY;
CacheWriteLine = 1'b1;
end else begin
NextState = STATE_MISS_WRITE_CACHE_LINE;
end
end
STATE_MISS_WRITE_CACHE_LINE: begin
SRAMLineWriteEnable = 1'b1;
CacheStall = 1'b1;
NextState = STATE_MISS_READ_WORD;
PreSelAdr = 2'b01;
SetValid = 1'b1;
ClearDirty = 1'b1;
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
end
STATE_MISS_READ_WORD: begin
PreSelAdr = 2'b01;
CacheStall = 1'b1;
if (RW[0] & ~Atomic[1]) begin // handles stores and amo write.
NextState = STATE_MISS_WRITE_WORD;
end else begin
NextState = STATE_MISS_READ_WORD_DELAY;
// delay state is required as the read signal RW[1] is still high when we
// return to the ready state because the cache is stalling the cpu.
end
end
STATE_MISS_READ_WORD_DELAY: begin
//PreSelAdr = 2'b01;
SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
if(&RW & Atomic[1]) begin // amo write
PreSelAdr = 2'b01;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
end
else begin
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
end
end else begin
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
end
STATE_MISS_WRITE_WORD: begin
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
PreSelAdr = 2'b01;
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
STATE_MISS_EVICT_DIRTY: begin
CacheStall = 1'b1;
PreSelAdr = 2'b01;
SelEvict = 1'b1;
if(CacheBusAck) begin
NextState = STATE_MISS_WRITE_CACHE_LINE;
end else begin
NextState = STATE_MISS_EVICT_DIRTY;
end
end
STATE_CPU_BUSY: begin
PreSelAdr = 2'b00;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
STATE_CPU_BUSY_FINISH_AMO: begin
PreSelAdr = 2'b01;
SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
end
else begin
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
end
end
STATE_FLUSH: begin
// intialize flush counters
SelFlush = 1'b1;
CacheStall = 1'b1;
PreSelAdr = 2'b10;
NextState = STATE_FLUSH_CHECK;
end
STATE_FLUSH_CHECK: begin
CacheStall = 1'b1;
PreSelAdr = 2'b10;
SelFlush = 1'b1;
if(VictimDirty) begin
NextState = STATE_FLUSH_WRITE_BACK;
FlushWayCntEn = 1'b0;
CacheWriteLine = 1'b1;
end else if (FlushAdrFlag & FlushWayFlag) begin
NextState = STATE_READY;
CacheStall = 1'b0;
PreSelAdr = 2'b00;
FlushWayCntEn = 1'b0;
end else if(FlushWayFlag) begin
NextState = STATE_FLUSH_INCR;
FlushAdrCntEn = 1'b1;
FlushWayCntEn = 1'b1;
end else begin
FlushWayCntEn = 1'b1;
NextState = STATE_FLUSH_CHECK;
end
end
STATE_FLUSH_INCR: begin
CacheStall = 1'b1;
PreSelAdr = 2'b10;
SelFlush = 1'b1;
FlushWayCntRst = 1'b1;
NextState = STATE_FLUSH_CHECK;
end
STATE_FLUSH_WRITE_BACK: begin
CacheStall = 1'b1;
PreSelAdr = 2'b10;
SelFlush = 1'b1;
if(CacheBusAck) begin
NextState = STATE_FLUSH_CLEAR_DIRTY;
end else begin
NextState = STATE_FLUSH_WRITE_BACK;
end
end
STATE_FLUSH_CLEAR_DIRTY: begin
CacheStall = 1'b1;
ClearDirty = 1'b1;
VDWriteEnable = 1'b1;
SelFlush = 1'b1;
PreSelAdr = 2'b10;
FlushWayCntEn = 1'b0;
if(FlushAdrFlag & FlushWayFlag) begin
NextState = STATE_READY;
CacheStall = 1'b0;
PreSelAdr = 2'b00;
end else if (FlushWayFlag) begin
NextState = STATE_FLUSH_INCR;
FlushAdrCntEn = 1'b1;
FlushWayCntEn = 1'b1;
end else begin
NextState = STATE_FLUSH_CHECK;
FlushWayCntEn = 1'b1;
end
end
default: begin
NextState = STATE_READY;
end
STATE_READY: if(DoFlush) NextState = STATE_FLUSH;
else if(DoAMOHit & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO;
else if(DoReadHit & CPUBusy) NextState = STATE_CPU_BUSY;
else if (DoWriteHit & CPUBusy) NextState = STATE_CPU_BUSY;
else if(DoReadMiss | DoWriteMiss | DoAMOMiss) NextState = STATE_MISS_FETCH_WDV;
else NextState = STATE_READY;
STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE;
else NextState = STATE_MISS_FETCH_WDV;
STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
else NextState = STATE_MISS_WRITE_CACHE_LINE;
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD;
STATE_MISS_READ_WORD: if (DoWrite & ~DoAMO) NextState = STATE_MISS_WRITE_WORD;
else NextState = STATE_MISS_READ_WORD_DELAY;
STATE_MISS_READ_WORD_DELAY: if(DoAMO & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO;
else if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
else NextState = STATE_MISS_EVICT_DIRTY;
STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
STATE_CPU_BUSY_FINISH_AMO: if(CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO;
else NextState = STATE_READY;
STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK;
else if (FlushFlag) NextState = STATE_READY;
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
else NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY;
else NextState = STATE_FLUSH_WRITE_BACK;
STATE_FLUSH_CLEAR_DIRTY: if(FlushAdrFlag & FlushWayFlag) NextState = STATE_READY;
else if (FlushWayFlag) NextState = STATE_FLUSH_INCR;
else NextState = STATE_FLUSH_CHECK;
default: NextState = STATE_READY;
endcase
end
assign CacheCommitted = CurrState != STATE_READY;
assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) |
(CurrState == STATE_MISS_FETCH_WDV) |
(CurrState == STATE_MISS_FETCH_DONE) |
(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
(CurrState == STATE_MISS_READ_WORD) |
(CurrState == STATE_MISS_EVICT_DIRTY) |
(CurrState == STATE_FLUSH) |
(CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) |
(CurrState == STATE_FLUSH_INCR) |
(CurrState == STATE_FLUSH_WRITE_BACK) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
assign ClearValid = '0;
assign SetDirty = (CurrState == STATE_READY & DoAMO) |
(CurrState == STATE_READY & DoWrite) |
(CurrState == STATE_MISS_READ_WORD_DELAY & DoAMO) |
(CurrState == STATE_MISS_WRITE_WORD);
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
assign SRAMWordWriteEnable = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) |
(CurrState == STATE_MISS_READ_WORD_DELAY & DoAMO) |
(CurrState == STATE_MISS_WRITE_WORD);
assign SRAMLineWriteEnable = (CurrState == STATE_MISS_WRITE_CACHE_LINE);
assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY);
assign LRUWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit)) |
(CurrState == STATE_MISS_READ_WORD_DELAY) |
(CurrState == STATE_MISS_WRITE_WORD);
assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayFlag & ~FlushAdrFlag) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayFlag & ~FlushAdrFlag);
assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
assign FlushAdrCntRst = (CurrState == STATE_READY & DoFlush);
assign FlushWayCntRst = (CurrState == STATE_READY & DoFlush) | (CurrState == STATE_FLUSH_INCR);
assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss));
assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) |
(CurrState == STATE_FLUSH_CHECK & VictimDirty);
assign restore = ((CurrState == STATE_CPU_BUSY) | (CurrState == STATE_CPU_BUSY_FINISH_AMO)) & ~`REPLAY;
assign save = ((CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit) & CPUBusy) |
(CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | DoRead) & CPUBusy) |
(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
// **** can this be simplified?
assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequest) |
(CurrState == STATE_READY & DoAMOHit) |
(CurrState == STATE_READY & DoReadHit & (CPUBusy & `REPLAY)) |
(CurrState == STATE_READY & DoWriteHit) |
(CurrState == STATE_MISS_FETCH_WDV) |
(CurrState == STATE_MISS_FETCH_DONE) |
(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
(CurrState == STATE_MISS_READ_WORD) |
(CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | (CPUBusy & `REPLAY))) |
(CurrState == STATE_MISS_WRITE_WORD) |
(CurrState == STATE_MISS_EVICT_DIRTY) |
(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |
(CurrState == STATE_CPU_BUSY_FINISH_AMO)) ? 2'b01 :
((CurrState == STATE_FLUSH) |
(CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) |
(CurrState == STATE_FLUSH_INCR) |
(CurrState == STATE_FLUSH_WRITE_BACK) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag))) ? 2'b10 :
2'b00;
endmodule // cachefsm

103
pipelined/src/cache/cachereplacementpolicy.sv vendored
View File

@ -39,9 +39,6 @@ module cachereplacementpolicy
input logic LRUWriteEn
);
// *** Only implements 2, 4, and 8 way
// I would like parametersize this in the future.
logic [NUMWAYS-2:0] LRUEn, LRUMask;
logic [$clog2(NUMWAYS)-1:0] EncVicWay;
logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0];
@ -52,56 +49,38 @@ module cachereplacementpolicy
logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] PAdrD;
logic [INDEXLEN-1:0] RAdrD;
logic LRUWriteEnD;
/* verilator lint_off BLKLOOPINIT */
always_ff @(posedge clk) begin
if (reset) begin
RAdrD <= '0;
PAdrD <= '0;
LRUWriteEnD <= 0;
NewReplacementD <= '0;
for(int index = 0; index < NUMLINES; index++)
ReplacementBits[index] <= '0;
end else begin
RAdrD <= RAdr;
PAdrD <= PAdr;
LRUWriteEnD <= LRUWriteEn;
NewReplacementD <= NewReplacement;
if (LRUWriteEnD) begin
ReplacementBits[PAdrD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD;
end
end
end
/* verilator lint_on BLKLOOPINIT */
initial begin
assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported");
end
// Pipeline Delay Registers
flopr #(INDEXLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD);
flopr #(INDEXLEN) PAdrDelayReg(clk, reset, PAdr, PAdrD);
flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD);
flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD);
// Replacement Bits: Register file
// Needs to be resettable for simulation, but could omit reset for synthesis ***
always_ff @(posedge clk)
if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0;
else if (LRUWriteEnD) ReplacementBits[PAdrD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacementD;
assign LineReplacementBits = ReplacementBits[RAdrD];
genvar index;
if(NUMWAYS == 2) begin : TwoWay
if(NUMWAYS == 2) begin : PseudoLRU
assign LRUEn[0] = 1'b0;
assign NewReplacement[0] = WayHit[1];
assign VictimWay[1] = ~LineReplacementBits[0];
assign VictimWay[0] = LineReplacementBits[0];
end else if (NUMWAYS == 4) begin : FourWay
// VictimWay is a function only of the current value of the LRU.
// binary encoding
//assign VictimWay[0] = LineReplacementBits[2] ? LineReplacementBits[1] : LineReplacementBits[0];
//assign VictimWay[1] = LineReplacementBits[2];
// 1 hot encoding
//| WayHit | LRU 2 | LRU 1 | LRU 0 |
//|--------+-------+-------+-------|
//| 0000 | - | - | - |
//| 0001 | 1 | - | 1 |
//| 0010 | 1 | - | 0 |
//| 0100 | 0 | 1 | - |
//| 1000 | 0 | 0 | - |
end else if (NUMWAYS == 4) begin : PseudoLRU
// 1 hot encoding for VictimWay; LRU = LineReplacementBits
//| LRU 2 | LRU 1 | LRU 0 | VictimWay
//+-------+-------+-------+-----------
//| 1 | - | 1 | 0001
//| 1 | - | 0 | 0010
//| 0 | 1 | - | 0100
//| 0 | 0 | - | 1000
assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0];
assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0];
@ -117,33 +96,11 @@ module cachereplacementpolicy
assign LRUMask[2] = WayHit[1] | WayHit[0];
assign LRUMask[1] = WayHit[2];
assign LRUMask[0] = WayHit[0];
/* -----\/----- EXCLUDED -----\/-----
// selects
assign LRUEn[2] = 1'b1;
assign LRUEn[1] = WayHit[3];
assign LRUEn[0] = WayHit[3] | WayHit[2];
// mask
assign LRUMask[0] = WayHit[1];
assign LRUMask[1] = WayHit[3];
assign LRUMask[2] = WayHit[3] | WayHit[2];
-----/\----- EXCLUDED -----/\----- */
for(index = 0; index < NUMWAYS-1; index++)
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
/* -----\/----- EXCLUDED -----\/-----
assign EncVicWay[1] = LineReplacementBits[2];
assign EncVicWay[0] = LineReplacementBits[2] ? LineReplacementBits[0] : LineReplacementBits[1];
onehotdecoder #(2)
waydec(.bin(EncVicWay),
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
-----/\----- EXCLUDED -----/\----- */
end else if (NUMWAYS == 8) begin : EightWay
mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, LRUMask, LRUEn, NewReplacement);
end
/* *** 8-way not yet working - look for a general way to write this for all NUMWAYS
else if (NUMWAYS == 8) begin : PseudoLRU
// selects
assign LRUEn[6] = 1'b1;
@ -164,7 +121,7 @@ assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBi
assign LRUMask[0] = WayHit[0];
for(index = 0; index < NUMWAYS-1; index++)
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
assign EncVicWay[2] = LineReplacementBits[6];
assign EncVicWay[1] = LineReplacementBits[6] ? LineReplacementBits[5] : LineReplacementBits[2];
@ -176,7 +133,7 @@ assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBi
waydec(.bin(EncVicWay),
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
end
end */
endmodule

161
pipelined/src/cache/cacheway.sv vendored
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@ -1,5 +1,5 @@
///////////////////////////////////////////
// DCacheMem (Memory for the Data Cache)
// cacheway
//
// Written: ross1728@gmail.com July 07, 2021
// Implements the data, tag, valid, dirty, and replacement bits.
@ -31,117 +31,106 @@
`include "wally-config.vh"
module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1)
(input logic clk,
input logic reset,
parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (
input logic clk,
input logic reset,
input logic [$clog2(NUMLINES)-1:0] RAdr,
input logic [`PA_BITS-1:0] PAdr,
input logic WriteEnable,
input logic VDWriteEnable,
input logic [LINELEN/`XLEN-1:0] WriteWordEnable,
input logic TagWriteEnable,
input logic [LINELEN-1:0] WriteData,
input logic SetValid,
input logic ClearValid,
input logic SetDirty,
input logic ClearDirty,
input logic SelEvict,
input logic VictimWay,
input logic InvalidateAll,
input logic SelFlush,
input logic FlushWay,
input logic [$clog2(NUMLINES)-1:0] RAdr,
input logic [`PA_BITS-1:0] PAdr,
input logic SRAMWayWriteEnable,
input logic [LINELEN/`XLEN-1:0] SRAMWordEnable,
input logic TagWriteEnable,
input logic [LINELEN-1:0] WriteData,
input logic SetValid,
input logic ClearValid,
input logic SetDirty,
input logic ClearDirty,
input logic SelEvict,
input logic Victim,
input logic InvalidateAll,
input logic SelFlush,
input logic Flush,
output logic [LINELEN-1:0] ReadDataLineWayMasked,
output logic WayHit,
output logic VictimDirtyWay,
output logic [TAGLEN-1:0] VictimTagWay
);
output logic [LINELEN-1:0] SelectedReadDataLine,
output logic WayHit,
output logic VictimDirty,
output logic [TAGLEN-1:0] VictimTag);
logic [NUMLINES-1:0] ValidBits;
logic [NUMLINES-1:0] DirtyBits;
logic [LINELEN-1:0] ReadDataLineWay;
logic [LINELEN-1:0] ReadDataLine;
logic [TAGLEN-1:0] ReadTag;
logic Valid;
logic Dirty;
logic SelectedWay;
logic [TAGLEN-1:0] VicDirtyWay;
logic [TAGLEN-1:0] FlushThisWay;
logic SelData;
logic SelTag;
logic [$clog2(NUMLINES)-1:0] RAdrD;
logic SetValidD, ClearValidD;
logic SetDirtyD, ClearDirtyD;
logic WriteEnableD, VDWriteEnableD;
logic SRAMWayWriteEnableD;
/////////////////////////////////////////////////////////////////////////////////////////////
// Tag Array
/////////////////////////////////////////////////////////////////////////////////////////////
sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk),
.Adr(RAdr), .ReadData(ReadTag),
.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable));
// AND portion of distributed tag multiplexer
assign SelTag = SelFlush ? Flush : Victim;
assign VictimTag = SelTag ? ReadTag : '0; // AND part of AOMux
assign VictimDirty = SelTag & Dirty & Valid;
/////////////////////////////////////////////////////////////////////////////////////////////
// Data Array
/////////////////////////////////////////////////////////////////////////////////////////////
// *** Potential optimization: if byte write enables are available, could remove subwordwrites
genvar words;
for(words = 0; words < LINELEN/`XLEN; words++) begin: word
sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN))
CacheDataMem(.clk(clk), .Addr(RAdr),
.ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr),
.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(SRAMWayWriteEnable & SRAMWordEnable[words]));
end
sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN))
CacheTagMem(.clk(clk),
.Addr(RAdr),
.ReadData(ReadTag),
.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
.WriteEnable(TagWriteEnable));
// AND portion of distributed read multiplexers
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
assign SelectedWay = SelFlush ? FlushWay :
SelEvict ? VictimWay : WayHit;
assign ReadDataLineWayMasked = SelectedWay ? ReadDataLineWay : '0; // first part of AO mux.
assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid :
VictimWay & Dirty & Valid;
assign VicDirtyWay = VictimWay ? ReadTag : '0;
assign FlushThisWay = FlushWay ? ReadTag : '0;
assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay;
always_ff @(posedge clk) begin
if (reset)
ValidBits <= {NUMLINES{1'b0}};
else if (InvalidateAll)
ValidBits <= {NUMLINES{1'b0}};
else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b1;
else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b0;
end
always_ff @(posedge clk) begin
RAdrD <= RAdr;
SetValidD <= SetValid;
ClearValidD <= ClearValid;
WriteEnableD <= WriteEnable;
VDWriteEnableD <= VDWriteEnable;
end
assign SelData = SelFlush ? Flush : (SelEvict ? Victim : WayHit);
assign SelectedReadDataLine = SelData ? ReadDataLine : '0; // AND part of AO mux.
/////////////////////////////////////////////////////////////////////////////////////////////
// Valid Bits
/////////////////////////////////////////////////////////////////////////////////////////////
always_ff @(posedge clk) begin // Valid bit array,
if (reset | InvalidateAll) ValidBits <= #1 '0;
else if (SetValidD) ValidBits[RAdrD] <= #1 1'b1;
else if (ClearValidD) ValidBits[RAdrD] <= #1 1'b0;
end
// *** consider revisiting whether these delays are the best option?
flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, SRAMWayWriteEnable},
{SetValidD, ClearValidD, SRAMWayWriteEnableD});
assign Valid = ValidBits[RAdrD];
/////////////////////////////////////////////////////////////////////////////////////////////
// Dirty Bits
/////////////////////////////////////////////////////////////////////////////////////////////
// Dirty bits
if(DIRTY_BITS) begin:dirty
if (DIRTY_BITS) begin:dirty
always_ff @(posedge clk) begin
if (reset) DirtyBits <= {NUMLINES{1'b0}};
else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1;
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0;
end
always_ff @(posedge clk) begin
SetDirtyD <= SetDirty;
ClearDirtyD <= ClearDirty;
if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
else if (SetDirtyD) DirtyBits[RAdrD] <= #1 1'b1;
else if (ClearDirtyD) DirtyBits[RAdrD] <= #1 1'b0;
end
flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
assign Dirty = DirtyBits[RAdrD];
end else begin:dirty
assign Dirty = 1'b0;
end
end else assign Dirty = 1'b0;
endmodule // DCacheMemWay
endmodule

90
pipelined/src/cache/dcache_ptw_interaction_README.txt vendored
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@ -1,90 +0,0 @@
Intractions betwen the dcache and hardware page table walker are complex.
In particular the complications arise when a fault occurs concurrently with a memory operation.
At the begining of every memory operation there are 8 combinations of three signals;
ITBL miss, DTLB miss, and a memory operation. By looking at each combination we
can understand exactly the correct sequence of operations and if the operation
should continue.
It is important to note ITLB misses and faults DO NOT flush a memory operation
in the memory stage. This is the core reason for the complexity.
| Type | ITLB miss | DTLB miss | mem op | |
|-------+-----------+-----------+--------+--------------|
| 0 | 0 | 0 | 0 | |
| 1 | 0 | 0 | 1 | |
| 2 | 0 | 1 | 0 | Not possible |
| 3 | 0 | 1 | 1 | |
| 4 | 1 | 0 | 0 | |
| 5 | 1 | 0 | 1 | |
| 6 | 1 | 1 | 0 | Not possible |
| 7 | 1 | 1 | 1 | |
The above table classifies the operations into 8 categories.
2 of the 8 are not possible because a DTLB miss implies a memory operation.
Each (I/D)TLB miss results in either a write to the corresponding TLB or a TLB fault.
To complicate things it is possilbe to have concurrent ITLB and DTLB misses, which
both can result in either a write or a fault. The table belows shows the possible
scenarios and the sequence of operations.
| Type | action 1 | action 2 | action 3 | keep stall? |
|------+------------------+-----------------+-----------------+-------------|
| 1 | D$ handles memop | | | Yes |
| 3a | DTLB Write | D$ finish memop | | Yes |
| 3b | DTLB Fault | Abort memop | | No |
| 4a | ITLB write | | | No |
| 4b | ITLB Fault | | | No |
| 5a | ITLB Write | D$ finish memop | | Yes |
| 5b | ITLB Fault | D$ finish memop | | Yes |
| 7a | DTLB Write | ITLB write | D$ finish memop | Yes |
| 7b | DTLB Write | ITLB Fault | D$ finish memop | Yes |
| 7c | DTLB Fault | Abort all | | No |
Type 1 is a memory operation which either hits in the DTLB or is a physical address. The
Dcache handles the operation.
Type 3a is a memory operation with a DTLB miss. The Dcache enters a special set of states
designed to handle the page table walker (HTPW). Secondly the HPTW takes control over the
LSU via a set of multiplexors in the LSU Arbiter, driving the Dcache with addresses of the
page table. Interally to the HPTW an FSM checks each node of the Page Table and eventually
signals either a TLB write or a TLB Fault. In Type 3a the DTLB is written with the leaf
page table entry and returns control of the Dcache back to the IEU. Now the Dcache finishes
the memory operation using the physical address provided by the TLB. Note it is crucial
the dcache replay the memory access into the cache's SRAM memory. As the HPTW sends it
requests through the Dcache the original memory operation's SRAM lookup will be lost.
Type 3b is similar to the 3a type in that is starts with the same conditions; however the
at the end of the page table walk a fault is detched. Rather than update the TLB the CPU
and the dcache need to be informed about the fault and abort the memory operation. Unlike
Type 3a the dcache returns directly to STATE_READY and lowers the stall.
Type 4a is the simpliest form of TLB miss as it is an ITLB miss with no memory operation.
The Dcache switches in to the special set of page table states and the HPTW takes control
of the Dcache. Like with Type 3a the HPTW sends data request through the Dcache and eventually
reads a leaf page table entry (PTE). At this time the HPTW writes the PTE to the ITLB and
removes the stall as there is not memory operation to do.
Type 4b is also an ITLB miss. As with 4a the Dcache switches into page table walker mode and reads
until it finds a leaf or in this case a fault. The fault is deteched and the Dcaches switches back
to normal mode.
Type 5a is a Type 4a with a current memory operation. The Dcache first switches to walker mode.
Other traps.
A new problem has emerged. What happens when an interrupt occurs during a page table walk?
The dcache has an output called CommittedM which tells the CPU if the memory operation is
committed into the memory system. It would be wrong to pin the interrupt to a memory operation
when it is already or partially committed to the memory system. Instead the next instruction
has to be pinned to the interrupt. The complexity occurs with the ITLB miss; types 4, 5 and 7.
Type 4: The ITLB misses and starts using the dcache to fetch the page table. There is no memory
operation. Depending on where in the walk the operations could be aborted. If the tlb is not yet
updated then the walk could be aborted. However if the TLB is updated then the interrupt must be
delayed until the next instruction.
What is the meaning of CommittedM?
This signal informs the CPU if a memory operation is not started or if it is between started
and done. Once a memory op is started it should not be interrupted. This is used to prevent the
CPU from generating an interrupt after the operation is partially or completely done.

36
pipelined/src/cache/sram1rw.sv vendored
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@ -34,25 +34,22 @@
// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
module sram1rw #(parameter DEPTH=128, WIDTH=256) (
input logic clk,
// port 1 is read only
input logic [$clog2(DEPTH)-1:0] Addr,
output logic [WIDTH-1:0] ReadData,
// port 2 is write only
input logic [WIDTH-1:0] WriteData,
input logic WriteEnable
);
input logic clk,
input logic [$clog2(DEPTH)-1:0] Adr,
input logic [WIDTH-1:0] WriteData,
input logic WriteEnable,
output logic [WIDTH-1:0] ReadData);
logic [DEPTH-1:0][WIDTH-1:0] StoredData; // *** inconsistency in packed vs. unpacked
logic [$clog2(DEPTH)-1:0] AddrD;
logic [WIDTH-1:0] WriteDataD;
logic WriteEnableD;
logic [WIDTH-1:0] StoredData[DEPTH-1:0];
logic [$clog2(DEPTH)-1:0] AddrD;
logic [WIDTH-1:0] WriteDataD;
logic WriteEnableD;
//*** model as single port
// *** merge with simpleram
always_ff @(posedge clk) begin
AddrD <= Addr;
WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay.
AddrD <= Adr;
WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay. Implement alternative cache stall to avoid this. Eliminates a bunch of delay flops elsewhere
WriteEnableD <= WriteEnable;
if (WriteEnableD) begin
StoredData[AddrD] <= #1 WriteDataD;
@ -60,7 +57,12 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
end
assign ReadData = StoredData[AddrD];
/*
always_ff @(posedge clk) begin
ReadData <= RAM[Adr];
if (WriteEnable) RAM[Adr] <= WriteData;
end
*/
endmodule

69
pipelined/src/cache/subcachelineread.sv vendored Normal file
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@ -0,0 +1,69 @@
///////////////////////////////////////////
// subcachelineread
//
// Written: Ross Thompson ross1728@gmail.com February 04, 2022
// Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes.
//
// Purpose: Controller for the dcache fsm
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// MIT LICENSE
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
// to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)(
input logic clk,
input logic reset,
input logic [`PA_BITS-1:0] PAdr,
input logic save, restore,
input logic [LINELEN-1:0] ReadDataLine,
output logic [WORDLEN-1:0] ReadDataWord);
localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
localparam PADLEN = WORDLEN-MUXINTERVAL;
// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
// easily build a variable input mux.
// *** move this to LSU and IFU, also remove mux from busdp into LSU.
// *** give this a module name to match block diagram
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved;
if (PADLEN > 0) begin
logic [PADLEN-1:0] Pad;
assign Pad = '0;
assign ReadDataLinePad = {Pad, ReadDataLine};
end else assign ReadDataLinePad = ReadDataLine;
genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)];
end
// variable input mux
assign ReadDataWordRaw = ReadDataLineSets[PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]];
if(!`REPLAY) begin
flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved);
mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved,
restore, ReadDataWord);
end else assign ReadDataWord = ReadDataWordRaw;
endmodule

20
pipelined/src/generic/flop/simpleram.sv
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@ -40,18 +40,14 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
/* verilator lint_off WIDTH */
if (`XLEN == 64) begin:ramrw
always_ff @(posedge clk) begin
rd <= RAM[a[31:3]];
if (we) RAM[a[31:3]] <= #1 wd;
end
end else begin
always_ff @(posedge clk) begin:ramrw
rd <= RAM[a[31:2]];
if (we) RAM[a[31:2]] <= #1 wd;
end
// discard bottom 2 or 3 bits of address offset within word or doubleword
localparam adrlsb = (`XLEN==64) ? 3 : 2;
logic [31:adrlsb] adrmsbs;
assign adrmsbs = a[31:adrlsb];
always_ff @(posedge clk) begin
rd <= RAM[adrmsbs];
if (we) RAM[adrmsbs] <= #1 wd;
end
/* verilator lint_on WIDTH */
endmodule

4
pipelined/src/ieu/controller.sv
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@ -166,7 +166,7 @@ module controller(
// unswizzle control bits
// squash control signals if coming from an illegal compressed instruction
// On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them.
assign IllegalERegAdrD = `E_SUPPORTED & RegWriteD & InstrD[11];
assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11];
assign IllegalBaseInstrFaultD = ControlsD[0] | IllegalERegAdrD;
assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD,
@ -187,7 +187,7 @@ module controller(
// Fences
// Ordinary fence is presently a nop
// FENCE.I flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
if (`ZIFENCEI_SUPPORTED & `MEM_ICACHE) begin:fencei
if (`ZIFENCEI_SUPPORTED & (`IMEM == `MEM_CACHE)) begin:fencei
logic FenceID;
assign FenceID = FenceD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
assign InvalidateICacheD = FenceID;

5
pipelined/src/ieu/datapath.sv
View File

@ -125,7 +125,7 @@ module datapath (
// Writeback stage pipeline register and logic
flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW);
flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
flopen #(`XLEN) ReadDataWReg(.clk, .en(~StallW), .d(ReadDataM), .q(ReadDataW));
flopen #(`XLEN) ReadDataWReg(clk, ~StallW, ReadDataM, ReadDataW);
mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, WriteDataW);
// floating point interactions: fcvt, fp stores
@ -133,8 +133,7 @@ module datapath (
mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
end else begin:fpmux
assign ResultM = IEUResultM;
assign WriteDataE = ForwardedSrcBE;
assign ResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE;
end
// handle Store Conditional result if atomic extension supported

2
pipelined/src/ieu/regfile.sv
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@ -50,7 +50,7 @@ module regfile (
// reset is intended for simulation only, not synthesis
always_ff @(negedge clk) // or posedge reset)
always_ff @(negedge clk) // or posedge reset) // *** make this a preload in testbench rather than reset
if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= 0;
else if (we3) rf[a3] <= wd3;

99
pipelined/src/ifu/bpred.sv
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@ -35,10 +35,11 @@
module bpred
(input logic clk, reset,
input logic StallF, StallD, StallE,
input logic FlushF, FlushD, FlushE,
input logic StallF, StallD, StallE, StallM,
input logic FlushF, FlushD, FlushE, FlushM,
// Fetch stage
// the prediction
input logic [31:0] InstrD,
input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
output logic [`XLEN-1:0] BPPredPCF,
output logic SelBPPredF,
@ -53,13 +54,14 @@ module bpred
input logic [`XLEN-1:0] IEUAdrE, // The branch destination if the branch is taken.
input logic [`XLEN-1:0] PCD, // The address the branch predictor took.
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
input logic [4:0] InstrClassE,
output logic [4:0] InstrClassM,
// Report branch prediction status
output logic BPPredWrongE,
output logic BPPredDirWrongE,
output logic BTBPredPCWrongE,
output logic RASPredPCWrongE,
output logic BPPredClassNonCFIWrongE
output logic BPPredWrongM,
output logic BPPredDirWrongM,
output logic BTBPredPCWrongM,
output logic RASPredPCWrongM,
output logic BPPredClassNonCFIWrongM
);
logic BTBValidF;
@ -71,14 +73,14 @@ module bpred
logic FallThroughWrongE;
logic PredictionPCWrongE;
logic PredictionInstrClassWrongE;
logic [4:0] InstrClassD, InstrClassE;
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
// Part 1 branch direction prediction
if (`BPTYPE == "BPTWOBIT") begin:Predictor
twoBitPredictor DirPredictor(.clk(clk),
.reset(reset),
.StallF(StallF),
twoBitPredictor DirPredictor(.clk, .reset, .StallF,
.LookUpPC(PCNextF),
.Prediction(BPPredF),
// update
@ -87,58 +89,27 @@ module bpred
.UpdatePrediction(UpdateBPPredE));
end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
globalHistoryPredictor DirPredictor(.clk, .reset, .StallF, .StallE,
.PCNextF, .BPPredF,
.InstrClassE, .BPInstrClassF, .BPInstrClassD, .BPInstrClassE, .BPPredDirWrongE,
.PCE, .PCSrcE, .UpdateBPPredE);
globalHistoryPredictor DirPredictor(.clk(clk),
.reset(reset),
.*, // Stalls and flushes
.PCNextF(PCNextF),
.BPPredF(BPPredF),
// update
.InstrClassE(InstrClassE),
.BPInstrClassE(BPInstrClassE),
.BPPredDirWrongE(BPPredDirWrongE),
.PCE(PCE),
.PCSrcE(PCSrcE),
.UpdateBPPredE(UpdateBPPredE));
end else if (`BPTYPE == "BPGSHARE") begin:Predictor
gsharePredictor DirPredictor(.clk(clk),
.reset(reset),
.*, // Stalls and flushes
.PCNextF(PCNextF),
.BPPredF(BPPredF),
// update
.InstrClassE(InstrClassE),
.BPInstrClassE(BPInstrClassE),
.BPPredDirWrongE(BPPredDirWrongE),
.PCE(PCE),
.PCSrcE(PCSrcE),
.UpdateBPPredE(UpdateBPPredE));
gsharePredictor DirPredictor(.clk, .reset, .StallF, .StallE,
.PCNextF, .BPPredF,
.InstrClassE, .BPInstrClassF, .BPInstrClassD, .BPInstrClassE, .BPPredDirWrongE,
.PCE, .PCSrcE, .UpdateBPPredE);
end
else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
localHistoryPredictor DirPredictor(.clk(clk),
.reset(reset),
.*, // Stalls and flushes
localHistoryPredictor DirPredictor(.clk,
.reset, .StallF, .StallE, .FlushF,
.LookUpPC(PCNextF),
.Prediction(BPPredF),
// update
.UpdatePC(PCE),
.UpdateEN(InstrClassE[0] & ~StallE),
.PCSrcE(PCSrcE),
.UpdatePrediction(UpdateBPPredE));
end
else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
localHistoryPredictor DirPredictor(.clk(clk),
.reset(reset),
.*, // Stalls and flushes
.LookUpPC(PCNextF),
.Prediction(BPPredF),
// update
.UpdatePC(PCE),
.UpdateEN(InstrClassE[0] & ~StallE),
.PCSrcE(PCSrcE),
.PCSrcE,
.UpdatePrediction(UpdateBPPredE));
end
@ -201,15 +172,35 @@ module bpred
.d(BPPredD),
.q(BPPredE));
// the branch predictor needs a compact decoding of the instruction class.
// *** consider adding in the alternate return address x5 for returns.
assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
assign InstrClassD[3] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
assign InstrClassD[1] = InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5
assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
flopenrc #(5) InstrClassRegE(.clk, .reset, .en(~StallE), .clear(FlushE), .d(InstrClassD), .q(InstrClassE));
flopenrc #(5) InstrClassRegM(.clk, .reset, .en(~StallM), .clear(FlushM), .d(InstrClassE), .q(InstrClassM));
flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), .d(BPPredWrongE), .q(BPPredWrongM));
// branch predictor
flopenrc #(4) BPPredWrongRegM(.clk, .reset, .en(~StallM), .clear(FlushM),
.d({BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}),
.q({BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}));
// pipeline the class
flopenrc #(5) InstrClassRegD(.clk(clk),
flopenrc #(5) BPInstrClassRegD(.clk(clk),
.reset(reset),
.en(~StallD),
.clear(FlushD),
.d(BPInstrClassF),
.q(BPInstrClassD));
flopenrc #(5) InstrClassRegE(.clk(clk),
flopenrc #(5) BPInstrClassRegE(.clk(clk),
.reset(reset),
.en(~StallE),
.clear(FlushE),

129
pipelined/src/ifu/ifu.sv
View File

@ -92,7 +92,7 @@ module ifu (
logic [`XLEN-3:0] PCPlusUpperF;
logic CompressedF;
logic [31:0] InstrRawD, InstrRawF;
logic [`XLEN-1:0] FinalInstrRawF;
logic [31:0] FinalInstrRawF;
logic [31:0] InstrE;
logic [`XLEN-1:0] PCD;
@ -100,8 +100,6 @@ module ifu (
localparam [31:0] nop = 32'h00000013; // instruction for NOP
logic [`XLEN-1:0] PCBPWrongInvalidate;
logic BPPredWrongM;
(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
logic [`XLEN+1:0] PCFExt;
@ -159,9 +157,8 @@ module ifu (
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
end else begin
assign {ITLBMissF, InstrAccessFaultF} = '0;
assign InstrPageFaultF = '0;
assign PCPF = PCF;
assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF} = '0;
assign PCPF = PCFExt[`PA_BITS-1:0];
assign CacheableF = '1;
end
@ -173,45 +170,38 @@ module ifu (
assign InstrRawF = AllInstrRawF[31:0];
if (`MEM_IROM) begin : irom
dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF), .IEUAdrE(PCNextFSpill),
if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM
dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
.TrapM(1'b0), .FinalWriteDataM(),
.ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
.BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF),
.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
end else begin : bus
localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
localparam integer LOGWPL = `MEM_ICACHE ? $clog2(WORDSPERLINE) : 1;
localparam integer LINELEN = `MEM_ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
localparam integer WordCountThreshold = `MEM_ICACHE ? WORDSPERLINE - 1 : 0;
localparam integer LINEBYTELEN = LINELEN/8;
localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
logic [LOGWPL-1:0] WordCount;
logic SelUncachedAdr;
localparam integer WORDSPERLINE = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/`XLEN : 1;
localparam integer LINELEN = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS : `XLEN;
localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
logic [LINELEN-1:0] ReadDataLine;
logic [LINELEN-1:0] ICacheMemWriteData;
logic [`PA_BITS-1:0] LocalIFUBusAdr;
logic [`PA_BITS-1:0] ICacheBusAdr;
logic ICacheBusAck;
genvar index;
busdp #(WORDSPERLINE, LINELEN)
logic save,restore;
logic [31:0] temp;
busdp #(WORDSPERLINE, LINELEN, 32, LOGWPL)
busdp(.clk, .reset,
.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(),
.LSUBusRead(IFUBusRead), .LSUBusHWDATA(), .LSUBusSize(),
.LSUBusRead(IFUBusRead), .LSUBusSize(),
.LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
.ReadDataLineSetsM(), .DCacheFetchLine(ICacheFetchLine),
.WordCount(), .LSUBusHWDATA(),
.DCacheFetchLine(ICacheFetchLine),
.DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck),
.DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF),
.FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF),
.FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF[31:0]),
.IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
.BusStall, .BusCommittedM());
if(`MEM_ICACHE) begin : icache
if(`IMEM == `MEM_CACHE) begin : icache
logic [1:0] IFURWF;
assign IFURWF = CacheableF ? 2'b10 : 2'b00;
@ -221,29 +211,29 @@ module ifu (
icache(.clk, .reset, .CPUBusy, .IgnoreRequest(ITLBMissF),
.CacheMemWriteData(ICacheMemWriteData), .CacheBusAck(ICacheBusAck),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
.ReadDataWord(FinalInstrRawF), .CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(), .ReadDataLineSets(),
.CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(), .ReadDataLine(ReadDataLine),
.save, .restore,
.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
.FinalWriteData('0),
.RW(IFURWF),
.Atomic(2'b00), .FlushCache(1'b0),
.Atomic('0), .FlushCache('0),
.NextAdr(PCNextFSpill[11:0]),
.PAdr(PCPF),
.CacheCommitted(), .InvalidateCacheM(InvalidateICacheM));
subcachelineread #(LINELEN, 32, 16) subcachelineread(
.clk, .reset, .PAdr(PCPF), .save, .restore,
.ReadDataLine, .ReadDataWord(FinalInstrRawF));
end else begin : passthrough
assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0;
assign ICacheAccess = CacheableF; assign ICacheMiss = CacheableF;
end
end
end
// branch predictor signal
logic SelBPPredF;
logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F;
logic [4:0] InstrClassD, InstrClassE;
logic [`XLEN-1:0] PCNext1F, PCNext2F;
assign IFUCacheBusStallF = ICacheStallF | BusStall;
assign IFUStallF = IFUCacheBusStallF | SelNextSpillF;
@ -253,53 +243,42 @@ module ifu (
assign PrivilegedChangePCM = RetM | TrapM;
// *** move unnecessary muxes into BPRED_ENABLED
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
logic [`XLEN-1:0] BPPredPCF, PCNext0F;
// The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE.
mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F));
// Mux only required on instruction class miss prediction.
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(PCBPWrongInvalidate));
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
// *** moved outside the bp. clean up. Should not be able to remove without bp.
mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
// branch and jump predictor
if (`BPRED_ENABLED) begin : bpred
// *** move the rest of this hardware into branch predictor including instruction class registers
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), .d(BPPredWrongE), .q(BPPredWrongM));
logic BPPredWrongM;
logic SelBPPredF;
bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE,
.FlushF, .FlushD, .FlushE,
.PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
.PCD, .PCLinkE, .InstrClassE, .BPPredWrongE, .BPPredDirWrongE,
.BTBPredPCWrongE, .RASPredPCWrongE, .BPPredClassNonCFIWrongE);
.StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM,
.InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
// the branch predictor needs a compact decoding of the instruction class.
// *** consider adding in the alternate return address x5 for returns.
assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
assign InstrClassD[3] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
assign InstrClassD[1] = InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5
assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
// branch predictor
flopenrc #(5) InstrClassRegE(.clk, .reset, .en(~StallE), .clear(FlushE), .d(InstrClassD), .q(InstrClassE));
flopenrc #(5) InstrClassRegM(.clk, .reset, .en(~StallM), .clear(FlushM), .d(InstrClassE), .q(InstrClassM));
flopenrc #(4) BPPredWrongRegM(.clk, .reset, .en(~StallM), .clear(FlushM),
.d({BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}),
.q({BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}));
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
// Mux only required on instruction class miss prediction.
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
.s(BPPredWrongM), .y(PCBPWrongInvalidate));
end else begin : bpred
assign BPPredPCF = '0;
assign BPPredWrongE = PCSrcE;
assign BPPredWrongM = '0;
assign {SelBPPredF, BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
assign PCNext0F = PCPlus2or4F;
//assign PCNext1F = PCPlus2or4F;
//assign PCBPWrongInvalidate = PCE;
end
// pcadder
@ -313,16 +292,12 @@ module ifu (
else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
// Decode stage pipeline register and logic
flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
// expand 16-bit compressed instructions to 32 bits
decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
// *** combine these with others in better way, including M, F
// Misaligned PC logic
// Instruction address misalignement only from br/jal(r) instructions.
@ -336,7 +311,6 @@ module ifu (
// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
// *** Ross Thompson. Check InstrMisalignedAdrM as I believe it is the same as PCF. Should be able to remove.
flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
// Instruction and PC/PCLink pipeline registers
@ -347,4 +321,3 @@ module ifu (
flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
endmodule

4
pipelined/src/ifu/spillsupport.sv
View File

@ -48,7 +48,7 @@ module spillsupport (
output logic CompressedF);
localparam integer SPILLTHRESHOLD = `MEM_ICACHE ? `ICACHE_LINELENINBITS/32 : 1;
localparam integer SPILLTHRESHOLD = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/32 : 1;
logic [`XLEN-1:0] PCPlus2F;
logic TakeSpillF;
logic SpillF;
@ -91,7 +91,7 @@ module spillsupport (
flopenr #(16) SpillInstrReg(.clk(clk),
.en(SpillSaveF),
.reset(reset),
.d(`MEM_ICACHE ? InstrRawF[15:0] : InstrRawF[31:16]),
.d((`IMEM == `MEM_CACHE) ? InstrRawF[15:0] : InstrRawF[31:16]),
.q(SpillDataLine0));
assign PostSpillInstrRawF = SpillF ? {InstrRawF[15:0], SpillDataLine0} : InstrRawF;

31
pipelined/src/lsu/busdp.sv
View File

@ -34,7 +34,7 @@
`include "wally-config.vh"
module busdp #(parameter WORDSPERLINE, parameter LINELEN)
module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
(
input logic clk, reset,
// bus interface
@ -46,10 +46,9 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN)
output logic [2:0] LSUBusSize,
input logic [2:0] LSUFunct3M,
output logic [`PA_BITS-1:0] LSUBusAdr,
output logic [LOGWPL-1:0] WordCount,
// cache interface.
input logic [`PA_BITS-1:0] DCacheBusAdr,
input var logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0],
input logic DCacheFetchLine,
input logic DCacheWriteLine,
output logic DCacheBusAck,
@ -58,8 +57,8 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN)
// lsu interface
input logic [`PA_BITS-1:0] LSUPAdrM,
input logic [`XLEN-1:0] FinalAMOWriteDataM,
input logic [`XLEN-1:0] ReadDataWordM,
output logic [`XLEN-1:0] ReadDataWordMuxM,
input logic [WORDLEN-1:0] ReadDataWordM,
output logic [WORDLEN-1:0] ReadDataWordMuxM,
input logic IgnoreRequest,
input logic [1:0] LSURWM,
input logic CPUBusy,
@ -68,13 +67,11 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN)
output logic BusCommittedM);
localparam integer WordCountThreshold = `MEM_DCACHE ? WORDSPERLINE - 1 : 0;
localparam integer LOGWPL = `MEM_DCACHE ? $clog2(WORDSPERLINE) : 1;
localparam integer WordCountThreshold = (`DMEM == `MEM_CACHE) ? WORDSPERLINE - 1 : 0;
logic SelUncachedAdr;
logic [`XLEN-1:0] PreLSUBusHWDATA;
logic [`PA_BITS-1:0] LocalLSUBusAdr;
logic [LOGWPL-1:0] WordCount;
logic SelUncachedAdr;
genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
@ -85,15 +82,15 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN)
mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr);
assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount]; // only in lsu, not ifu
mux2 #(`XLEN) lsubushwdatamux(.d0(PreLSUBusHWDATA), .d1(FinalAMOWriteDataM),
.s(SelUncachedAdr), .y(LSUBusHWDATA));
mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M),
.s(SelUncachedAdr), .y(LSUBusSize));
mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheMemWriteData[`XLEN-1:0]),
.s(SelUncachedAdr), .y(ReadDataWordMuxM));
if(LSU == 1) mux2 #(`XLEN) lsubushwdatamux( .d0(ReadDataWordM), .d1(FinalAMOWriteDataM),
.s(SelUncachedAdr), .y(LSUBusHWDATA));
else assign LSUBusHWDATA = '0;
mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M),
.s(SelUncachedAdr), .y(LSUBusSize));
mux2 #(WORDLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheMemWriteData[WORDLEN-1:0]),
.s(SelUncachedAdr), .y(ReadDataWordMuxM));
busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE)
busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup Icache? must fix.
busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
.LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusRead,
.DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);

22
pipelined/src/lsu/dtim.sv
View File

@ -48,18 +48,18 @@ module dtim(
output logic DCacheMiss,
output logic DCacheAccess);
simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk,
.a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]),
.we(LSURWM[0] & ~TrapM), // have to ignore write if Trap.
.wd(FinalWriteDataM), .rd(ReadDataWordM));
simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk,
.a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently ***
.we(LSURWM[0] & ~TrapM), // have to ignore write if Trap.
.wd(FinalWriteDataM), .rd(ReadDataWordM));
// since we have a local memory the bus connections are all disabled.
// There are no peripherals supported.
assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0;
assign ReadDataWordMuxM = ReadDataWordM;
assign {DCacheStallM, DCacheCommittedM} = '0;
assign {DCacheMiss, DCacheAccess} = '0;
// since we have a local memory the bus connections are all disabled.
// There are no peripherals supported.
assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0;
assign ReadDataWordMuxM = ReadDataWordM;
assign {DCacheStallM, DCacheCommittedM} = '0;
assign {DCacheMiss, DCacheAccess} = '0;
endmodule

75
pipelined/src/lsu/lsu.sv
View File

@ -110,7 +110,7 @@ module lsu (
// MMU include PMP and is needed if any privileged supported
/////////////////////////////////////////////////////////////////////////////////////////////
if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
.DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM, .SATP_REGW, .PCF,
.ReadDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM,
@ -167,49 +167,64 @@ module lsu (
end
/////////////////////////////////////////////////////////////////////////////////////////////
// Hart Memory System
// Memory System
// Either Data Cache or Data Tightly Integrated Memory or just bus interface
/////////////////////////////////////////////////////////////////////////////////////////////
logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM;
logic [`XLEN-1:0] ReadDataWordM;
logic [`XLEN-1:0] ReadDataWordMuxM;
if (`MEM_DTIM) begin : dtim
logic SelUncachedAdr;
if (`DMEM == `MEM_TIM) begin : dtim
dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM,
.ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
.ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM,
.DCacheMiss, .DCacheAccess);
end else begin : bus
localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
localparam integer LINELEN = `MEM_DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0];
localparam integer WORDSPERLINE = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS/`XLEN : 1;
localparam integer LINELEN = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS : `XLEN;
localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
logic [LINELEN-1:0] ReadDataLineM;
logic [LINELEN-1:0] DCacheMemWriteData;
logic [`PA_BITS-1:0] DCacheBusAdr;
logic DCacheWriteLine;
logic DCacheFetchLine;
logic DCacheBusAck;
logic save, restore;
logic [`PA_BITS-1:0] WordOffsetAddr;
logic SelBus;
logic [LOGWPL-1:0] WordCount;
busdp #(WORDSPERLINE, LINELEN, `XLEN, LOGWPL, 1) busdp(
.clk, .reset,
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
.WordCount,
.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
.DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM,
.ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
.BusStall, .BusCommittedM);
assign WordOffsetAddr = LSUBusWrite ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM;
busdp #(WORDSPERLINE, LINELEN)
busdp(.clk, .reset,
.LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusHWDATA, .LSUBusSize,
.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .ReadDataLineSetsM, .DCacheFetchLine,
.DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM,
.ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
.BusStall, .BusCommittedM);
if(`MEM_DCACHE) begin : dcache
if(`DMEM == `MEM_CACHE) begin : dcache
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1))
dcache(.clk, .reset, .CPUBusy,
.RW(CacheableM ? LSURWM : 2'b00), .FlushCache(FlushDCacheM),
.Atomic(CacheableM ? LSUAtomicM : 2'b00), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
.FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM),
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.IgnoreRequest, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr),
.ReadDataLineSets(ReadDataLineSetsM), .CacheMemWriteData(DCacheMemWriteData),
.CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine),
.CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache(
.clk, .reset, .CPUBusy,
.RW(CacheableM ? LSURWM : 2'b00), .FlushCache(FlushDCacheM),
.Atomic(CacheableM ? LSUAtomicM : 2'b00), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
.save, .restore,
.FinalWriteData(FinalWriteDataM),
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.IgnoreRequest, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr),
.ReadDataLine(ReadDataLineM), .CacheMemWriteData(DCacheMemWriteData),
.CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine),
.CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread(
.clk, .reset, .PAdr(WordOffsetAddr), .save, .restore,
.ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM));
end else begin : passthrough
assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
@ -218,14 +233,14 @@ module lsu (
end
subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
.Funct3M(LSUFunct3M), .ReadDataM);
.Funct3M(LSUFunct3M), .ReadDataM);
// this might only get instantiated if there is a dcache or dtim.
// There is a copy in the ebu. *** is it needed there, or can data come in from ebu, get muxed here and sent back out
// Explore changing feedback path from output of AMOALU to subword write ***
subwordwrite subwordwrite(.HRDATA(ReadDataWordM), .HADDRD(LSUPAdrM[2:0]),
.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
.HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM));
.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
.HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM));
/////////////////////////////////////////////////////////////////////////////////////////////
// Atomic operations
@ -233,8 +248,8 @@ module lsu (
if (`A_SUPPORTED) begin:atomic
atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .WriteDataM, .LSUPAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM);
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM);
end else begin:lrsc
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = WriteDataM;
end

25
pipelined/src/lsu/lsuvirtmen.sv
View File

@ -73,20 +73,16 @@ module lsuvirtmem(
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
interlockfsm interlockfsm (.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF,
.DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM,
.InterlockStall, .SelReplayCPURequest, .SelHPTW,
.IgnoreRequest);
hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
.ITLBMissF(ITLBMissF & ~TrapM),
.DTLBMissM(DTLBMissM & ~TrapM),
.PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
.HPTWReadPTE(ReadDataM),
.DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWSize);
interlockfsm interlockfsm (
.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF,
.DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM,
.InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequest);
hptw hptw( // *** remove logic from (), mention this in style guide CH3
.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
.ITLBMissF(ITLBMissF & ~TrapM), .DTLBMissM(DTLBMissM & ~TrapM),
.PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM),
.DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWSize);
// arbiter between IEU and hptw
// multiplex the outputs to LSU
mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLSURWM);
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
@ -98,5 +94,4 @@ module lsuvirtmem(
// always block interrupts when using the hardware page table walker.
assign CPUBusy = StallW & ~SelHPTW;
endmodule; // lsuvirtmem
endmodule

2
pipelined/src/mmu/mmu.sv
View File

@ -97,7 +97,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
logic TLBPageFault;
// only instantiate TLB if Virtual Memory is supported
if (`MEM_VIRTMEM) begin:tlb
if (`VIRTMEM_SUPPORTED) begin:tlb
logic ReadAccess, WriteAccess;
assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages
assign WriteAccess = WriteAccessM;

13
pipelined/src/privileged/csrm.sv
View File

@ -145,25 +145,18 @@ module csrm #(parameter
assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
// CSRs
flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); //busybear: changed reset value to 0
flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW);
if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin:deleg // DELEG registers should exist
flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW);
flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW);
end else begin
assign MEDELEG_REGW = 0;
assign MIDELEG_REGW = 0;
end
end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0;
flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW);
flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
if(`QEMU) assign MTVAL_REGW = `XLEN'b0;
else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
if (`BUSYBEAR == 1) begin:counters // counter 1 (TIME) enable tied to 0 to match simulator***
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, MCOUNTEREN_REGW);
end else begin:counters
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
end
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);

15
pipelined/src/privileged/csrs.sv
View File

@ -91,22 +91,17 @@ module csrs #(parameter
assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM;
// CSRs
flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); //busybear: change reset to 0
flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW);
flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW);
flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW);
flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
if (`MEM_VIRTMEM)
if (`VIRTMEM_SUPPORTED)
flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
else
assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
if (`BUSYBEAR == 1) begin:scounteren
flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, SCOUNTEREN_REGW);
end else if (`BUILDROOT == 1) begin:scounteren
flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
end else begin:scounteren
flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
end
flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
if (`N_SUPPORTED) begin:nregs
logic WriteSEDELEGM, WriteSIDELEGM;
assign WriteSEDELEGM = CSRSWriteM & (CSRAdrM == SEDELEG);
@ -134,7 +129,7 @@ module csrs #(parameter
SEPC: CSRSReadValM = SEPC_REGW;
SCAUSE: CSRSReadValM = SCAUSE_REGW;
STVAL: CSRSReadValM = STVAL_REGW;
SATP: if (`MEM_VIRTMEM & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
else begin
CSRSReadValM = 0;
if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1;

4
pipelined/src/privileged/csrsr.sv
View File

@ -96,7 +96,7 @@ module csrsr (
// SXL and UXL bits only matter for RV64. Set to 10 for RV64 if mode is supported, or 0 if not
assign STATUS_SXL = `S_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if supervisor mode supported
assign STATUS_UXL = `U_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if user mode supported
assign STATUS_SUM = `S_SUPPORTED & `MEM_VIRTMEM & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
assign STATUS_SUM = `S_SUPPORTED & `VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported
assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP
assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic
@ -117,7 +117,7 @@ module csrsr (
STATUS_MXR_INT <= #1 0;
STATUS_SUM_INT <= #1 0;
STATUS_MPRV_INT <= #1 0; // Per Priv 3.3
STATUS_FS_INT <= #1 0; //2'b01; // busybear: change all these reset values to 0
STATUS_FS_INT <= #1 0;
STATUS_MPP <= #1 0; //`M_MODE;
STATUS_SPP <= #1 0; //1'b1;
STATUS_MPIE <= #1 0; //1;

8
pipelined/testbench/common/function_radix.sv → pipelined/testbench/common/functionName.sv
View File

@ -46,7 +46,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
logic [`XLEN-1:0] PCF, PCD, PCE, FunctionAddr;
logic StallD, StallE, FlushD, FlushE;
integer ProgramAddrIndex;
integer ProgramAddrIndex, ProgramAddrIndexQ;
assign PCF = testbench.dut.core.PCF;
assign StallD = testbench.dut.core.StallD;
@ -163,8 +163,12 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
bin_search_min(PCE, ProgramAddrMapLineCount, ProgramAddrMapMemory, FunctionAddr, ProgramAddrIndex);
end
logic OrReducedAdr, AnyUnknown;
assign OrReducedAdr = |ProgramAddrIndex;
assign AnyUnknown = (OrReducedAdr === 1'bx) ? 1'b1 : 1'b0;
initial ProgramAddrIndex = '0;
assign FunctionName = ProgramLabelMapMemory[ProgramAddrIndex];
assign FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex];
endmodule // function_radix

4
pipelined/testbench/testbench-coremark_bare.sv
View File

@ -137,7 +137,9 @@ module testbench();
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
end
endmodule
/* verilator lint_on STMTDLY */
/* verilator lint_on WIDTH */

22
pipelined/testbench/testbench-fpga.sv
View File

@ -549,7 +549,7 @@ string tests32f[] = '{
if (`M_SUPPORTED) tests = {tests, tests64m};
if (`F_SUPPORTED) tests = {tests64f, tests};
if (`D_SUPPORTED) tests = {tests64d, tests};
if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
if (`VIRTMEM_SUPPORTED) tests = {tests64mmu, tests};
if (`A_SUPPORTED) tests = {tests64a, tests};
end
//tests = {tests64a, tests};
@ -565,7 +565,7 @@ string tests32f[] = '{
else tests = {tests, tests32iNOc};
if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
if (`F_SUPPORTED) tests = {tests32f, tests};
if (`MEM_VIRTMEM) tests = {tests32mmu, tests};
if (`VIRTMEM_SUPPORTED) tests = {tests32mmu, tests};
if (`A_SUPPORTED) tests = {tests32a, tests};
end
end
@ -782,17 +782,17 @@ module riscvassertions();
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double without supporting float");
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS) else $error("DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS) else $error("ICACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (`ICACHE_NUMWAYS == 1 | `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
assert (`ICACHE_NUMWAYS == 1 | (`IMEM != `MEM_CACHE)) else $warning("Multiple Instruction Cache ways not yet implemented");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
assert (`RAM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
@ -836,10 +836,10 @@ module DCacheFlushFSM
copyShadow #(.tagstart(tagstart), .loglinebytelen(loglinebytelen))
copyShadow(.clk,
.start,
.tag(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].CacheTagMem.StoredData[index]),
.valid(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].ValidBits[index]),
.dirty(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].DirtyBits[index]),
.data(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
.tag(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].CacheTagMem.StoredData[index]),
.valid(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].ValidBits[index]),
.dirty(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].DirtyBits[index]),
.data(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]),
.index(index),
.cacheWord(cacheWord),
.CacheData(CacheData[way][index][cacheWord]),

6
pipelined/testbench/testbench-linux.sv
View File

@ -4,7 +4,7 @@
// Written: nboorstin@g.hmc.edu 2021
// Modified:
//
// Purpose: Testbench for buildroot or busybear linux
// Purpose: Testbench for Buildroot Linux
//
// A component of the Wally configurable RISC-V project.
//
@ -186,8 +186,8 @@ module testbench;
`define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q
`define MEPC `CSR_BASE.csrm.MEPCreg.q
`define SEPC `CSR_BASE.csrs.csrs.SEPCreg.q
`define MCOUNTEREN `CSR_BASE.csrm.counters.MCOUNTERENreg.q
`define SCOUNTEREN `CSR_BASE.csrs.csrs.scounteren.SCOUNTERENreg.q
`define MCOUNTEREN `CSR_BASE.csrm.MCOUNTERENreg.q
`define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q
`define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q
`define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q
`define MTVEC `CSR_BASE.csrm.MTVECreg.q

476
pipelined/testbench/testbench-tim.sv
View File

@ -1,476 +0,0 @@
///////////////////////////////////////////
// testbench.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Wally Testbench and helper modules
// Applies test programs from the riscv-arch-test and Imperas suites
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// MIT LICENSE
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
// to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
`include "tests.vh"
module testbench;
parameter TESTSPERIPH = 0; // set to 0 for regression
parameter TESTSPRIV = 0; // set to 0 for regression
parameter DEBUG=0;
parameter TEST="none";
logic clk;
logic reset_ext, reset;
parameter SIGNATURESIZE = 5000000;
int test, i, errors, totalerrors;
logic [31:0] sig32[0:SIGNATURESIZE];
logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
logic [`XLEN-1:0] testadr;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW;
logic [`XLEN-1:0] meminit;
string tests[];
logic [3:0] dummy;
string ProgramAddrMapFile, ProgramLabelMapFile;
logic [`AHBW-1:0] HRDATAEXT;
logic HREADYEXT, HRESPEXT;
logic [31:0] HADDR;
logic [`AHBW-1:0] HWDATA;
logic HWRITE;
logic [2:0] HSIZE;
logic [2:0] HBURST;
logic [3:0] HPROT;
logic [1:0] HTRANS;
logic HMASTLOCK;
logic HCLK, HRESETn;
logic [`XLEN-1:0] PCW;
logic DCacheFlushDone, DCacheFlushStart;
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
// check assertions for a legal configuration
riscvassertions riscvassertions();
// pick tests based on modes supported
initial begin
$display("TEST is %s", TEST);
//tests = '{};
if (`XLEN == 64) begin // RV64
case (TEST)
"arch64i": tests = arch64i;
"arch64priv": tests = arch64priv;
"arch64c": if (`C_SUPPORTED)
if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
else tests = {arch64c};
"arch64m": if (`M_SUPPORTED) tests = arch64m;
"arch64d": if (`D_SUPPORTED) tests = arch64d;
"imperas64i": tests = imperas64i;
"imperas64p": tests = imperas64p;
// "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
"imperas64m": if (`M_SUPPORTED) tests = imperas64m;
"imperas64a": if (`A_SUPPORTED) tests = imperas64a;
"imperas64c": if (`C_SUPPORTED) tests = imperas64c;
else tests = imperas64iNOc;
"testsBP64": tests = testsBP64;
"wally64i": tests = wally64i; // *** redo
"wally64priv": tests = wally64priv;// *** redo
"imperas64periph": tests = imperas64periph;
endcase
end else begin // RV32
case (TEST)
"arch32i": tests = arch32i;
"arch32priv": tests = arch32priv;
"arch32c": if (`C_SUPPORTED)
if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
else tests = {arch32c};
"arch32m": if (`M_SUPPORTED) tests = arch32m;
"arch32f": if (`F_SUPPORTED) tests = arch32f;
"imperas32i": tests = imperas32i;
"imperas32p": tests = imperas32p;
// "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
"imperas32a": if (`A_SUPPORTED) tests = imperas32a;
"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
else tests = imperas32iNOc;
"wally32i": tests = wally32i; // *** redo
"wally32priv": tests = wally32priv; // *** redo
"imperas32periph": tests = imperas32periph;
endcase
end
if (tests.size() == 0) begin
$display("TEST %s not supported in this configuration", TEST);
$stop;
end
end
string signame, memfilename, pathname;
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
logic UARTSin, UARTSout;
logic SDCCLK;
logic SDCCmdIn;
logic SDCCmdOut;
logic SDCCmdOE;
logic [3:0] SDCDatIn;
logic HREADY;
logic HSELEXT;
// instantiate device to be tested
assign GPIOPinsIn = 0;
assign UARTSin = 1;
assign HREADYEXT = 1;
assign HRESPEXT = 0;
assign HRDATAEXT = 0;
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
// Track names of instructions
instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
dut.core.ifu.FinalInstrRawF,
dut.core.ifu.InstrD, dut.core.ifu.InstrE,
dut.core.ifu.InstrM, InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// initialize tests
localparam integer MemStartAddr = `RAM_BASE>>(1+`XLEN/32);
localparam integer MemEndAddr = (`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32);
initial
begin
test = 1;
totalerrors = 0;
testadr = 0;
// fill memory with defined values to reduce Xs in simulation
// Quick note the memory will need to be initialized. The C library does not
// guarantee the initialized reads. For example a strcmp can read 6 byte
// strings, but uses a load double to read them in. If the last 2 bytes are
// not initialized the compare results in an 'x' which propagates through
// the design.
if (`XLEN == 32) meminit = 32'hFEDC0123;
else meminit = 64'hFEDCBA9876543210;
// *** broken because DTIM also drives RAM
if (`TESTSBP) begin
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
dut.uncore.ram.ram.RAM[i] = meminit;
end
end
// read test vectors into memory
pathname = tvpaths[tests[0].atoi()];
/* if (tests[0] == `IMPERASTEST)
pathname = tvpaths[0];
else pathname = tvpaths[1]; */
memfilename = {pathname, tests[test], ".elf.memfile"};
//$readmemh(memfilename, dut.uncore.ram.ram.RAM);
$readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
// if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
//`ifdef `MEM_IROM
// $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
// $readmemh(memfilename, dut.core.ifu.irom.ram.RAM);
//`endif
// if(`MEM_IROM == 1) begin
// $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
$readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM);
// end
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
$display("Read memfile %s", memfilename);
reset_ext = 1; # 42; reset_ext = 0;
end
// generate clock to sequence tests
always
begin
clk = 1; # 5; clk = 0; # 5;
// if ($time % 100000 == 0) $display("Time is %0t", $time);
end
// check results
always @(negedge clk)
begin
if (DCacheFlushDone) begin
#600; // give time for instructions in pipeline to finish
// clear signature to prevent contamination from previous tests
for(i=0; i<SIGNATURESIZE; i=i+1) begin
sig32[i] = 'bx;
end
// read signature, reformat in 64 bits if necessary
signame = {pathname, tests[test], ".signature.output"};
$readmemh(signame, sig32);
i = 0;
while (i < SIGNATURESIZE) begin
if (`XLEN == 32) begin
signature[i] = sig32[i];
i = i+1;
end else begin
signature[i/2] = {sig32[i+1], sig32[i]};
i = i + 2;
end
if (sig32[i-1] === 'bx) begin
if (i == 1) begin
i = SIGNATURESIZE+1; // flag empty file
$display(" Error: empty test file");
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
end
end
// Check errors
errors = (i == SIGNATURESIZE+1); // error if file is empty
i = 0;
testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8);
/* verilator lint_off INFINITELOOP */
while (signature[i] !== 'bx) begin
//$display("signature[%h] = %h", i, signature[i]);
// *** have to figure out how to exclude shadowram when not using a dcache.
if (signature[i] !== dut.core.lsu.dtim.dtim.ram.RAM[testadr+i] &
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
// report errors unless they are garbage at the end of the sim
// kind of hacky test for garbage right now
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
//tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]);
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.dtim.ram.RAM[testadr+i], signature[i]);
$stop;//***debug
end
end
i = i + 1;
end
/* verilator lint_on INFINITELOOP */
if (errors == 0) begin
$display("%s succeeded. Brilliant!!!", tests[test]);
end
else begin
$display("%s failed with %d errors. :(", tests[test], errors);
totalerrors = totalerrors+1;
end
test = test + 2;
if (test == tests.size()) begin
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
else $display("FAIL: %d test programs had errors", totalerrors);
$stop;
end
else begin
//pathname = tvpaths[tests[0]];
memfilename = {pathname, tests[test], ".elf.memfile"};
//$readmemh(memfilename, dut.uncore.ram.ram.RAM);
$readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
//if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
/* -----\/----- EXCLUDED -----\/-----
`ifdef `MEM_IROM
$display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
$readmemh(memfilename, dut.core.ifu.irom.ram.RAM);
`endif
-----/\----- EXCLUDED -----/\----- */
$readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM);
//if(`MEM_IROM == 1) $readmemh(memfilename, dut.core.ifu.irom.ram.RAM);
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
$display("Read memfile %s", memfilename);
reset_ext = 1; # 47; reset_ext = 0;
end
end
end // always @ (negedge clk)
// track the current function or global label
if (DEBUG == 1) begin : FunctionName
FunctionName FunctionName(.reset(reset),
.clk(clk),
.ProgramAddrMapFile(ProgramAddrMapFile),
.ProgramLabelMapFile(ProgramLabelMapFile));
end
// Termination condition
// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
// or sw gp,-56(t0) for new Imperas tests
// or sd gp, -56(t0)
// or on a jump to self infinite loop (6f) for RISC-V Arch tests
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
else assign ecf = 0;
assign DCacheFlushStart = ecf &
(dut.core.ieu.dp.regf.rf[3] == 1 |
(dut.core.ieu.dp.regf.we3 &
dut.core.ieu.dp.regf.a3 == 3 &
dut.core.ieu.dp.regf.wd3 == 1)) |
(dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM;
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
.reset(reset),
.start(DCacheFlushStart),
.done(DCacheFlushDone));
// initialize the branch predictor
if (`BPRED_ENABLED == 1)
initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
end
endmodule
module riscvassertions;
initial begin
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
assert (`S_SUPPORTED | `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support");
assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | `MEM_DCACHE==0) else $error("DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | `MEM_ICACHE==0) else $error("ICACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2");
assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported.");
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
end
endmodule
/* verilator lint_on STMTDLY */
/* verilator lint_on WIDTH */
module DCacheFlushFSM
(input logic clk,
input logic reset,
input logic start,
output logic done);
genvar adr;
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
if(`MEM_DCACHE) begin
localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN;
localparam integer lognumlines = $clog2(numlines);
localparam integer loglinebytelen = $clog2(linebytelen);
localparam integer lognumways = $clog2(numways);
localparam integer tagstart = lognumlines + loglinebytelen;
genvar index, way, cacheWord;
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
for(index = 0; index < numlines; index++) begin
for(way = 0; way < numways; way++) begin
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
copyShadow #(.tagstart(tagstart),
.loglinebytelen(loglinebytelen))
copyShadow(.clk,
.start,
.tag(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
.valid(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].ValidBits[index]),
.dirty(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].DirtyBits[index]),
.data(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
.index(index),
.cacheWord(cacheWord),
.CacheData(CacheData[way][index][cacheWord]),
.CacheAdr(CacheAdr[way][index][cacheWord]),
.CacheTag(CacheTag[way][index][cacheWord]),
.CacheValid(CacheValid[way][index][cacheWord]),
.CacheDirty(CacheDirty[way][index][cacheWord]));
end
end
end
integer i, j, k;
always @(posedge clk) begin
if (start) begin #1
#1
for(i = 0; i < numlines; i++) begin
for(j = 0; j < numways; j++) begin
for(k = 0; k < numwords; k++) begin
if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
end
end
end
end
end
end
end
flop #(1) doneReg(.clk, .d(start), .q(done));
endmodule
module copyShadow
#(parameter tagstart, loglinebytelen)
(input logic clk,
input logic start,
input logic [`PA_BITS-1:tagstart] tag,
input logic valid, dirty,
input logic [`XLEN-1:0] data,
input logic [32-1:0] index,
input logic [32-1:0] cacheWord,
output logic [`XLEN-1:0] CacheData,
output logic [`PA_BITS-1:0] CacheAdr,
output logic [`XLEN-1:0] CacheTag,
output logic CacheValid,
output logic CacheDirty);
always_ff @(posedge clk) begin
if(start) begin
CacheTag = tag;
CacheValid = valid;
CacheDirty = dirty;
CacheData = data;
CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8));
end
end
endmodule

104
pipelined/testbench/testbench.sv
View File

@ -49,8 +49,6 @@ module testbench;
logic [`XLEN-1:0] testadr;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW;
logic [`XLEN-1:0] meminit;
string tests[];
logic [3:0] dummy;
@ -92,7 +90,7 @@ logic [3:0] dummy;
"arch64d": if (`D_SUPPORTED) tests = arch64d;
"imperas64i": tests = imperas64i;
"imperas64p": tests = imperas64p;
// "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
// "imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu;
"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
"imperas64m": if (`M_SUPPORTED) tests = imperas64m;
@ -102,7 +100,8 @@ logic [3:0] dummy;
"testsBP64": tests = testsBP64;
"wally64i": tests = wally64i; // *** redo
"wally64priv": tests = wally64priv;// *** redo
"imperas64periph": tests = imperas64periph;
"imperas64periph": tests = imperas64periph;
"coremark": tests = coremark;
endcase
end else begin // RV32
case (TEST)
@ -115,13 +114,14 @@ logic [3:0] dummy;
"arch32f": if (`F_SUPPORTED) tests = arch32f;
"imperas32i": tests = imperas32i;
"imperas32p": tests = imperas32p;
// "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
// "imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu;
"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
"imperas32a": if (`A_SUPPORTED) tests = imperas32a;
"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
else tests = imperas32iNOc;
"wally32i": tests = wally32i; // *** redo
"wally32e": tests = wally32e;
"wally32priv": tests = wally32priv; // *** redo
"imperas32periph": tests = imperas32periph;
endcase
@ -161,7 +161,7 @@ logic [3:0] dummy;
// Track names of instructions
instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
dut.core.ifu.FinalInstrRawF,
dut.core.ifu.FinalInstrRawF[31:0],
dut.core.ifu.InstrD, dut.core.ifu.InstrE,
dut.core.ifu.InstrM, InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
@ -181,22 +181,20 @@ logic [3:0] dummy;
// strings, but uses a load double to read them in. If the last 2 bytes are
// not initialized the compare results in an 'x' which propagates through
// the design.
if (`XLEN == 32) meminit = 32'hFEDC0123;
else meminit = 64'hFEDCBA9876543210;
// *** broken because DTIM also drives RAM
if (`TESTSBP) begin
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
dut.uncore.ram.ram.RAM[i] = meminit;
end
end
if (TEST == "coremark")
for (i=MemStartAddr; i<MemEndAddr; i = i+1)
dut.uncore.ram.ram.RAM[i] = 64'h0;
// read test vectors into memory
pathname = tvpaths[tests[0].atoi()];
/* if (tests[0] == `IMPERASTEST)
pathname = tvpaths[0];
else pathname = tvpaths[1]; */
memfilename = {pathname, tests[test], ".elf.memfile"};
$readmemh(memfilename, dut.uncore.ram.ram.RAM);
//if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM);
else $readmemh(memfilename, dut.uncore.ram.ram.RAM);
if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
$display("Read memfile %s", memfilename);
@ -213,6 +211,11 @@ logic [3:0] dummy;
// check results
always @(negedge clk)
begin
if (TEST == "coremark")
if (dut.core.priv.priv.ecallM) begin
$display("Benchmark: coremark is done.");
$stop;
end
if (DCacheFlushDone) begin
#600; // give time for instructions in pipeline to finish
@ -233,8 +236,8 @@ logic [3:0] dummy;
signature[i/2] = {sig32[i+1], sig32[i]};
i = i + 2;
end
if (sig32[i-1] === 'bx) begin
if (i == 1) begin
if (i >= 4 & sig32[i-4] === 'bx) begin
if (i == 4) begin
i = SIGNATURESIZE+1; // flag empty file
$display(" Error: empty test file");
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
@ -247,17 +250,21 @@ logic [3:0] dummy;
testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8);
/* verilator lint_off INFINITELOOP */
while (signature[i] !== 'bx) begin
//$display("signature[%h] = %h", i, signature[i]);
// *** have to figure out how to exclude shadowram when not using a dcache.
if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] &
logic [`XLEN-1:0] sig;
if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadr+i];
else sig = dut.uncore.ram.ram.RAM[testadr+i];
// $display("signature[%h] = %h sig = %h", i, signature[i], sig);
if (signature[i] !== sig &
//if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] &
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin // ***i+1?
if ((signature[i] !== '0 | signature[i+4] !== 'x)) begin
// if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin
// report errors unless they are garbage at the end of the sim
// kind of hacky test for garbage right now
$display("sig4 = %h ne %b", signature[i+4], signature[i+4] !== 'bx);
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]);
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DMEM) = %h, signature = %h",
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
// tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.ram.RAM[testadr+i], signature[i]);
$stop;//***debug
end
@ -281,8 +288,11 @@ logic [3:0] dummy;
else begin
//pathname = tvpaths[tests[0]];
memfilename = {pathname, tests[test], ".elf.memfile"};
$readmemh(memfilename, dut.uncore.ram.ram.RAM);
//if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
//$readmemh(memfilename, dut.uncore.ram.ram.RAM);
if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM);
else $readmemh(memfilename, dut.uncore.ram.ram.RAM);
if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
$display("Read memfile %s", memfilename);
@ -330,30 +340,30 @@ endmodule
module riscvassertions;
initial begin
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
assert (`S_SUPPORTED | `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support");
assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | `MEM_DCACHE==0) else $error("DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | `MEM_ICACHE==0) else $error("ICACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (`DMEM != `MEM_CACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (`IMEM != `MEM_CACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported.");
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
assert (`MEM_DTIM == 0 | `MEM_VIRTMEM ==0) else $error("DTIM doesn't play nicely with virtual memory");
assert (`MEM_IROM == 0 | `MEM_VIRTMEM ==0) else $error("IROM doesn't play nicely with virtual memory");
// assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
end
endmodule
@ -371,7 +381,7 @@ module DCacheFlushFSM
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
if(`MEM_DCACHE) begin
if(`DMEM == `MEM_CACHE) begin
localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
@ -396,10 +406,10 @@ module DCacheFlushFSM
.loglinebytelen(loglinebytelen))
copyShadow(.clk,
.start,
.tag(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
.valid(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].ValidBits[index]),
.dirty(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].DirtyBits[index]),
.data(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]),
.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]),
.index(index),
.cacheWord(cacheWord),
.CacheData(CacheData[way][index][cacheWord]),

1458
pipelined/testbench/tests.vh
View File

File diff suppressed because it is too large Load Diff

4
synthDC/.synopsys_dc.setup
View File

@ -3,7 +3,7 @@
set CURRENT_DIR [exec pwd]
set search_path [list "./" ]
set s8lib ../addins/sky130_osu_sc_t18/18T_ms/lib
set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib
lappend search_path $s8lib
# Synthetic libraries
@ -12,7 +12,7 @@ set synthetic_library [list dw_foundation.sldb]
# Set OKSTATE standard cell libraries
set target_library [list]
lappend target_library sky130_osu_sc_18T_ms_TT_1P8_25C.ccs.db
lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db
# Set Link Library
set link_library "$target_library $synthetic_library"

62
synthDC/hdl/wally-shared.vh Normal file
View File

@ -0,0 +1,62 @@
//////////////////////////////////////////
// wally-shared.vh
//
// Written: david_harris@hmc.edu 7 June 2021
//
// Purpose: Shared and default configuration values common to all designs
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// include shared constants
`include "wally-constants.vh"
// macros to define supported modes
// NOTE: No hardware support fo Q yet
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
// logarithm of XLEN, used for number of index bits to select
`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
`define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
`define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
// Disable spurious Verilator warnings
/* verilator lint_off STMTDLY */
/* verilator lint_off ASSIGNDLY */
/* verilator lint_off PINCONNECTEMPTY */

18
synthDC/scripts/synth.tcl
View File

@ -6,11 +6,11 @@
# Config
set hdl_src "../pipelined/src"
eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {hdl/}
eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {reports/}
eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/}
eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {hdl/}
eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {reports/}
eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
# Verilog files
set my_verilog_files [glob hdl/*]
@ -47,7 +47,7 @@ reset_design
# Set Frequency in [MHz] or [ps]
set my_clock_pin clk
set my_clk_freq_MHz 10
set my_clk_freq_MHz 500
set my_period [expr 1000 / $my_clk_freq_MHz]
set my_uncertainty [expr .1 * $my_period]
@ -76,14 +76,14 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
set_propagated_clock [get_clocks $my_clk]
# Setting constraints on input ports
set_driving_cell -lib_cell sky130_osu_sc_18T_ms__dff_1 -pin Q $all_in_ex_clk
set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
# Set input/output delay
set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
set_output_delay 0.0 -max -clock $my_clk [all_outputs]
# Setting load constraint on output ports
set_load [expr [load_of sky130_osu_sc_18T_ms_TT_1P8_25C.ccs/sky130_osu_sc_18T_ms__dff_1/D] * 1] [all_outputs]
set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
# Set the wire load model
set_wire_load_mode "top"
@ -111,7 +111,7 @@ write_file -format ddc -hierarchy -o $filename
# Compile statements - either compile or compile_ultra
# compile -scan -incr -map_effort low
# compile_ultra -no_seq_output_inversion -no_boundary_optimization
compile_ultra -no_seq_output_inversion -no_boundary_optimization
# Eliminate need for assign statements (yuck!)
set verilogout_no_tri true

3
tests/linux-testgen/buildroot-config-src/make-buildroot.sh
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@ -1,3 +0,0 @@
cp main.config ../buildroot/.config
cd ../buildroot
make

413
tests/wally-riscv-arch-test/CHANGELOG.md
View File

@ -1,413 +0,0 @@
# CHANGELOG
## [2.5.3] - 2021-10-15
- fix the lower case `i` in the `RVTEST_CASE` macros used in the shift operation tests.
## [2.5.2] - 2021-10-14
- update format for aes32 and sm4 instructions
- update reference signature for sha256 and sm3 instructions in rv64i_m/K_unratified
- delete zip and unzip tests in rv64i_m/K_unratified
- update tests for aes64ks1i, sm4ed and sm4ks to use byte_count with overlap = "Y" to improve the coverage of S-boxes
## [2.5.1] - 2021-10-07
- added styles files to the F coverage report directories.
## [2.5.0] - 2021-10-01
- Added rv32f tests, references, coverage files and data propagation reports
- fixed broken links in READMEs across the repo.
- corrected string "EBREAK" in io string macro to "ECALL" for ecall.S tests. #207
- fixed typo `.alive` --> `.align` in `riscv-target/example_target/model_test.h`.
## [2.4.7] - 2021-10-01
- Fix for the issue #206
## [2.4.6] - 2021-08-02
- Added rv32e tests in riscv-test-suite
## [2.4.5] - 2021-07-29
- fix for issue #195
## [2.4.4] - 2021-07-19
- Annotating tags during releases
## [2.4.3] - 2021-05-20
- added new 64-bit K crypto tests as per the test-plan presented by the scalar crypto task group
[here](https://github.com/riscv/riscv-crypto/blob/d89dfee25780f79c162da4eb69cd9076dd701c88/tests/compliance/test-plan-scalar.adoc)
- added new 32-bit K crypto tests as per the above mentioned test-plan.
- added coverage and data propagation reports for the above tests.
- updated README in riscv-test-suite
- added missing semi-colon in example target Makefile.include files
## [2.4.2] - 2021-04-20
- changed all occurances of SPTBR to the new name SATP
## [2.4.1] - 2021-04-01
- updated issue number in TestFormatSpec to be consistent with doc history
- adding a contribution guideline
- updated comment on usage of RISCV_DEVICE in Makefile.include
- updated licenses that are currently used by tests
- renamed K tests to K_unratified
- updated ci to build and upload pdf for testformatspec
## [2.4.0] - 2021-03-26
2021-03-26 Duncan Graham <info@imperas.com>
- Added new K Crypto (scalar) (0.8.1) tests from Imperas
## [2.3.1] - 2021-03-20
### Changed
- Compliance Task Group changed to Architecture Test SIG in all docs and comments
- replacing old riscv-compliance link with new riscv-arch-test links
- fixed ci for release
### Removed
- spec/TestFormatSpec.pdf is removed since its old. Keeping only adoc file
- removing obsolete and commented out portions from doc/README
## [2.3] - 2021-03-11
### Added
- updated maintainers list in root-level readme
- updated the links to riscof, isac and ctg repos and docs in root-level readme
- adding CI to update versions automatically
### Removed
- replaced spike target with a REAMDE pointing to riscv-isa-sim/arch_test_target/README.md
## [2.2] - 2021-01-28
2021-01-22 Tobias Wölfel <tobias.woelfel@mailbox.org>
* Add missing base ISA check in riscv-test-suite
2021-01-20 Xiretza <xiretza@xiretza.xyz>
* Deduplicate makefiles in riscv-test-suite
* Makefile: Fix ordering of simulate and verify targets to allow multi-job runs (make -j)
* Makefile.include: Document RISCV_TEST
* Makefile: use $(TARGETDIR) variable for postverify target instead of hard-coded path
2021-01-16 S Pawan Kumar <spawan1999@gmail.com>
* Fixed NARGS macro defintion to work correctly.
2021-01-15 Xiretza <xiretza@xiretza.xyz>
* style: Add a missing space to the "OK" message in verify.sh
2020-12-17 Neel Gala <neelgala@incoresemi.com>
* remove env folder symlinks from all riscv-test-suite src folders
* fixed assertion macros for ovpsim
* renamed RVTEST_ASSERT to RVMODEL_ASSERT in the Makefile and ovpsim macros
* tests updated with right set of "correctvals"
2020-11-24 Neel Gala <neelgala@incoresemi.com>
* added MIGRATION.adoc in doc directory to indicate how old framework targets can work with
changes made as part of this PR
* updated doc/README.adoc to avoid the word "compliance" and updated the section on porting a new
target to the framework.
* Added an example_target directory to host dummy files which can be used as a starting point for
porting targets. This was provided by MarcKarasek.
* migrated/ported existing targets (except codasip and sifive-formal) to the new framework
changes.
* in riscv-test-env/p/riscv_test.h changed names of RVTEST_[CODE/DATA]_[BEGIN/END] to
RVTEST_[CODE/DATA]_[BEGIN/END]_OLD respectively to avoid conflicts with the new framework macros.
* in riscv-test-env/p/riscv_test.h re-strutucture RVTEST_DATA_BEGIN_OLD/END to ensure that all
target specific data contents are introduced in RVTEST_DATA_END after the signature.
* added new file riscv-test-suite/env/arch_test.h which contains the macros used by the new set of
tests. A symlink to this in the riscv-test-env directory is also created. The arch_test also
includes aliases for the old macros.
* encoding.h moved to riscv-test-suite/env and a symlink to this file exists in riscv-test-env.
This was done to ensure that the arch_test.h and encoding.h are not to be modified by the
targets
* Added riscv-test-stats which includes coverage and data propagation reports for the tests
available in the riscv-test-suite directory.
* upddted the directory structure of the riscv-test-suite as per definition found in the
TestFormatSpec document.
* new set of tests with better coverage for rv[32/64][I,M,C, Zifencei] added. Almost all tests
were generated using the open source riscv_ctg tool. A few tests like fence, fencei, ebreak,
ecall, etc were handwritten/modified to follow the new macro conventions.
* Updated TestFormatSpec to avoid the word compliance and also updated the definitions of macros
and signatures
* created a root-level Makefile.include to decouple the Makefile and target specific settings.
* Added riscv-target and Makefile.include to the .gitignore file to stop tracking target specific
changes.
* Added special targets for compile(build), simulate(run) and verify in the Makefiles of each
test-suite.
* the existing riscv-targets have been either updated for the new framework or migrated to the
framework.
2020-10-15 Simon Davidmann <simond@imperas.com>
* riscvOVPsim enhanced and moved to its own respository: github.com/riscv-ovpsim
2020-04-24 Allen Baum <allen.baum@esperantotech.com>
* fixed the I-SB-01.S and I-SH-01.S tests and associated reference signatures to account
of tests with negative offsets (which causes stores outside the signature area)
2020-03-19 Neel Gala <neelgala@gmail.com>
* restructuring the riscv-test-suite to indicate clearly what is deprecated, wip and usable
tests.
* based on the above fixed the directory structure for riscv-targets where-ever applicable. Only
tested riscvOVPsim and spike.
* fixed script bugs for spike as well
* renamed rv32i/I-IO.S to rv32i/I-IO-01.S along with necessary changes to the reference files
and Makefrag
* renamed mbadaddr csr to mtval as raised in issue #31
* C.SWSP-01.S test updated to fix issue #37
2020-03-18 Neel Gala <neelgala@gmail.com>
* fixed doc/README.adoc with correct version to pass the sanity-check in the doc/Makefile
2020-02-07 Prashanth Mundkur <prashanth.mundkur@gmail.com>
* Support F extension on RV32 sail-riscv-c.
2019-12-01 Allen Baum <allen.baum@esperantotech.com>
* modified macro names to conformn to riscof naming convention of model specific vs. pre-defined
* add more complete list of macros, their uses, parameters, and whether they are required or optional
* minor structural changes (moving sentences, renumbering) and typo fixes
* clarified impact of debug macros
* clarified how SIGUPD and BASEUPD must be used
* remove section about test taxonomy, binary tests, emulated ops
* clarify/fix boundary between test target and framework responsibilities
(split test target into test target and test shell)
* remove To Be discussed items that have been discussed
* remove default case condition; if conditions are unchanged, part of same case
* minor grammatical changes related to the above
2019-10-16 Allen Baum <allen.baum@esperantotech.com>
* spec/TestFormatSpec.adoc: changed the format of the signature to fixed physical address size, fixed 32b data size extracted from COMPLIANCE_DATA_BEGIN/END range.
* more gramatical fixes, clarifications added
* added To Be Discussed items regarding emulated instruction and binary tests
2019-09-11 Allen Baum <allen.baum@esperantotech.com>
* spec/TestFormatSpec.adoc: more grammar and typo corrections and changes
clarified and added To Be Discussed issues
2019-09-11 Allen Baum <allen.baum@esperantotech.com>
* spec/TestFormatSpec.adoc: many grammar and typo corrections and changes
removed many "to Be Discussed items and made them official
Added wording to clarify spec intent (work in progress/goal rather than final)
Added macros to ease test authoring: RVTEST_SIGBASE, RVTEST_SIGUPDATE, RVTEST_CASE
Added detail on proposals for connection to framework (how framework selects tests).
Expanded definition of signature format
Changed the (proposed) directory structure and naming convention to eliminate ambiguities, add consistancy and slightly better match existing structure
Added many "future work" items related to the above
Added examples and comments to code examples to indicate how proposed macros would be used
* .gitignore: added condition to ignore Mac file system artifacts
2019-11-05 Lee Moore <moore@imperas.com>
* Restructured RV32I to move Zicsr and Zifencei into their own suites
2019-10-14 Lee Moore <moore@imperas.com>
* Added Ability to run a single test by using the Make Variable RISCV_TEST
for example, to only run the test I-ADD-01 from the rv32i suite
make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01
* Added Top Level Variable to Makefile RISCV_TARGET_FLAGS,
in the case of the RISCV_TARGET this can be passed and appended to the invocation
commandline configuration, for example to pass a command line flag to the RISCV_TARGET
to perform tracing. The value of this flag will be target specific
make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 RISCV_TARGET_FLAGS="--trace"
This is has also been added to all other targets to allow target configuration from
the commandline
2019-10-07 Philipp Wagner <phw@lowrisc.org>
* When executing the test suite, Ibex always writes an instruction
log. Update the Makefile to write it to a test-specific location
(next to all other log files).
* On Ibex, provide an additional .objdump-noalias disassembly file
with no aliases and numeric register names (instead of ABI names).
This file matches the Ibex trace and can be used to debug the test
runs.
2019-08-29 Robert Balas <balasr@iis.ee.ethz.ch>
* Added support for using RI5CY as a target.
* Added subdirectory riscv-target/ri5cy
2019-08-08 Lee Moore <moore@imperas.com>
* Added support for lowRISC/ibex RTL as a target using Verilator.
In conjunction with Philipp Wagner of lowRISC phw@lowrisc.org
2019-07-18 Paul Donahue <pdonahue@ventanamicro.com>
* Fix typos/grammar and use correct architectural terms.
2019-06-21 Ben Selfridge <benselfridge@galois.com>
* Added support for using the the GRIFT simulator as a target.
* Added subdirectory riscv-target/grift
* updated README.md and doc/README.adoc
2019-05-23 Prashanth Mundkur <prashanth.mundkur@gmail.com>
* Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets.
* added subdirectories riscv-target/sail-riscv-c and riscv-target/sail-riscv-ocaml
* updated README.md and doc/README.adoc
2019-04-05 Allen Baum <allen.baum@esperantotech.com>
* spec/TestFormatSpec.adoc: Adding details, minor corrections, ToBeDiscussed
items and clarifications to the specification of the future compliance test
suite. Also removing restrictions on having absolate addresses in signature
2019-02-21 Lee Moore <moore@imperas.com>
* Fixed bug in RVTEST_IO_ASSERT_GPR_EQ which was not preserving register t0
* Corrected commit I-LUI-01.S, register target changed but missed assertion
2019-02-21 Deborah Soung <debs@sifive.com>
* added RiscvFormalSpec as a target with its own unique environment
2019-02-15 Radek Hajek <radek.hajek@codasip.com>
* updated rv32i tests to support all registers (x31) with assertions
* updated spec/TestFormatSpec.adoc example ISA test with new assertions
2019-02-05 Deborah Soung <debs@sifive.com>
* [Issue #33] fixing rv32si/ma_fetch.S test
* [Issue #32] fixing breakpoint test
2019-02-01 Lee Moore <moore@imperas.com>
* updated Infrastructure macros to support non-volatile registers
* updated riscvOVPsim
2019-01-29 Deborah Soung <debs@sifive.com>
* Added Rocket Chip generated cores as a target
* riscv-target/rocket/compliance_io.h created
* riscv-target/rocket/compliance_test.h created
* riscv-target/rocket/*/Makefile.include created for existing test suites
* README.adoc updated with instructions for using Rocket cores as targets
2019-01-22 Premysl Vaclavik <pvaclavik@codasip.com>
* feature: initial version of Compliance Test Format Specification
* This new document outlines how we should like the compliance
system to work going forward. By contrast the doc/README.adoc file
describes the current system as it is.
* Approved at Compliance TG meeting of 9 Jan 2019.
2019-01-02 Radek Hajek <radek.hajek@codasip.com>
* unified macros in all compliance tests
2018-12-20 Lee Moore <moore@imperas.com>
* fixed riscvOVPsim
2018-11-22 Simon Davidmann <simond@imperas.com>
* added information on test suite status
2018-11-21 Olof Kindgren <olof.kindgren@gmail.com>
* Added support for using external target directories with $TARGETDIR
2018-11-21 Neel Gala <neelgala@incoresemi.com>
* riscv-test-suite/rv_/references/_.reference_output: changed signature
format for all tests to include only 4-bytes per line starting with the
most significant byte on the left.
* riscv-target/spike/device/rv_/Makefile.include: Added a patch for
spike-device Makefiles where the old-signature format is post-processed
to generate a signature in the new format at the end of each test.
* riscv-target/riscvOVPsim/device/rv_/Makefile.include: same patch as above.
* Makefile: default target for Makefile is now to run all tests supported by
the target mentioned defined by RISCV_TARGET variable.
2018-10-11 Simon Davidmann <simond@imperas.com>
* Ported github riscv/riscv-tests for RV32 processors to this compliance env
* rv32ua rv32uc rv32ud rv32uf rv32ud rv32ui
2018-09-10 Lee Moore <moore@imperas.com>
* Added tests to RV32I to improve coverage, usage of Imperas Mutating Fault Simulator to
identify untested usage cases
* Macro renames to support GPR, (S)FPR, (D)FPR
* Added test suite RV32IM to test 32 bit Multiply and Divide instructions
* Added test suite RV32IMC to test 32 bit Compressed instructions
* Added test suite RV64I to test 64 bit Integer instructions
* Added test suite RV64IM to test 64 bit Multiply and Divide instructions
2018-06-15 Radek Hajek <hajek@codasip.com>
Modifications to support Codasip simulator.
The simulator is renamed as Codasip-simulator (was
Codasip-IA-simulator), compliance_test.h has been moved to target
directories and a COMPILE_TARGET has been added to Makefile to
allow use of LLVM.
* Makefile: Include Codasip simulator target.
* riscv-target/codasip-IA-simulator/compliance_io.h: Renamed as
riscv-target/Codasip-simulator/compliance_io.h.
* riscv-target/Codasip-simulator/compliance_io.h: Renamed from
riscv-target/codasip-IA-simulator/compliance_io.
* riscv-target/Codasip-simulator/compliance_test.h: Created.
* riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include:
Renamed as
riscv-target/Codasip-simulator/device/rv32i/Makefile.include
* riscv-target/Codasip-simulator/device/rv32i/Makefile.include:
Renamed from
riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include.
* riscv-test-env/compliance_test.h: Renamed as
riscv-target/riscvOVPsim/compliance_test.h.
* riscv-target/riscvOVPsim/compliance_test.h: Renamed from
riscv-test-env/compliance_test.h.
* riscv-target/riscvOVPsim/device/rv32i/Makefile.include: Updated
for new environment.
* riscv-target/spike/compliance_test.h: Created.
* riscv-target/spike/device/rv32i/Makefile.include: Updated for
new environment.
* riscv-test-suite/rv32i/Makefile: Likewise.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
Put placeholders in empty directories to make sure they show in
the GitHub hierarchy.
* riscv-test-suite/rv32i/.gitignore: Created.
* riscv-test-suite/rv32m/.gitignore: Created.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Make references to files in the repo into links.
2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* .gitignore: Ignore editor backup files.
2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Add better link to documentation README.md.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Move AsciiDoc details into new README.md in the doc
directory.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Fix typo in link to AsciiDoc cheat sheet
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* COPYING.BSD: Created.
* COPYING.CC: Created.
* README.md: Add git process, licensing and engineering process.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Correct details for running the compliance tests and
directory for OVPsim.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
Clean restructuring to just the work of interest.
* thought-experiments: Directory removed.
* .gitignore: Merged with TestStructure/.gitignore
* Makefile: Renamed from TestStructure/Makefile.
* TestStructure/Makefile: Renamed as Makefile.
* README.md: Merged with TestStructure/README.md.
* TestStructure/.gitignore: Deleted and contents moved into
.gitignore.
* TestStructure/README.md: Deleted and contents moved into
README.md.
* TestStructure/doc: Directory deleted.
* TestStructure/riscv-target: Directory moved to riscv-target.
* riscv-target: Directory moved from TestStructure/riscv-target
* TestStructure/riscv-test-env: Directory moved to riscv-test-env.
* riscv-test-env: Directory moved from
TestStructure/riscv-test-env.
* TestStructure/riscv-test-suite: Directory moved to
riscv-test-suite.
* riscv-test-suite: Directory moved from
TestStructure/riscv-test-suite.
* thought-experiments: Directory deleted.
2018-05-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
Initial commit to populate the repository.
* ChangeLog: Created.
* README.md: Created.

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@ -1,66 +0,0 @@
# Contributing to RISC-V Architecture Tests
Your inputs are welcome and greatly appreciated! We want to make contributing to this project as easy and transparent as possible, whether it's:
- Reporting a bug
- Discussing the current state of the code
- Submitting a fix
- Proposing new features
- Becoming a maintainer
## We develop with Github
We use github to host code, to track issues and feature requests, as well as accept pull requests.
## We use a simple git flow where all code changes happen through Pull Requests
Pull requests are the best way to propose changes to the codebase. We actively welcome your pull requests:
1. Fork the repo and create your branch from `master`.
2. If you have added new tests, please ensure they adhere to the latest TestFormatSpec and that you have run them on the RVI approved reference
models (if support in those models is available).
3. If you have updated any test-macros make sure to update the documentation as well.
4. If you have updated the docs, ensure that they render correctly in the respective format.
5. Make sure to create an entry in the CHANGELOG.md. Please refer to the section on versioning below
to choose an appropriate version number.
6. Ensure the existing tests are not broken and still pass on the the RVI approved reference models.
7. Please include a comment with the SPDX license identifier in all source files, for example:
```
// SPDX-License-Identifier: BSD-3-Clause
```
8. Issue that pull request!
## Versioning
When issuing pull requests, an entry in the CHANGELOG.md is mandatory. The arch-test-repo adheres to
the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must
be followed while assigning a new version number :
- Patch-updates: all doc updates (like typos, more clarification,etc) and updates to unratified extensions.
- Minor-updates: Updates to ratified extensions OR migration of extensions to ratified OR changes in docs regarding policies or spec.
- Major-updates: Changes to the framework flow (backward compatible or incompatible).
Note: You can have either a patch or minor or major update.
Note: In case of a conflict, the maintainers will decide the final version to be assigned.
## Any contributions you make will be under the permissive open-source License
In short, when you submit code changes, your submissions are understood to be under a permissive open source license like BSD-3, Apache-2.0 and CC, etc that covers the project. Feel free to contact the maintainers if that's a concern.
## Report bugs using Github's [issues](https://github.com/riscv/riscv-arch-test/issues)
We use GitHub issues to track public bugs. Report a bug by [opening a new issue](https://github.com/riscv/riscv-arch-test/issues/new); it's that easy!
## Write bug reports with detail, background, and sample code
**Great Bug Reports** tend to have:
- A quick summary and/or background
- Steps to reproduce
- Be specific!
- Give sample code if you can.
- What you expected would happen
- What actually happens
- Notes (possibly including why you think this might be happening, or stuff you tried that didn't work)
## License
By contributing, you agree that your contributions will be licensed under its permissive open source
licenses.

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@ -87,7 +87,7 @@ simulate:
run -C $(SUITEDIR)
verify: simulate
riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values
riscv-test-env/verify.sh
postverify:
ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),)

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# RISC-V Architecture Test SIG
This is a repository for the work of the RISC-V Foundation Architecture Test SIG. The repository owners are:
- Neel Gala (InCore Semiconductors)
- Marc Karasek (Inspire Semiconductors)
Details of the RISC-V Foundation, the work of its task groups, and how to become a member can be found at [riscv.org](https://riscv.org/).
For more details and documentation on the current testing framework see: [doc/README.adoc](doc/README.adoc)
For more details on the test format spec see: [spec/TestFormatSpec.adoc](spec/TestFormatSpec.adoc)
For contributions and reporting issues please refer to [CONTRIBUTION.md](CONTRIBUTION.md)
## Test Disclaimers
The following are the exhaustive list of disclaimers that can be used as waivers by target owners
when reporting the status of pass/fail on the execution of the architectural suite on their respective targets.
1. The references uploaded for the following misaligned load/store tests will match targets which do
not support misaligned load/stores in hardware. Targets with hardware misaligned support for
load/stores will fail these tests.
1. rv32i_m/privilege/src/misalign-[lb[u],lh[u],lw,sh,sb,sw]-01.S
2. rv64i_m/privilege/src/misalign-[lb[u],lh[u],lw[u],ld,sb,sh,sw,sd]-01.S
2. The references uploaded for the following misaligned instruction tests will match targets which
have compressed extension support enabled by default. Targets without the compressed extension
support will fail the following tests:
1. rv[32/64]i_m/privilege/src/misalign-b[ge[u],lt[u],eq,ne]-01.S
2. rv[32/64]i_m/privilege/src/misalign[1,2]-jalr-01.S
3. The machine mode trap handler used in the privilege tests assumes one of the following conditions.
Targets not satisfying any of the following conditions are bound to fail the entire
rv32i_m/privilege and rv64i_m/privilege tests:
1. The target must have implemented mtvec which is completely writable by the test in machine mode.
2. The target has initialized mtvec, before entering the test (via RVMODEL_BOOT), to point to a memory location which has both read and write permissions.
## Contribution process
Please refer to to [CONTRIBUTION.md](CONTRIBUTION.md) for guidelines on contributions.
## Licensing
In general:
- code is licensed under one of the following:
- the BSD 3-clause license (SPDX license identifier `BSD-3-Clause`);
- the Apache License (SPDX license identifier `Apache-2.0`); while
- documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier `CC-BY-4.0`).
The files [`COPYING.BSD`](./COPYING.BSD), [`COPYING.APACHE`](./COPYING.APACHE) and [`COPYING.CC`](./COPYING.CC) in the top level directory contain the complete text of these licenses.
## Engineering practice
- Documentation uses the structured text format _AsciiDoc_. See [`doc/README.adoc`](doc/README.adoc) for more details.
- Some directories use `ChangeLog` files to track changes in the code and documentation. Please honor these, keeping them up to date and including the ChangeLog entry in the _git_ commit message.
- Please include a comment with the SPDX license identifier in all source files, for example:
```
// SPDX-License-Identifier: BSD-3-Clause
```
## Quick Links:
- RISCOF \[[DOCS](https://riscof.readthedocs.io/en/latest/)\] \[[REPO](https://github.com/riscv-software-src/riscof)\]: This is the next version of the architectural test framework currently under development
- RISCV-ISAC \[[DOCS](https://riscv-isac.readthedocs.io/en/latest/index.html)\] \[[REPO](https://github.com/riscv-software-src/riscv-isac)\] : This is an ISA level coverage extraction tool for RISC-V which used to generate the coverage statistics of the architectural tests.
- RISCV-CTG: \[[DOCS](https://riscv-ctg.readthedocs.io/en/latest/index.html)\]\[[REPO](https://github.com/riscv-software-src/riscv-ctg)\]: This is a RISC-V Architectural Test generator used to generate some of the tests already checked into this repository.
- [Videos](https://youtu.be/VIW1or1Oubo): This Global Forum 2020 video provides an introduction to the above mentioned tools
- [riscvOVPsim](https://github.com/riscv-ovpsim/imperas-riscv-tests): Imperas freeware RISC-V reference simulator for compliance testing
- [riscvOVPsimPlus](https://www.ovpworld.org/riscvOVPsimPlus/): Imperas enhanced freeware RISC-V reference simulator for test development and verification

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@ -1,6 +0,0 @@
# Ignore editor backups
*~
# Generated files
custom.dict
README.pdf
README.html

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@ -1,147 +0,0 @@
2019-02-21 Deborah Soung <debs@sifive.com>
* README.adoc: Documentation for rocket chip as target.
2019-02-05 Deborah Soung <debs@sifive.com>
* README.adoc: Update documentation for rocket chip as target (fixed rv32si/ma_fetch.S).
* README.adoc: Update documentation for rocket chip as target (fixed breakpoint.S).
2019-01-29 Deborah Soung <debs@sifive.com>
* README.adoc: Documentation for rocket chip as target.
2018-11-21 Olof Kindgren <olof.kindgren@gmail.com>
* README.adoc (Repository structure) Added documentation for the $TARGETDIR environmental variable
2018-11-21 Neel Gala <neelgala@incoresemi.com>
* README.adoc: Added new signature format spec.
2018-06-18 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.adoc (Future work): Reflect changes made to support
Codasip simulator.
(Repository structure): Diagrammatic representation of the file
structure deleted.
2018-06-12 Jeremy Bennett <jeremy.bennett@embecosm.com>
* .gitignore: Add custom.dict.
2018-06-12 Jeremy Bennett <jeremy.bennett@embecosm.com>
Document issue 1.8 Draft.
* README.adoc (Introduction): Add Future work section and bump
version.
* custom.wordlist: Add words needed for Future work section.
2018-06-12 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.adoc: Remove special apostrophe from "licensor's".
* custom.wordlist: Updated with more words to be ignored.
2018-06-12 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README-old.md: Deleted.
* README.adoc: Include details of how to contribute and installing
the tools from the old README and reference the licence as an
appendix.
2018-06-11 Jeremy Bennett <jeremy.bennett@embecosm.com>
This makes the document appear directly as the README of the doc
directory, so there is now no longer a need to publish to GitHub
pages.
* .gitignore: Change name of files ignored.
* Makefile: Remove publish target.
* README.adoc: Symbolic link removed and replaced by design.adoc,
to which the CC license text has been added.
* design.adoc: Renamed as README.adoc.
* publish.sh: Deleted.
2018-06-11 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Previous version moved to README-old.md for the time
being.
* README.adoc: Created as symbolic link to design.adoc.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Note about make publish.
* design.adoc (Overall structure): Make list or instruction sets
and extensions compact representation.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* publish.sh: Only publish from clean and committed master branch
to avoid difficult use of git stash.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* publish.sh: Don't rely on doc directory being available on
gh-pages branch.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* publish.sh: Make executable and correctly set top level
repository directory.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
Add a mechanism to make the latest documentation available via
GitHub pages. This means that design.html is no longer part of
the master branch, but is published by copying to index.html on
the gh-pages branch.
* .gitignore: Ignore design.html.
* Makefile: Add publish target and delete design.html when cleaning.
* README.md: Link to GitHub pages for latest documentation.
* design.adoc: Deal with AsciiDoc apparent bug with consecutive
comment blogs.
* design.html: Deleted.
* publish.sh: Created.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Fix link to generated documentation.
* design.html: Regenerated.
2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* Makefile: Add sanity check for version number and spell target.
* design.adoc: Fix trivial typo.
* design.html: Regenerated.
2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* .gitignore: Don't ignore .html or .xml
* README.md: Note location of old documentation, give link to HTML
and explain how to contribute.
* custom.wordlist: Created.
* design.adoc: Cleaned up from top to bottom and spell checked.
* design.html: Generated.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* Makefile: Clean up and add license header.
* README.md: Created.
* design.adoc: Add licensing and SPDX license identifier.
* legacy.adoc: Deleted.
2018-06-04 Jeremy Bennett <jeremy.bennett@embecosm.com>
This is the first version of the document taken from Simon
Davidmann's MS Word document. The main document is design.adoc,
legacy material, currently just appendices C and D has been moved
to legacy.adoc.
design.adoc is correct AsciiDoc. legacy.adoc is just a raw dump,
which needs cleaning up.
The next step will be restructuring design.adoc as agreed.
* .gitignore: Created.
* ChangeLog: Created.
* Makefile: Created.
* design.adoc: Created.
* legacy.adoc: Created.

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= Migration guide
:toc:
:icons: font
:numbered:
:source-highlighter: rouge
This document serves as a guide to users of the architectural suite to migrate their targets from an
older version to a newer version with minimal changes. This guide thus provides a patch scheme to get
the previous versions of the targets up and running with the new versions of the framework.
However, users are strongly encouraged to completely migrate to the newer versions, as and when
available, and avoid using these patches.
== Migration from v0.1 to v0.2
This section will describe the changes required to transition your targets ported on v0.1 to v0.2
framework. For examples please see: `riscv-target/riscvOVPsim_0p1` and `riscv-target/spike_0p1`.
=== Change header filename
In version v0.1 the target specific assembly macros were split across two files: `compliance_test.h`
and `compliance_io.h`. In version v0.2 these macros are to merged into a single file named
`model_test.h`. The following commands can the achieve the above:
----
mv compliance_test.h model_test.h
cat compliance_io.h >> model_test.h
rm compliance_io.h
----
=== Change device directory structure
In version v0.1 a target would have one or multiple of the directories defined to indicate supported
extensions: `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei`. In version v0.2 the
directories of the extensions have changed in order to provide more consistency and less ambiguity.
For version v0.2, the `device` directory first needs to have either a `rv32i_m` directory to indicate
that the target is a 32-bit machine. The extension directories, as supported by the target, are
now to be created in each of these directories using the following mapping scheme:
. device/rv32i -> device/rv32i_m/I
. device/rv32im -> device/rv32i_m/M
. device/rv32imc -> device/rv32i_m/C
. device/rv32Zicsr -> device/rv32i_m/privilege
. device/rv32Zifencei -> device/rv32i_m/Zifencei
The contents of the extension directories need not change, unless there are dependencies on the path
of the directory itself. The following commands will achieve the above:
----
cd device
mkdir rv32i_m
mv rv32i rv32i_m/I
mv rv32im rv32i_m/M
mv rv32imc rv32i_m/C
mv rv32Zicsr rv32i_m/privilege
mv rv32Zifencei rv32i_m/Zifencei
----
=== Changes in target macro names.
Since some of the macros from the old framework have been re-purposed in the new v0.2 framework,
there will be name conflicts rendering the old ones useless. In order to retain the old macros, they
have been renamed with a post-fix `_OLD`. The macros that have been renamed are given below:
. `RVTEST_CODE_BEGIN` -> `RVTEST_CODE_BEGIN_OLD`
. `RVTEST_CODE_END` -> `RVTEST_CODE_END_OLD`
. `RVTEST_DATA_BEGIN` -> `RVTEST_DATA_BEGIN_OLD`
. `RVTEST_DATA_END` -> `RVTEST_DATA_END_OLD`
The user is thus required to make the above changes in the new `model_test.h` that was created
as part of this migration. The following commands will help achieve the above:
----
sed -i 's/RVTEST_CODE_BEGIN/RVTEST_CODE_BEGIN_OLD/g' model_test.h
sed -i 's/RVTEST_CODE_END/RVTEST_CODE_END_OLD/g' model_test.h
sed -i 's/RVTEST_DATA_BEGIN/RVTEST_DATA_BEGIN_OLD/g' model_test.h
sed -i 's/RVTEST_DATA_END/RVTEST_DATA_END_OLD/g' model_test.h
----
note:: the RVTEST_DATA_END in v0.1 enforced a 16-byte alignment before the signature end. This
constraint has been removed.
=== Changes in device Makefile.include files
No changes required.

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# Makefile for RISC-V Architectural Test SIG documentation
# This file is part of the RISC-V Foundation Architectural Test SIG
# tool set and documentation.
# Copyright (C) 2017 CodaSip Limited <www.codasip.com>
# Copyright (C) 2018 Embecosm Limited <www.embecosm.com>.
# Copyright (C) 2018 Imperas Limited <www.imperas.com>
# All rights reserved.
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of mosquitto nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
# SPDX-License-Identifier: BSD-3-Clause
ROOT = README
SRC = $(ROOT).adoc
SRC_STRIPPED = $(ROOT)-stripped.adoc
.PHONY: all
all: pdf html
.PHONY: pdf
pdf: $(ROOT).pdf
$(ROOT).pdf: sanity-check $(SRC)
asciidoctor-pdf -d article $(SRC)
.PHONY: html
html: $(ROOT).html
$(ROOT).html: sanity-check $(SRC)
asciidoctor -d article -b html $(SRC)
# It is all too easy for the document history and title page to have diverging
# version numbers. This target checks first.
.PHONY: sanity-check
sanity-check:
@s=$$(sed -n < $(SRC) -e '3s/Issue //p') ; \
t=$$(sed -n < $(SRC) -e "/== Document history/,/^$$/p" | \
grep -c "$${s}") ; \
if [ $${t} -ne 1 ] ; \
then \
echo "Version number of title and document history do not match" ; \
exit 1 ; \
fi
custom.dict: custom.wordlist
aspell --lang=en create master ./$@ < $<
.PHONY: spell
spell: custom.dict $(SRC)
sed < $(SRC) > $(SRC_STRIPPED) -e 's/`[^`]\+`//gp' -e '/^----$$/,/^----$$/d'
aspell --master=en_US --mode=none --add-extra-dicts=./custom.dict \
-c $(SRC_STRIPPED)
$(RM) $(SRC_STRIPPED)
clean:
rm -f $(ROOT)-stripped.adoc $(ROOT).pdf $(ROOT).html custom.dict

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= RISC-V Architectural Testing Framework =
RISC-V Foundation Architecture Test SIG
Issue 1.16 Draft
:toc:
:icons: font
:numbered:
:source-highlighter: rouge
////
SPDX-License-Identifier: CC-BY-4.0
Document conventions:
- one line per paragraph (don't fill lines - this makes changes clearer)
- Wikipedia heading conventions (First word only capitalized)
- US spelling throughout.
- Run "make spell" before committing changes.
- Build the HTML and commit it with any changed source.
- Do not commit the PDF!
////
== Introduction
=== About
This document describes the RISC-V Architectural Testing framework which is used to test if a RISC-V device's has understood and implemented the specifications correctly
* It explains the framework around the tests, the running of individual tests, and the suites of tests.
* It explains how to set up targets to run the tests.
This document is made freely available under a <<app_cc_by_4.0>>.
=== Intent of the architectural test suite
The RISC-V Architectural Tests are an evolving set of tests that are created to help ensure that software written for a given RISC-V Profile/Specification will run on all implementations that comply with that profile.
These tests also help ensure that the implementer has both understood and implemented the specification correctly.
The RISC-V Architectural Test suite is a minimal filter. Passing the tests and having the results approved by RISC-V International is a prerequisite to licensing the RISC-V trademarks in connection with the design. Passing the RISC-V Architectural Tests does not mean that the design complies with the RISC-V Architecture. These are only a basic set of tests checking important aspects of the specification without focusing on details.
The RISC-V Architectural Tests are not a substitute for rigorous design verification.
The result that the architecture tests provide to the user is an assurance that the specification has been interpreted correctly and the implementation under test (DUT) can be declared as RISC-V Architecture Test compliant.
=== Intended audience
This document is intended for design and verification engineers who wish to check if their RISC-V implementation (simulation models, HDL models, etc.) is compliant to the RISC-V specification.
For those who wish to develop new architectural tests and/or to write or adapt their own test framework are suggested to read the link:../spec/TestFormatSpec.adoc[`Test Format Spec`].
=== Contribute
You are encouraged to contribute to this repository (including changes to this document) by submitting pull requests and by commenting on pull requests submitted by other people as described in the link:../README.md[`README.md`] file in the top level directory.
While submitting a pull request note that some directories use `ChangeLog` files to track changes in the code and documentation. Please honor these, keeping them up to date and including the ChangeLog entry in the _git_ commit message.
Make sure to also include a comment with the SPDX license identifier in all source files, for example:
```
// SPDX-License-Identifier: BSD-3-Clause
```
NOTE: Don't forget to add your own name to the list of contributors in the document.
== Licensing
In general:
* code is licensed under the BSD 3-clause license (SPDX license identifier `BSD-3-Clause`);
* documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier `CC-BY-4.0`).
The files link:../COPYING.BSD[`COPYING.BSD`] and link:../COPYING.CC[`COPYING.CC`] in the top level directory contain the complete text of these licenses.
NOTE: The riscv-ovpsim simulator is licensed under an Imperas license. There is no dependency on this and it is included as a convenience to users.
==== AsciiDoc
This is a structured text format used by this document. Simple usage should be fairly self evident.
* Comprehensive information on the format is on the http://www.methods.co.nz/asciidoc/[AsciiDoc website].
* Comprehensive information on the tooling on the https://asciidoctor.org/[AsciiDoctor website].
* You may find this https://asciidoctor.org/docs/asciidoc-syntax-quick-reference/[cheat sheet] helpful.
==== Installing tools
To generate the documentation as HTML you need _asciidoctor_ and to generate as
PDF you need _asciidoctor-pdf_.
* These are the https://asciidoctor.org/docs/install-toolchain/[installation instructions for asciidoctor].
* These are the https://asciidoctor.org/docs/asciidoctor-pdf/#install-the-published-gem[installation instructions for asciidoctor-pdf].
To spell check you need _aspell_ installed.
==== Building the documentation
To build HTML:
[source,make]
----
make html
----
To build PDF:
[source,make]
----
make pdf
----
To build both:
[source,make]
----
make
----
To check the spelling (excludes any listing or code phrases):
[source,make]
----
make spell
----
Any custom words for spell checking should be added to link:./custom.wordlist[`custom.wordlist`].
=== Contributors
This document has been created by the following people (in alphabetical order of surname).
* Jeremy Bennett
* Mary Bennett
* Simon Davidmann
* Neel Gala
* Radek Hajek
* Lee Moore
* Milan Nostersky
* Marcela Zachariasova
=== Document history
[cols="<1,<2,<3,<4",options="header,pagewidth",]
|================================================================================
| _Revision_ | _Date_ | _Author_ | _Modification_
| 1.16 Draft | 23 September 2020 | Neel Gala| Changed Compliance to Architecture/Architectural. Refined the steps to port a new target. Removed simulator and target specific docs. Added vocabulary from the Test Format Specification
| 1.15 Draft | 14 March 2019 |
Prashanth Mundkur |
Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets.
| 1.14 Draft | 21 February 2019 |
Deborah Soung |
Documented how to use SiFive's RISC-V ISA Formal Specification model as a target.
| 1.13 Draft | 29 January 2019 |
Deborah Soung |
Added documentation on how to use Rocket Chip generated cores as targets.
| 1.12 Draft | 22 November 2018 |
Simon Davidmann |
Updated notes on Test Suites.
| 1.11 Draft | 21 November 2018 |
Neel Gala |
Added new signature format specs .
| 1.10 Draft | 20 June 2018 |
Simon Davidmann, Lee Moore |
Cleaned up description of updated framework and inclusion of riscvOVPsim.
| 1.9 Draft | 12 June 2018 |
Jeremy Bennett |
Update Future work section to take account of Codasip changes. Remove diagrammatic directory structure.
| 1.8 Draft | 12 June 2018 |
Jeremy Bennett |
Add Future work section.
| 1.7 Draft | 12 June 2018 |
Jeremy Bennett |
Add CC license as an appendix.
| 1.6 Draft | 10 June 2018 |
Jeremy Bennett |
Tidy up areas that are flawed in HTML version.
| 1.5 Draft | 8 June 2018 |
Jeremy Bennett |
General tidy up.
| 1.4 Draft | 8 June 2018 |
Jeremy Bennett |
Added license preamble.
| 1.3 Draft | 5 June 2018 |
Simon Davidmann |
Updated to reflect directory structure and trace macros.
| 1.2 Draft | 3 June 2018 |
Jeremy Bennett |
Converted to AsciiDoc, cleaned up and restructured.
| 1.1 Draft | 1 June 2018 |
Simon Davidmann
Lee Moore |
Revised format and expand to describe framework, usage of many tests groups,
and different Targets
|1.0 | 24 December 2017 |
Radek Hajek
Milan Nostersky
Marcela Zachariasova |
First version of the document.
|================================================================================
== Repository structure
The top level directory contains :
- a `README.md` file providing high-level details about the RISC-V Architecture Testing Framework.
- top level `Makefile` for running the tests on a RISC-V implementation.
- `ChangeLog` for logging changes with respect to code.
- complete license files for the Creative Commons and BSD licenses used by the task group.
There are then five top level directories.
`doc`:: All the documentation for the project, written using _AsciiDoc_.
`coverage`:: This directory contains a sub-directory structure similar to the `riscv-test-suite` directory. The coverage reports of each test-suite are available in the corresponding directories. The reports are available in the html and yaml formats. The directory also contains multiple coverpoint YAMLs which capture all the coverpoints of interest which are covered by all the tests in the `riscv-test-suite` directory.
`riscv-target`:: Contains a further subdirectory for each target, within which are placed the `model_test.h` header for that target and a `device` directory for all the devices of that target. If the `$TARGETDIR` environment variable is set to another directory, the scripts will search this directory for targets instead.
`riscv-test-env`:: This contains the `verify.sh` script which checks if the signatures generated the riscv-target device match the statically hosted reference signatures at the end of simulation. The directory also contains symbolic-links to the `arch_test.h` and `encoding.h` files present in the `riscv-test-suite/env` directory.
`riscv-test-suite`:: This contains a further `env` subdirectory which contains the `arch_test.h` and the `encoding.h` file which includes common assembly macros and routines which is used across the tests in the suite. Further directories are present which contain the actual architectural tests. The names and structure of these directories is based on the link:../test-pool structure guideline highlighted above.
`riscv-ovpsim`:: This contains a README pointing to the Imperas OVP riscvOVPsim simulator for use in architectural testing.
== Vocabulary
=== The architectural test
At the heart of the testing infrastructure is the detailed <<The architectural tests, _architectural test_>> available as `.S` assembly files. The specification and format of the tests is defined in the link:./TestFormatSpec.adoc[`Test Format Specification`].
=== The architectural test pool
The <<The architectural test, _architectural tests_>> are grouped into different functional test suites targeting the different subsets of the RISC-V specification. For more details on the test-pool structure, hierarchy and conventions please refer to the link:./TestFormatSpec.adoc[`Test Format Specification`].
For information on the currently supported different test suites, look here: link:../riscv-test-suite/README.md[../riscv-test-suite/README.md]
=== The test signature
Each test in the <<The architectural test pool, _architectural test pool_>> generates a <<The test signature, _test signature_>>, which represents the data written into specific memory locations during the execution of the test. The signature typically will record values (or sanitised values) of the operations carried out in the test. More details on the format and nature of the signatures is available in the link:./TestFormatSpec.adoc[`Test Format Specification`]
=== The reference signature
In order to claim that a device/implementation has passed the RISC-V Architecture Tests, the <<The test signature, _test signatures_>> obtained from the execution of the tests on the implementation need to be compared against a set of _golden_ <<The reference signatures, _reference signature_>>. These reference signatures are currently generated by the link:https://github.com/rems-project/sail-riscv[`RISC-V SAIL`] formal model and statically hosted in the repository for each test.
=== The test target
The <<The test target,_test target_>> can be either a RISC-V Instruction Set Simulator (ISS), a RISC-V emulator, a RISC-V RTL model running on an HDL simulator, a RISC-V FPGA implementation or a physical chip. Each of the target types offers specific features and represents specific interface challenges. It is a role of the <<The target shell, _target shell_>> to handle different targets while using the same <<The architectural test pool,_architectural test pool_>> as a test source.
=== The target shell
The <<The target shell, _target shell_>> is the software and hardware environment around the <<The test target,_test target_>> that enables it to communicate with the framework, including assembling and linking tests, loading tests into memory, executing tests, and extracting the signature. The input to the <<The target shell, _target shell_>> is a .S <<The architectural test,_architectural test_>> file, and the output is a <<The test signature,_test signature_>>.
== Porting a new target
In this section, a short tutorial on how to add a user target to the RISC-V Architectural Test Framework is provided.
The following steps demonstrate an example in which a target was replaced by the RISCV-ISA-SIM
(a.k.a Spike). In a similar way, any RISC-V ISA simulator or any RTL simulation model of the
RISC-V processor can be ported as a potential target for testing.
=== Setup environment variables
NOTE: `ROOTDIR` will always point to the riscv-arch-test repo.
1. Clone the repository:
---
git clone https://github.com/riscv/riscv-arch-test.git
cd riscv-arch-test
---
2. Open the `Makefile.include` available in the root folder of the repository and edit the following
variables based on your target:
a. `TARGETDIR` : set `TARGETDIR` to point to the directory which contains a sub-folder in the same name
as the target. For example, the arch-test repo includes the targets: sail-riscv-c and spike
under the `riscv-target` folder, in which case we set the `TARGETDIR` to riscv-target as shown
below. One can set this completely arbitrary paths as suitable by the user.
---
export TARGETDIR ?= $(ROOTDIR)/riscv-target
---
b. `XLEN`: set XLEN to max supported XLEN. Allowed values are 32 and 64.
---
export XLEN ?= 64
---
c. `RISCV_TARGET`: set this variable to the name of the target. A folder of the same name must exist in
the `TARGETDIR` directory
---
export RISCV_TARGET ?= spike
---
d. `RISCV_DEVICE`: set the `RISCV_DEVICE` environment to the extension you want to compile, simulate and verify. Leave
this blank if you want to iterate through all the supported extensions of the target. Allowed values
are the individual names of the extensions supported by your target like: I, M, C or Zifencei, etc. Multiple extensions are not be provided.
---
export RISCV_DEVICE ?=
---
e. `RISCV_TARGET_FLAGS`: set this to a string which needs to be passed to your target's Makefile.include files
---
export RISCV_TARGET_FLAGS ?=
---
f. `RISCV_ASSERT`: set this if you want to enable assertions on the test-suites. **Currently no tests use assertions.**
---
export RISCV_ASSERT ?= 0
---
g. `JOBS`: set the number of parallel jobs (along with any other arguments) you would like to
execute. Note that the target needs to be coded in such a way to support parallel execution. Some
targets use common intermediate files, rather than unique files, which makes them unsuitable for
parallel execution, these targets will need to be re-coded.
---
JOBS= -j1
---
3. Now inside your `TARGETDIR/RISCV_TARGET` directory you will need to create the following files:
a. `model_test.h`: A header file containing the definition of the various target specific
assembly macros that are required to compile and simulate the tests. The list and definition of the
required target specific macros is available in the link:../spec/TestFormatSpec.adoc[Test Format
Specification]
b. `link.ld`: A linker script to compile the tests for your target.
c. Any other files required by the target (configuration scripts, logs, etc.) can also be placed in
this directory.
4. Inside the `TARGETDIR/RISCV_TARGET` directory create a new folder named: `device`. If your device
is a 32-bit target then create a directory `device/rv32i_m`. If your device is a 64-bit target then
create a directory `device/rv64i_m`. If your target is configurable on the `XLEN` parameter then
both the folders need to be created.
5. Within the `rv32i_m`/`rv64i_m` directories sub-folders in the name of the extensions supported
by the target need to be created. For eg. A target supporting the ISA RV32IMC_Zifence will have the
following directory structure:
---
- rv32i_m/I
- rv32i_m/M
- rv32i_m/C
- rv32i_m/privilege
- rv32i_m/Zifencei
---
6. Each of the above extension directories will now need to include a file: `Makefile.include` which
defines the following Makefile variables:
a. `RUN_TARGET`:: This variable needs to include commands and steps to execute an ELF on target device. Note here that this variable should include all the necessary steps and arguments to run that specific test-suite. For example, in case of spike for the `rv32i_m/C` test-suite the corresponding `Makefile.include` has the `--isa=rv32ic` argument as opposed to just `--isa=rv32i` for the base `rv32i_m/I` test-suite. This variable should also include other steps to extract and sanitize the signature file as well for each test. The only argument available to this variable is the compiled `elf` file.
b. `COMPILE_TARGET`:: This variable should include the commands and steps required to compile an assembly test for the target for each extension mentioned above. Note, currently only the GCC compiler is supported. This compiler takes `march` and `mabi` arguments from the corresponding architectural suite framework. `COMPILE_TARGET` will more or less be the same across test-suites. The only argument available to `COMPILE_TARGET` is the assembly file of one architectural test.
The following figure depicts the final directory structure of a target device that should get created at the end of the above steps:
[#img-testStruct]
.File Structure of the Target directory
image::./file-struct.jpg[TargetStruct]
=== Generating Signature
As previously mentioned the execution of each test on the target must generate a signature file. The name of the signature file should be `<test-file-name.signature_output>`. The signature file should follow the guidelines mentioned in the link:../spec/TestFormatSpec.adoc[`Test Format Specification`].
In case of spike, we have ensured that the signature region is bounded by the labels: `begin_signature` and `end_signature`. This is enforced in the `RVMODEL_DATA_BEGIN` and `RVMODEL_DATA_END` macros defined in the `riscv-target/spike/model_test.h` file. Additionally, if you look closely at the `RUN_TARGET` variable defined in the `Makefile.include` files of the spike target, it includes a few bash commands to sanitize the signature produced from spike. This is done to conform the final signature file to the specification defined in the link:../spec/TestFormatSpec.adoc[`Test Format Specification`].
=== Compile, simulate and verify the tests
Once you have ported your target to the riscv-arch-test framework by following the above steps, you
are now ready to compile, simulate and verify the tests on your target
If you would like to compile, simulate and verify all the extension tests applicable to your target
simply run `make` from the `ROOTDIR`.
NOTE: For the above to work the `RISCV_DEVICE` in `ROOTDIR/Makefile.include` must be left empty.
If you would like to only compile the tests for a particular extension you can use the following
command.
make RISCV_DEVICE=M compile
make RISCV_DEVICE=C compile
The arguments to the `RISCV_DEVICE` variable must be the extensions supported by the target.
NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary
for all targets.
To simulate the compiled tests on your target:
make RISCV_DEVICE=M simulate
make RISCV_DEVICE=Zifencei simulate
NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary
for all targets.
To verify if the generated signatures match the corresponding reference signatures.
make RISCV_DEVICE=M verify
NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary
for all targets.
All the above steps create and modify files in the `work` directory created in `ROOTDIR` folder. To
clean the `workdir` simple run :
make clean
By default the working directory is set to `ROOTDIR/work`. This can be overwritten by assigning a
new working directory path via the command line. Note, the path must be absolute and not relative :
make WORK=/home/me/my_path/mywork clean compile simulate

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riscvOVPsim
===
A Complete, Fully Functional, Configurable RISC-V Simulator
===
riscvOVPsim has moved to its own GitHub repository.
It can now be found here: [github.com/riscv-ovpsim](https://github.com/riscv-ovpsim/imperas-riscv-tests)
For the enhanced version, please download from [ovpworld.org/riscv-ovpsim-plus](https://www.ovpworld.org/riscvOVPsimPlus).
The simulators implement the full and complete functionality of the RISC-V Foundation's public User and Privilege specifications.
The simulator is command line configurable to enable/disable all current optional and processor specific options.
The simulator is developed, licensed and maintained by [Imperas Software](http://www.imperas.com/riscv) and it is fully compliant to the OVP open standard APIs.
As a member of the RISC-V Foundation community of software and hardware innovators collaboratively driving RISC-V adoption, Imperas has developed the riscvOVPsim simulator to assist RISC-V adopters to become compliant to the RISC-V specifications. The latest RISC-V compliance test suite and framework can be downloaded from https://www.github.com/riscv/riscv-compliance.
riscvOVPsim includes an industrial quality model and simulator of RISC-V processors for use for compliance and test development. It has been developed for personal, academic, or commercial use, and the model is provided as open source under the Apache 2.0 license. The simulator is provided under the Open Virtual Platforms (OVP) Fixed Platform Kits license that enables download and usage. riscvOVPsim and Imperas RISC-V support is actively maintained and enhanced. To ensure you make use of the current version of riscvOVPsim versions do expire. Please download the latest version.
![](riscvOVPsim.jpg)
Extending riscvOVPsim and building your own models and platforms
---
riscvOVPsim is a fixed function simulation of one configurable processor model in a fixed platform.
Full extendable platform simulations of reference designs booting FreeRTOS, Linux, SMP Linux etc.
are available as open source and are available from [www.IMPERAS.com](http://www.imperas.com),
[www.OVPworld.org](http://www.OVPworld.org).
About Open Virtual Platforms (OVP) and Imperas Software
---
**Open Virtual Platforms** was created in 2008 to provide an open standard set of APIs and methodology to develop virtual platforms and simulation technology.
[www.OVPworld.org](http://www.OVPworld.org/riscv).
**Imperas Software Ltd.** is the leading independent commercial developer of virtual platforms and high-performance software simulation solutions for embedded processor and systems. Leading semiconductor and embedded software companies use Imperas simulators for their processor based simulation solutions.
[www.imperas.com](http://www.imperas.com/riscv).
![OVP Image ](http://www.imperas.com/sites/default/files/partner-logos/ovp_0.jpg)
![Imperas Imperas](https://www.imperas.com/sites/default/files/imperas-web-logo_2.png)
---
This is the riscvOVPsim/README.md

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