Ross Thompson 6d12010d02 Fixed subtle and infrequenct bug. ... Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.		2022-02-11 10:46:06 -06:00
..
config	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 14:22:19 -06:00
fpu-testfloat/FMA/tbgen	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
misc
regression	Fixed subtle and infrequenct bug.	2022-02-11 10:46:06 -06:00
src	Fixed subtle and infrequenct bug.	2022-02-11 10:46:06 -06:00
srt
testbench	Restored E tests to makefrag	2022-02-08 16:41:11 +00:00