Ross Thompson 400b5f7632 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.		2022-04-04 09:57:26 -05:00
..
config	added RV64IA config to have a config without compressed instructions	2022-04-02 18:24:08 +00:00
fpu-testfloat/FMA/tbgen	FMA parameterized and FMA testbench reworked	2022-03-19 19:39:03 +00:00
misc
regression	Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.	2022-04-04 09:57:26 -05:00
src	Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.	2022-04-04 09:57:26 -05:00
srt	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
testbench	Updated the fpga test bench.	2022-04-01 17:14:47 -05:00