bbracker 3465d8cd32 improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS		2022-04-13 03:37:53 -07:00
..
config	Added missing ZFH macro to new configs	2022-04-06 07:13:51 +00:00
misc
regression	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-10 13:41:27 -05:00
src	Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.	2022-04-07 16:56:28 -05:00
srt	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
testbench	improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS	2022-04-13 03:37:53 -07:00