forked from Github_Repos/cvw
Moved lsu virtual memory logic into separate module.
This commit is contained in:
Ross Thompson
parent
9cd502d0af
commit
31da37dd0f
@ -82,7 +82,6 @@ module lsu (
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);
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logic [`PA_BITS-1:0] LSUPAdrM; // from mmu to dcache
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logic [`XLEN+1:0] IEUAdrExtM;
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logic DTLBMissM;
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logic DTLBWriteM;
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logic [1:0] LSURWM;
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@ -107,54 +106,27 @@ module lsu (
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////////////////////////////////////////////////////////////////////////////////////////////////
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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logic [`XLEN+1:0] IEUAdrExtM;
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
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// *** encapsulate as lsuvirtmem
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logic AnyCPUReqM;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic HPTWRead;
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logic [2:0] HPTWSize;
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logic SelReplayCPURequest;
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lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM, .SATP_REGW, .PCF,
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.ReadDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM,
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.IEUAdrExtM, .PTE, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE,
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.LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW,
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.IgnoreRequest);
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assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
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interlockfsm interlockfsm (.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM,
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.InterlockStall, .SelReplayCPURequest, .SelHPTW,
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.IgnoreRequest);
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hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
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.ITLBMissF(ITLBMissF & ~TrapM),
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.DTLBMissM(DTLBMissM & ~TrapM),
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.PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
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.HPTWReadPTE(ReadDataM),
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.DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWSize);
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// arbiter between IEU and hptw
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// multiplex the outputs to LSU
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mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLSURWM);
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mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
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mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
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mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
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mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE);
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mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw.
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mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM);
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// always block interrupts when using the hardware page table walker.
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assign CPUBusy = StallW & ~SelHPTW;
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end // if (`MEM_VIRTMEM)
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else begin
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assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF} = '0;
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assign IgnoreRequest = TrapM;
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assign CPUBusy = StallW;
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assign LSUAdrE = PreLSUAdrE; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
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assign PreLSURWM = MemRWM; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM;
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assign PreLSURWM = MemRWM; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM[`PA_BITS-1:0];
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end
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// **** look into this confusing signal.
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// This signal is confusing. CommittedM tells the CPU's trap unit the current instruction
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// in the memory stage is a memory operaton and that memory operation is either completed
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102
pipelined/src/lsu/lsuvirtmen.sv
Normal file
102
pipelined/src/lsu/lsuvirtmen.sv
Normal file
@ -0,0 +1,102 @@
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///////////////////////////////////////////
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// lsuvirtmem.sv
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//
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// Written: Ross Thompson ross1728@gmail.com January 30, 2022
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// Modified:
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//
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// Purpose: Encapsulates the hptw and muxes required to support virtual memory.
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module lsuvirtmem(
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input logic clk, reset, StallW,
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input logic [1:0] MemRWM,
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input logic [1:0] AtomicM,
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input logic ITLBMissF,
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output logic ITLBWriteF,
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input logic DTLBMissM,
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output logic DTLBWriteM,
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input logic TrapM,
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input logic DCacheStallM,
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic [`XLEN-1:0] PCF,
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input logic [`XLEN-1:0] ReadDataM,
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input logic [2:0] Funct3M,
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output logic [2:0] LSUFunct3M,
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input logic [6:0] Funct7M,
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output logic [6:0] LSUFunct7M,
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input logic [`XLEN-1:0] IEUAdrE,
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input logic [`XLEN-1:0] IEUAdrM,
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output logic [`XLEN-1:0] PTE,
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output logic [1:0] PageType,
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output logic [1:0] PreLSURWM,
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output logic [1:0] LSUAtomicM,
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output logic [11:0] LSUAdrE,
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output logic [`PA_BITS-1:0] PreLSUPAdrM,
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input logic [`XLEN+1:0] IEUAdrExtM,
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output logic InterlockStall,
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output logic CPUBusy,
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output logic SelHPTW,
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output logic IgnoreRequest);
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logic AnyCPUReqM;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic HPTWRead;
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logic [2:0] HPTWSize;
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logic SelReplayCPURequest;
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logic [11:0] PreLSUAdrE;
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assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
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interlockfsm interlockfsm (.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM,
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.InterlockStall, .SelReplayCPURequest, .SelHPTW,
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.IgnoreRequest);
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hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
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.ITLBMissF(ITLBMissF & ~TrapM),
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.DTLBMissM(DTLBMissM & ~TrapM),
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.PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
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.HPTWReadPTE(ReadDataM),
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.DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWSize);
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// arbiter between IEU and hptw
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// multiplex the outputs to LSU
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mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLSURWM);
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mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
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mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
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mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
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mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE);
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mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw.
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mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM);
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// always block interrupts when using the hardware page table walker.
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assign CPUBusy = StallW & ~SelHPTW;
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endmodule; // lsuvirtmem
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