Ross Thompson 67ff8f27f4 Can now support the following memory and bus configurations. ... 1. dtim/irom only 2. bus only 3. dtim/irom + bus 4. caches + bus		2022-03-11 15:18:56 -06:00
..
config	Can now support the following memory and bus configurations.	2022-03-11 15:18:56 -06:00
fpu-testfloat/FMA/tbgen	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-04 00:06:27 +00:00
src	Can now support the following memory and bus configurations.	2022-03-11 15:18:56 -06:00
srt	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
testbench	fix up PLIC and UART checkpointing	2022-03-07 23:48:47 -08:00