David Harris
057183bcc9
Cache code cleanup
2023-01-07 15:44:44 -08:00
David Harris
0a25f18a07
Cache code cleanup
2023-01-07 15:42:08 -08:00
David Harris
0ad707f1a5
Cache code cleanup
2023-01-07 15:39:13 -08:00
Ross Thompson
bf08c57ab0
Added branch outcome logger to testbench
2023-01-07 13:16:57 -06:00
Ross Thompson
475becb414
Removed unused rv64BP config.
2023-01-07 12:17:40 -06:00
David Harris
f541a277a8
Remove unused CACHE_ENABLED parameter
2023-01-07 09:57:24 -08:00
David Harris
33c910f952
Remove unused signals
2023-01-07 06:26:29 -08:00
David Harris
dc526c92bd
Removed unused signals
2023-01-07 06:06:54 -08:00
David Harris
01525399cc
Removed unused signals; added check for atomic in pmachecker
2023-01-07 05:59:56 -08:00
David Harris
21b9f50851
Remove conditional from inside decompress module
2023-01-07 05:51:47 -08:00
David Harris
8506f120e1
Remove unused signals
2023-01-07 05:46:22 -08:00
David Harris
44352ced64
Branch logic simplification and remove unused signals
2023-01-07 05:42:34 -08:00
David Harris
d8f0425467
vclean working; started removing unused signals
2023-01-07 05:34:58 -08:00
David Harris
f4cb652a00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2023-01-07 04:49:40 -08:00
David Harris
2188ff879b
code cleanup
2023-01-07 04:49:25 -08:00
Ross Thompson
f119b492bb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2023-01-06 15:18:13 -06:00
Ross Thompson
7223d1e05c
Added python script to post process performance counter metrics.
2023-01-06 15:15:54 -06:00
Katherine Parry
1bcb1725f5
renamed alot of signals in fpu
2023-01-06 10:35:23 -06:00
David Harris
c260354817
Removed unused UARCH configuration entries
2023-01-06 05:11:14 -08:00
Ross Thompson
01d4e942d0
Added more missing files.
2023-01-06 00:12:08 -06:00
Ross Thompson
8a5916ce66
Addd missing file.
2023-01-06 00:09:18 -06:00
Ross Thompson
09bb733088
Added code to print out performance counters at end of each test.
2023-01-05 18:00:11 -06:00
Ross Thompson
78e441fb38
More branch predictor cleanup.
2023-01-05 17:19:27 -06:00
Ross Thompson
65dd86b726
Keep around the old gshare.
2023-01-05 15:55:46 -06:00
Ross Thompson
2224679694
Added speculative gshare.
2023-01-05 14:18:00 -06:00
Ross Thompson
9d03109f34
Officially added global history with speculation to types of branch predictors.
2023-01-05 14:04:09 -06:00
Ross Thompson
0737efc86c
More branch predictor cleanup.
2023-01-05 13:36:51 -06:00
Ross Thompson
808c106504
Two bit predictor cleanup.
2023-01-05 13:27:22 -06:00
Ross Thompson
14ebf2360d
Simplified gshare.
2023-01-04 23:51:09 -06:00
Ross Thompson
0eceeeeeaa
Simiplified global history branch predictor.
2023-01-04 23:41:55 -06:00
davidharrishmc
4a2ed0142f
Update decompress.sv
...
typo
2023-01-04 17:01:26 -08:00
Katherine Parry
970318f881
forgot the normshift module
2023-01-04 10:48:19 -06:00
Katherine Parry
95a1ddd636
some commenting fixes, converter optimizations, and moves normshift into postproc
2023-01-03 15:55:30 -06:00
David Harris
43f45c62a6
Made Q4.k interface to fgen2/4 consistent
2023-01-01 15:06:32 -08:00
David Harris
3d5acc7c2a
Simplified intdiv selection logic to muxes
2023-01-01 14:04:37 -08:00
David Harris
f8af51e07b
Handle special case Int Div/Rem of |A| < |B| in a single cycle
2023-01-01 13:54:01 -08:00
David Harris
f567577ede
Fixed radix 2 k = 1 lint
2022-12-31 07:01:50 -08:00
David Harris
c1689b54bb
Fixed backward mux in fdivsqrtstage2
2022-12-31 06:55:20 -08:00
David Harris
7c7d40ad63
Broken commit starting to address radix 2 issues
2022-12-31 06:19:15 -08:00
David Harris
50af122909
Moved shared config so wally-shared only has values a user would alter
2022-12-31 05:51:42 -08:00
David Harris
3ac62c74c2
fdivsqrt post processing cleanup
2022-12-31 05:45:15 -08:00
David Harris
99b244c8c4
fdivsqrt post processing major simplification
2022-12-31 05:42:51 -08:00
David Harris
f587933fb5
fdivsqrt post processing simplification
2022-12-31 05:37:48 -08:00
David Harris
5edc925dff
fdivsqrt post processing simplification
2022-12-31 05:36:09 -08:00
David Harris
6832b9d9f6
config file, comment, postproc cleanup
2022-12-31 05:20:56 -08:00
Cedar Turek
0836d4d4f0
removed unnecessary values from shared config. unbroke division
2022-12-30 21:26:55 -08:00
Cedar Turek
e994f26d6d
simplified initU and UM logic, separated radix2/4 logic
2022-12-30 18:57:07 -08:00
Cedar Turek
fb9a0c797f
various formatting fixes and comments
2022-12-30 18:41:40 -08:00
Cedar Turek
286e43807a
added mux to intdiv result
2022-12-30 18:06:35 -08:00
Cedar Turek
ae447e42df
removed unnecessary mdue gating
2022-12-30 17:53:06 -08:00
Cedar Turek
ba90d868db
took out broken muxes
2022-12-30 15:13:52 -08:00
Cedar Turek
545a3ff363
various cleanup
2022-12-30 14:31:23 -08:00
Cedar Turek
3170130c94
Code cleanup
2022-12-30 14:13:33 -08:00
Ross Thompson
9d5213b71e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-30 15:04:54 -06:00
Ross Thompson
a538d4316f
Cleanup spill logic.
2022-12-30 14:59:51 -06:00
Ross Thompson
fdd7b68501
Signal renames for PC*NextF and SelSpillNextF.
2022-12-30 14:21:20 -06:00
Cedar Turek
158e23b5a5
commented complicated step/right shift calc
2022-12-30 12:03:10 -08:00
Cedar Turek
eef1d4dd66
comment cleaning
2022-12-30 11:11:34 -08:00
Cedar Turek
7e5cafeda3
Described internal signals of fdivsqrt top
2022-12-30 11:01:02 -08:00
Cedar Turek
8cb4a7a69a
Commented fdivsqrt module
2022-12-30 10:52:25 -08:00
Ross Thompson
ed536dd142
Removed da page fault from spill logic.
2022-12-30 12:51:56 -06:00
Cedar Turek
3115df9380
Begin commenting divsqrt
2022-12-30 10:43:02 -08:00
Ross Thompson
80a135f101
Spill only occurs on 32-bit instructions.
2022-12-30 12:41:25 -06:00
Katherine Parry
aca6f0d4e6
removed ethe second bit from fma alignment shift
2022-12-30 12:07:44 -06:00
Ross Thompson
b1f68a1d85
Modified IROM to return the correct offset when unaligned.
2022-12-30 11:48:40 -06:00
Katherine Parry
5844a596a3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-30 09:56:35 -06:00
David Harris
58218dbdd1
continued simplifying integer division special cases
2022-12-30 07:40:28 -08:00
David Harris
bd16fd79d4
started simplifying integer division special cases
2022-12-30 07:34:26 -08:00
David Harris
30dc45c764
removed duplicate quotient mux
2022-12-30 07:17:38 -08:00
David Harris
61230c967c
simplified sign handling mux
2022-12-30 07:10:47 -08:00
David Harris
ba976d66e4
Radix 4 divsqrt
2022-12-30 07:01:44 -08:00
David Harris
3c475455d9
Clean up sqrt preproc
2022-12-30 07:00:48 -08:00
David Harris
4fb8396867
Clean up sqrt initialization mux
2022-12-30 06:55:20 -08:00
David Harris
dba3ffe767
Reduced size of preproc right shift
2022-12-30 06:47:40 -08:00
David Harris
0e9bd5dab5
fdivsqrtpreproc shift simplification
2022-12-30 06:45:51 -08:00
David Harris
e9b314f902
fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression
2022-12-30 06:40:25 -08:00
David Harris
ef37070eee
Fixed register timing failure on SpecialCaseM in fdivsqrt
2022-12-29 21:09:23 -08:00
Ross Thompson
872ff619e3
Fixed problems with changes to ram2p.
2022-12-29 17:13:48 -06:00
Ross Thompson
c725b5534a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-29 17:07:53 -06:00
Ross Thompson
654b10894c
Re-enabled the branch predictor in rv64gc.
2022-12-29 17:07:50 -06:00
Katherine Parry
90eb4fc1f1
minor optimizations and renaming
2022-12-29 15:54:17 -06:00
Katherine Parry
89e8df084a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-29 12:37:51 -06:00
David Harris
776f4714af
Clean up names and comments in divsqrt
2022-12-29 08:02:44 -08:00
David Harris
6664cb9db4
Factored out hardware unique to RV64 and to IDIV
2022-12-29 07:36:26 -08:00
Katherine Parry
1b4fa38510
one bitt removed from inital lignment shift
2022-12-28 17:46:53 -06:00
Alessandro Maiuolo
7c19665dea
added script in pipelined folder to run regressions with all radix/copies configurations
2022-12-28 07:32:35 -08:00
David Harris
7780b44973
fdivsqrtfsm conditional on IDIV (fixed typo)
2022-12-27 22:16:48 -08:00
David Harris
5ee44b7405
fdivsqrtfsm conditional on IDIV
2022-12-27 22:15:45 -08:00
David Harris
db933aa7e2
fdivsqrtfsm conditional on IDIV
2022-12-27 22:14:09 -08:00
Cedar Turek
ef360f0539
idiv passing radix 2, four copies
2022-12-27 22:11:18 -08:00
Cedar Turek
4ed2c6255c
idiv passing radix 2, four copies
2022-12-27 22:10:48 -08:00
David Harris
9964fc9ebe
Moved IDIV in fdivsqrtfms into generate block
2022-12-27 22:04:50 -08:00
David Harris
a832605658
Moved IDIV for postproc into generate block
2022-12-27 22:02:14 -08:00
David Harris
d59878a886
Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc
2022-12-27 21:53:00 -08:00
Cedar Turek
a559abe554
Fixed cycles for multiple iterations. 2-copies radix 2 passing regression.
2022-12-27 21:34:27 -08:00
David Harris
665b545fd0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-27 21:30:13 -08:00
David Harris
87abed6722
cleanup
2022-12-27 21:29:36 -08:00
David Harris
6cf73cdaee
Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
2022-12-27 21:24:38 -08:00
David Harris
c08811357c
Renamed muldiv to mdu
2022-12-27 19:57:10 -08:00
Ross Thompson
a129e27502
signal name changes in ram2p.
2022-12-27 15:07:01 -06:00
Ross Thompson
66b2fbd836
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-27 15:06:25 -06:00
Ross Thompson
3f4b3a4159
Added about moving decompressed config generate.
2022-12-27 15:04:55 -06:00
David Harris
dfc0b5d1ad
Removed MDUE from unnecessary places in fdivsqrt
2022-12-27 10:42:40 -08:00
David Harris
4850d058b2
fdiv typo
2022-12-27 10:30:42 -08:00
David Harris
acc9498ae2
Made SqrtE only true on square root so gating with ~MDUE can be removed)
2022-12-27 10:27:07 -08:00
David Harris
e34b8139af
Check for non-negative W in int sign handling
2022-12-27 06:35:17 -08:00
Cedar Turek
f48b7d7ef9
fpu idiv working on all configs with 1 copy of radix 2!
2022-12-26 23:18:28 -08:00
Cedar Turek
0b14aa852d
fpu passing idiv tests on rv32gc 1 copy of radix 2!
2022-12-26 21:47:56 -08:00
Cedar Turek
bebaf08bed
took out otfc swap. updated postprocessing quotient/remainder logic for int div.
2022-12-26 21:03:56 -08:00
David Harris
c326a274ac
Fixed early termination for square root
2022-12-26 08:54:57 -08:00
David Harris
2de66e9eef
Moved fdivsqrtexpcalc to its own file
2022-12-26 08:45:43 -08:00
David Harris
a7204c9012
Removed unused DivSE from FPU
2022-12-26 07:29:19 -08:00
David Harris
fb0b2d4227
Moved floating-point tests earlier in Wally config
2022-12-25 22:31:20 -08:00
David Harris
7e77a39d32
Restored missing floating point load/store tests
2022-12-25 22:28:14 -08:00
David Harris
d627512d2b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-25 20:12:55 -08:00
Ross Thompson
4f436dc7f0
Added missing assignment for no branch predictor mode.
2022-12-24 17:08:29 -06:00
David Harris
0cc2b0fcd2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-24 12:24:38 -08:00
Ross Thompson
0d6ce1d459
Fixed bug with the performance counters not updating.
2022-12-24 14:24:17 -06:00
David Harris
10af4e4353
ALU cleanup
2022-12-24 07:18:35 -08:00
cturek
cc6f219bdd
Added A Sign register. Fixed postprocessing logic for postinc and rem calculation.
2022-12-24 06:46:52 +00:00
Ross Thompson
b0d6c9616e
Minor optimizations.
2022-12-23 20:11:36 -06:00
Ross Thompson
6e9d1eb180
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-23 19:51:23 -06:00
Katherine Parry
4b50ffac91
reworked negitive sticky bit handeling in fma
2022-12-23 17:01:34 -06:00
Ross Thompson
6f9e21d61b
Improved comment.
2022-12-23 15:13:15 -06:00
Ross Thompson
a2de53aeeb
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
fe9361de34
Removed XEnE, YEnE, and ZEnE from forward logic.
...
Cleanup comments.
2022-12-23 14:27:03 -06:00
Ross Thompson
af9afafdae
Cleanup floating point hazard logic.
2022-12-23 14:21:47 -06:00
Ross Thompson
b4c7998ded
DON'T USE. First commit in attempt to move fpustall detection into the decode stage.
2022-12-23 12:47:18 -06:00
Ross Thompson
f6f66cb79e
Removed ZForwardEnE and replaced with ZEnE.
...
Similar for YForwardEnE.
2022-12-23 12:27:51 -06:00
Ross Thompson
ca67e5588d
Removed unnecessary stall when MatchDE was driven 1 by RdE == 0.
2022-12-23 11:45:42 -06:00
David Harris
f038494760
Commented out fdiv early termination - broke fsqrt test
2022-12-23 00:58:55 -08:00
David Harris
e061bacc9d
Fixed early termination on fdivsqrt
2022-12-23 00:53:55 -08:00
David Harris
0505f1fd37
Moved InstrValidNotFLushed to csr including InstrValidM
2022-12-23 00:27:44 -08:00
David Harris
3b1fe78bdc
Removed unused StallW from CSRs
2022-12-23 00:21:36 -08:00
David Harris
9e21358d75
Removed unused signals from FPU
2022-12-23 00:18:39 -08:00
David Harris
0a7ed944a5
Revert to 98b824
2022-12-22 23:58:14 -08:00
David Harris
56312cd0a6
Clean up unused FPU signals
2022-12-22 23:53:09 -08:00
David Harris
4d509f94ec
FDIV merge
2022-12-22 23:03:03 -08:00
David Harris
2d72bed1f4
Removed unused signals in FPU and CSR
2022-12-22 22:59:05 -08:00
Ross Thompson
98b824c4c4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-22 22:51:33 -06:00
Ross Thompson
2cc4d66ded
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
03021765a6
The LSU is properly using FlushW rather than TrapM.
2022-12-22 21:47:34 -06:00
Ross Thompson
3b791b768a
Success we've replaced TrapM with FlushD in the IFU.
2022-12-22 21:36:49 -06:00
Ross Thompson
e0e92952c3
Partial cleanup for BP.
2022-12-22 20:33:38 -06:00
Ross Thompson
206bc7daa6
Closing in on icache flushed by FlushD rather than TrapM.
2022-12-22 20:19:09 -06:00
Ross Thompson
b1475df5e1
Wavefile updates.
2022-12-22 19:45:02 -06:00
Kip Macsai-Goren
a768d70093
Added status.tvm bit test that passes make and regression
2022-12-22 14:43:22 -08:00
Ross Thompson
41fe876e7a
First pass at resolving ifu flush on trap rather than FlushD.
2022-12-22 15:53:06 -06:00
David Harris
d4bedca1bf
Code cleanup
2022-12-22 10:04:50 -08:00
cturek
ccbad67497
Added negative-result int diviison support in U and UM registers. 13 tests pass!
2022-12-22 16:25:37 +00:00
cturek
1b7ed72ece
Moved swap from qslc to otfc
2022-12-22 15:44:50 +00:00
cturek
3574bedb08
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-12-22 05:45:00 +00:00
cturek
80ca75e216
Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.
2022-12-22 05:44:55 +00:00
David Harris
c42967f5c6
XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-21 20:39:38 -08:00
Ross Thompson
c8c73f47d2
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
2022-12-21 22:13:05 -06:00
cturek
0b4d81bd4a
worked out some bugs with int div cycles
2022-12-22 02:22:01 +00:00
cturek
c3fdc0ab23
Renamed signals to E and M stages, forwarded preprocessed n to fsm
2022-12-22 00:43:27 +00:00
Ross Thompson
84f8d9953f
Updated cache fsm names to match book.
2022-12-21 16:49:53 -06:00
Ross Thompson
d72cf65809
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-21 16:13:09 -06:00
Ross Thompson
e7a44d8975
Changed GatedStallF to GatedStallD.
2022-12-21 16:12:55 -06:00
David Harris
d0a3e939e3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-21 14:12:25 -08:00
David Harris
8bc753a291
Added assertion about atomics needing caches
2022-12-21 13:57:28 -08:00
cturek
0c30ecf86d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-12-21 20:41:38 +00:00
David Harris
6d46261350
comment cleanup
2022-12-21 12:39:09 -08:00
David Harris
c7f3aae084
Only delegated bits of SIP are readable
2022-12-21 12:32:49 -08:00
cturek
ab71962dc0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-12-21 19:35:57 +00:00
cturek
c479b9f112
fixed normshift calculations
2022-12-21 19:35:47 +00:00
David Harris
5ef3a1d371
git push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-21 11:31:27 -08:00
David Harris
e327d70cdc
Removed unused FPU signals
2022-12-21 11:31:22 -08:00
Ross Thompson
c3b43b2fac
Waiting on fix for wally64periph uart test.
...
would like to remove vectored interrupt adder.
2022-12-21 13:16:09 -06:00
Ross Thompson
0b4186f1e8
Vectored interrupts now require 64 byte alignment.
...
Eliminates adder.
2022-12-21 12:05:49 -06:00
Ross Thompson
91f948a91c
The optimzied PC+2/4 logic still hanges on wally32priv.
2022-12-21 09:19:34 -06:00
Ross Thompson
6858b7568c
Renamed PCPlusUpperF to PCPlus4F.
2022-12-21 09:18:30 -06:00
Ross Thompson
3d95aa3423
Added timeout check to testbench.
...
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
2022-12-21 09:18:00 -06:00
Ross Thompson
ac94b55e74
Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
...
Switched to even simplier PC+2/4 logic.
2022-12-21 09:00:09 -06:00
Ross Thompson
a02b40cf02
Changes to wave file.
2022-12-21 08:41:47 -06:00
Ross Thompson
fe723af1af
Comments about PC+2/4.
2022-12-21 08:35:43 -06:00
David Harris
5d91b3044f
Clean up vecgtored interrupts
2022-12-20 16:53:09 -08:00
David Harris
dd0a02f0c8
Converted tvecmux to structural
2022-12-20 16:24:04 -08:00
Ross Thompson
f860440361
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 18:09:37 -06:00
Ross Thompson
80be2e7be5
privileged pc mux cleanup.
2022-12-20 18:05:44 -06:00
Ross Thompson
97593e8a6f
Moved privileged pc logic into privileged unit.
2022-12-20 17:55:45 -06:00
David Harris
8f640f050f
IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI
2022-12-20 15:38:30 -08:00
Ross Thompson
35ad49502f
Implement FENCE.I as NOP when ZIFENCEI is not supported.
2022-12-20 17:34:11 -06:00
Ross Thompson
0dc09ac22d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 17:11:35 -06:00
Ross Thompson
65cbff9283
Changed long names of vectored pcm signals.
2022-12-20 17:01:20 -06:00
David Harris
f3e9950317
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-20 14:43:33 -08:00
David Harris
e7702e48b7
FPU remove unused signals
2022-12-20 14:43:30 -08:00
Ross Thompson
6f543d01b7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 16:36:44 -06:00
Ross Thompson
8029b12f2a
Renumbered bits for PCPlusUpper.
2022-12-20 16:33:49 -06:00
David Harris
caef1a6997
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-20 11:23:53 -08:00
David Harris
f0ef5caf32
Memory cleanup
2022-12-20 11:22:26 -08:00
Ross Thompson
c4901450c4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 12:58:59 -06:00
Ross Thompson
684d260005
Reorganized IFU PCNextF logic.
2022-12-20 12:58:54 -06:00
David Harris
e74d47bcb4
Renamed renamed sram to ram
2022-12-20 08:36:45 -08:00
David Harris
16f3c25cb7
sram1p1rw cleanup
2022-12-20 02:57:51 -08:00
David Harris
08234cb1c7
Remoed unused bram modules
2022-12-20 02:40:45 -08:00
David Harris
2c46f22be5
Renamed SRAM2P1R1W to lower case
2022-12-20 02:09:55 -08:00
David Harris
54e856c4f5
Renamed SRAM2P1R1W to lower case
2022-12-20 02:09:36 -08:00
David Harris
caf457106a
Replaced || and && with single ops
2022-12-20 01:33:35 -08:00
Ross Thompson
dedc08bd42
several options for pcnextf on fence.i
2022-12-19 23:33:12 -06:00
Ross Thompson
2df18cc758
More bp/ifu pcmux cleanup.
2022-12-19 23:16:58 -06:00
Ross Thompson
565585b35a
Moved more muxes inside bp.
2022-12-19 22:51:55 -06:00
Ross Thompson
d8ee0ea59d
Begin cleanup of ifu. partial move of pc muxes inside bp.
2022-12-19 22:46:11 -06:00
David Harris
e4579f3e9b
Removed CSR support from rv32i
2022-12-19 16:15:12 -08:00
David Harris
9fea16fd20
Simplified InstrRawD register
2022-12-19 15:18:42 -08:00
David Harris
a4da3f30e1
Explained hazard causes
2022-12-19 09:41:41 -08:00
David Harris
67763dbeec
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-19 09:09:57 -08:00
David Harris
3172dfd6a9
Properly decode fcvtint to prevent unnecessary stalls
2022-12-19 09:09:48 -08:00
Ross Thompson
159eda85f0
Renamed FStallD to FPUStallD.
2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
5a82898649
Added NumZeroE, AZeroM, and BZeroM
2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
2989782fe6
fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)
2022-12-18 19:04:36 -08:00
Ross Thompson
4f56e6ff5d
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
376b01fcb8
Attempted to make a cache test.
2022-12-18 17:15:08 -06:00
Ross Thompson
ebdac1a9d0
Updated tests for fpga and BP.
2022-12-18 16:24:26 -06:00
Ross Thompson
73fd3fe040
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
cdeccd78e6
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
ade06f3780
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
7d04675073
Cleanup comments.
2022-12-16 17:08:35 -06:00
Ross Thompson
89a30e7e37
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
9ebea891e2
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
731fbfc851
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
41c636ecfa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-16 15:37:03 -06:00
Ross Thompson
b462554896
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
dacba855da
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
cturek
4b8cbd9fa0
Added integer support for initC
2022-12-16 19:02:11 +00:00
Ross Thompson
bc907f3e2f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-16 12:52:22 -06:00
Ross Thompson
e425ecac96
Fixed regression-wally to correct remove and mkdir wkdir.
2022-12-16 12:51:21 -06:00
cturek
06c58f310d
Added mux for integer special case, renamed signals to match pipelined stage
2022-12-16 18:43:49 +00:00
David Harris
378c40002f
Clean up interrupt masking by Commit
2022-12-16 08:27:39 -08:00
David Harris
7989f449ad
Disabled starting FPU divider when IDIV_ON_FPU = 0
2022-12-16 06:35:29 -08:00
cturek
d7571bb9b1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-12-16 03:41:39 +00:00
David Harris
b7abc0037e
Use FlushE to reset integer divider FSM
2022-12-15 11:00:54 -08:00
David Harris
4365c99b52
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
David Harris
5b040b7935
Regression delete wkdir files to prevent spurious failures
2022-12-15 10:24:58 -08:00
David Harris
2457448e29
Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
2022-12-15 08:23:34 -08:00
Ross Thompson
fa19a111c6
Hazard cleanup.
2022-12-15 10:05:17 -06:00
Ross Thompson
e774dd2db9
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
2022-12-15 09:53:35 -06:00
Ross Thompson
b02550b05c
Merge branch 'main' into hazards
2022-12-15 08:44:59 -06:00
David Harris
33aca5d35e
Added IDIV_ON_FPU flag to control whether integer division uses FPU
2022-12-15 06:37:55 -08:00
David Harris
5f637ef4a7
Use FPU divider for integer division when F is supported
2022-12-14 17:03:13 -08:00
cturek
8829e627eb
Fixed BZero and initU/initUM muxes
2022-12-14 16:44:46 +00:00
Ross Thompson
09dcb56217
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
a3ec829b80
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-14 09:34:34 -06:00
Ross Thompson
6da7849d27
Reduced complexity of linebytemask.
2022-12-14 09:34:29 -06:00
cturek
ed59736a4b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-12-14 15:13:44 +00:00
Ross Thompson
1ba1bed0b0
Broken dont' use.
2022-12-11 23:24:01 -06:00
Ross Thompson
0716aedbd5
Removed unused flushf.
2022-12-11 16:28:11 -06:00
Ross Thompson
115e9e7bb3
Renamed CPUBusy to GatedStallF in IFU.
2022-12-11 15:54:19 -06:00
Ross Thompson
ffc5bce0b6
Renamed CPUBusy in LSU.
2022-12-11 15:52:51 -06:00
