cvw/pipelined
Ross Thompson 3d95aa3423 Added timeout check to testbench.
A watchdog checks the value of PCW.  If it does not change within 1M cycles immediately stop simulation and report an error.
2022-12-21 09:18:00 -06:00
..
config Removed CSR support from rv32i 2022-12-19 16:15:12 -08:00
misc Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
regression Changes to wave file. 2022-12-21 08:41:47 -06:00
src Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 2022-12-21 09:00:09 -06:00
testbench Added timeout check to testbench. 2022-12-21 09:18:00 -06:00