This website requires JavaScript.
Explore
Help
Register
Sign In
Xavi
/
cvw
Watch
1
Star
0
Fork
0
You've already forked cvw
forked from
Github_Repos/cvw
Code
Issues
Pull Requests
Packages
Projects
Releases
Wiki
Activity
376b01fcb8
cvw
/
pipelined
History
Ross Thompson
376b01fcb8
Attempted to make a cache test.
2022-12-18 17:15:08 -06:00
..
config
Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
2022-12-15 08:23:34 -08:00
misc
regression
Updated tests for fpga and BP.
2022-12-18 16:24:26 -06:00
src
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
testbench
Attempted to make a cache test.
2022-12-18 17:15:08 -06:00
Home