Ross Thompson 73fd3fe040 Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.		2022-12-17 23:47:49 -06:00
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config	Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE	2022-12-15 08:23:34 -08:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.	2022-12-17 23:47:49 -06:00
src	Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.	2022-12-17 23:47:49 -06:00
testbench	Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE	2022-12-15 08:23:34 -08:00