forked from Github_Repos/cvw
cdeccd78e6
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not forward data to a read from address y in cycle 2. A read form address x in cycle 2 would still require forwarding. |
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| config | ||
| misc | ||
| regression | ||
| src | ||
| testbench | ||