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1154 Commits

Author SHA1 Message Date
Thomas Fleming
c055ab272d Clean up lint errors in fpu and muldiv 
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
 2021-04-22 15:36:03 -04:00
Domenico Ottolia
787ae978d7 Fix misa synthesis bug (for real now) 2021-04-22 15:35:20 -04:00
Thomas Fleming
e7822ce20c Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
Thomas Fleming
848508530c Pass lint-wally arguments to verilator 2021-04-22 13:39:20 -04:00
Jarred Allen
8baa2a350d Add buildroot to regression test 2021-04-22 13:34:56 -04:00
Thomas Fleming
805ac5dbd7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 13:20:12 -04:00
Thomas Fleming
f9e071baf8 Temporarily disable rv64 mmu test 
Will restore once cache revamp is pushed
 2021-04-22 13:19:18 -04:00
bbracker
c796547156 greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
Ross Thompson
7c8d2e9b78 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Thomas Fleming
d22f0f9d63 Refactor tlb_ram to use flop primitives 2021-04-22 01:52:43 -04:00
Thomas Fleming
4d4ca24640 Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00
Domenico Ottolia
939e36a151 Fix misa bug 2021-04-22 00:59:07 -04:00
Thomas Fleming
88bd151d55 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-04-21 20:01:08 -04:00
Thomas Fleming
70c801331a Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Ross Thompson
50e893eec9 Fixed for the instruction spills. 2021-04-21 16:47:05 -05:00
Teo Ene
6da8530104 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-21 16:06:33 -05:00
Teo Ene
008b308b79 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Noah Boorstin
0afd5ae5f6 buildroot: add workaround for weird initial MSTATUS state 2021-04-21 16:03:42 -04:00
Ross Thompson
269ea7997c major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
 2021-04-21 08:39:54 -05:00
Domenico Ottolia
82320033d5 Add tests for stval and mtval 2021-04-21 02:31:32 -04:00
Domenico Ottolia
fed42ffe19 Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file 2021-04-21 01:12:55 -04:00
Domenico Ottolia
d5f86fadac Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
a861a37b72 Why was the linter messed up? 
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
 2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261 Progress on icache. Fixed some issues aligning the PC with instruction. Still broken. 2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Domenico Ottolia
e02ff60b07 Fix synthesis warnings for privileged unit (replace 'initial' settings) 2021-04-20 17:57:56 -04:00
Noah Boorstin
c7a09d2359 yay buildroot passes a decent amount of tests now 
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
 2021-04-19 03:26:08 -04:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Katherine Parry
204e5cb018 fixed synth bugs in fpu 2021-04-19 00:39:16 +00:00
Noah Boorstin
10c7ac7f73 slowly more buildroot progress 2021-04-18 18:18:07 -04:00
Noah Boorstin
d0a137ce0c neat verilog thing 2021-04-18 17:48:51 -04:00
Noah Boorstin
5902637632 buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9 start to add buildroot testbench 
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
 2021-04-16 23:27:29 -04:00
Jarred Allen
3868a82932 dcache lints 2021-04-15 21:13:56 -04:00
Jarred Allen
32cfbc6926 Enable linting of blocks not yet in the hierarchy 2021-04-15 21:13:40 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
a149f2f3d8 Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Domenico Ottolia
70b79ca301 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 16:57:27 -04:00
Domenico Ottolia
8c4cfa5f69 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Teo Ene
a9c6d357d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 15:29:09 -05:00
Teo Ene
7a40c27b59 Quick fix to ahblite missing default statement done in class :) 2021-04-15 15:29:04 -05:00
Thomas Fleming
e8770e3eac Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/mmu/priority_encoder.sv
 2021-04-15 16:20:43 -04:00
Thomas Fleming
e838f0bb3d Change priority encoder to avoid extra assignment 2021-04-15 16:17:35 -04:00
Thomas Fleming
2c4682c4be Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Teo Ene
cefc8ea22b Temporary change to mmu/priority_encoder.sv 
Necessary to get synth working
Original HDL is still there, just commented out
 2021-04-15 13:37:12 -05:00
Katherine Parry
0bdd3efdd5 integraded the FMA into the FPU 2021-04-15 18:28:00 +00:00
Jarred Allen
7b4b1a31ef Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Ross Thompson
534e3eaac8 Merge branch 'bpfixes' into main 2021-04-15 09:06:21 -05:00
Shreya Sanghai
75caa65df1 Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
ShreyaSanghai
80fbd66113 added localHistoryPredictor 2021-04-15 08:58:22 -05:00
Shreya Sanghai
3696bf4f2c fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
bbracker
76f50d7a69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 09:06:03 -04:00
bbracker
da22308e60 csri lint improvement 2021-04-15 09:05:53 -04:00
Jarred Allen
4d58f673b2 Add a comment to explain a detail 2021-04-14 23:14:59 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
c32fe09056 More icache bugfixes 2021-04-14 19:03:33 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
3e0ed5a2b1 busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
18a4d5fc8d busybear testbench updates 
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
 2021-04-14 00:00:27 -04:00
Thomas Fleming
bb2d433971 Fix mmu lint errors 2021-04-13 19:19:58 -04:00
Thomas Fleming
a545dcb9ae Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-13 17:15:10 -04:00
Katherine Parry
e075dc2d13 Various bugs fixed in FMA 2021-04-13 18:27:13 +00:00
Thomas Fleming
ae888b5705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
f0c926cf68 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Thomas Fleming
08a84048b6 Add lru algorithm to TLB 2021-04-13 13:37:24 -04:00
Teo Ene
0bffac2c74 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Jarred Allen
95ad9a93a4 Merge branch 'main' into cache 2021-04-13 01:10:03 -04:00
Jarred Allen
357aed75ee A few more cache fixes 2021-04-13 01:07:40 -04:00
Ross Thompson
cb52820249 Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
ushakya22
c8c2d63163 Latest IE tests with timer interupts 2021-04-08 17:53:39 -04:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Ross Thompson
75b97f1422 Created special test for driving the instruction spill error. 
The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code.

0000000000000080 <test_spill>:
  80:	42a9                	li	t0,10
  82:	0001                	nop
  84:	0001                	nop
  86:	0001                	nop
  88:	02bd                	addi	t0,t0,15
  8a:	00628e33          	add	t3,t0,t1
  8e:	01ce8963          	beq	t4,t3,a0 <match>

0000000000000092 <failure>:
  92:	557d                	li	a0,-1
  94:	8082                	ret
  96:	00000013          	nop
  9a:	00000013          	nop
  9e:	0001                	nop

00000000000000a0 <match>:
  a0:	1ffd                	addi	t6,t6,-1
  a2:	fc0f9fe3          	bnez	t6,80 <test_spill>
  a6:	4501                	li	a0,0
  a8:	8082                	ret

Instructions 0x88, 0x8a and 0x8e are read incorrectly.  However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92.  This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates.

The button of wavefile wave.do shows the exact problem in the 'icache'.
 2021-04-08 15:05:08 -05:00
bbracker
0c85b1c201 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
37bca569ff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:28:25 -04:00
bbracker
c8c87bd0d8 merge testbench 2021-04-08 14:28:01 -04:00
Katherine Parry
6e4a22ec4b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:06:51 +00:00
David Harris
5b262159cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:04:09 -04:00
David Harris
2a7dd37441 restored testbench-imperas.sv 2021-04-08 14:04:01 -04:00
Katherine Parry
21efd0cad9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:03:57 +00:00
Katherine Parry
08f45eb076 fixed FPU lint warnings 2021-04-08 18:03:21 +00:00
Katherine Parry
ebf4915440 fixed FPU lint warnings 2021-04-08 17:55:25 +00:00
ushakya22
6dc982285c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 13:55:23 -04:00
ushakya22
0dfeb76f10 Updates to WALLY-IE tests 2021-04-08 13:54:42 -04:00
David Harris
2203e64b65 merge conflict resolution 2021-04-08 13:53:56 -04:00
David Harris
aabebdb59f fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00
Noah Boorstin
5f1cd43033 try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
d6949b5b81 Update privileged testgen & helper script 2021-04-08 05:14:07 -04:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
bd310a55af Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
b3795cef2e Provide attribution link for priority encoder 2021-04-08 03:05:06 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
ushakya22
7888eacc3f MIE privilege tests with working timer interupt 2021-04-07 04:09:09 -04:00
Domenico Ottolia
9b82fbff5a Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
bbdd4e1467 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
a5dc175ab2 Merge remote-tracking branch 'refs/remotes/origin/tests' into tests 2021-04-06 21:20:55 -05:00
Ross Thompson
0a20e33971 Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Jarred Allen
4da2688c40 Fix another bug in icache 2021-04-06 17:47:00 -04:00
Jarred Allen
ecb2bc8163 Fix another bug in icache 2021-04-06 12:48:42 -04:00
Noah Boorstin
c820910b29 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
ce22a1de04 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
80a67dc906 declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
eca92041e9 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
8f4da826fb plic subword access compliance 2021-04-04 23:10:33 -04:00
Katherine Parry
f41b5a2d38 Added missing files in FPU 2021-04-04 18:09:13 +00:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
5946b860ca Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
2f503ee6b9 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Thomas Fleming
e04ad8f304 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Jarred Allen
4ebc991a65 Fix bug in icache 2021-04-03 18:10:54 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
Ross Thompson
a743acd1fd Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
e38e7aff8e Minor cleanup 2021-04-02 08:20:44 -05:00
James E. Stine
82cd900b65 Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
14cf331265 Merge branch 'main' into mmu 2021-04-01 16:29:39 -04:00
Thomas Fleming
06032936bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
3f3d8f414d Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Jarred Allen
8dc57a7706 Begin changes to direct-mapped cache 2021-04-01 13:55:21 -04:00
Shreya Sanghai
bf3f4ff5b2 fixed minor bugs in localHistory 2021-04-01 13:40:08 -04:00
James E. Stine
59dee5580c Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
ShreyaSanghai
e33007e30e added localHistoryPredictor 2021-04-01 22:22:40 +05:30
Shreya Sanghai
65e9747752 fixed bugs in global history to read latest GHRE 2021-03-31 21:56:14 -04:00
Teo Ene
6aed8eaea1 Updated MISA in coremark_bare config file 2021-03-31 20:39:02 -05:00
Noah Boorstin
4e62c7d5f5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
ddc56d8cd7 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Ross Thompson
f1107c5d7b Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
1e83810450 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
9388a9f28a Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
e35020b7dc Extend lint-wally to lint both rv32 and rv64 2021-03-30 22:42:28 -04:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58 Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
Domenico Ottolia
ae7868b166 Update privileged tests generator 2021-03-30 16:58:46 -04:00
Domenico Ottolia
47648dc721 Add all working mcause tests 2021-03-30 16:55:12 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
ushakya22
2b99a7657a privilege tests 2021-03-30 15:23:47 -04:00
Ross Thompson
a3925505bf fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
6cda818f09 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
dd0b3fde59 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
335178a1d3 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
85164c7a87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
9f0a58e193 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
aa0d0d50d8 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
606295db2f Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
edaf89e3d1 Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
d3e914f64b removed minor bugs 2021-03-25 20:29:50 -04:00
Jarred Allen
c8a88757ab Fix error when reading an instruction that crosses a line boundary 2021-03-25 18:47:23 -04:00
ShreyaSanghai
da4086db79 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
7338ddf853 Remove old icache 2021-03-25 15:46:35 -04:00
Jarred Allen
fa6e6f1724 Works for misaligned instructions not on line boundaries 2021-03-25 15:42:17 -04:00
Noah Boorstin
ee3a53de7a regression: use busybear batch instead 2021-03-25 15:34:10 -04:00
Domenico Ottolia
9e9fe5e9d3 More bug fixes for privileged tests 2021-03-25 15:05:55 -04:00
Jarred Allen
73d4dd8c15 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Noah Boorstin
9eb1786fb1 busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Brett Mathis
aedc96cd04 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Domenico Ottolia
fb00d0f209 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
ed37e933e5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Jarred Allen
feabcf2d50 Make cache output NOP after a reset 2021-03-25 13:18:30 -04:00
David Harris
dea2ec280e testgen-PIPELINE python startup 2021-03-25 13:12:18 -04:00
Shriya Nadgauda
e55a245948 adding PIPELINE tests 2021-03-25 13:07:25 -04:00
Jarred Allen
fdecd6c56c Clean up some stuff 2021-03-25 13:04:54 -04:00
Jarred Allen
15e786da0b Working for all of rv64i now, but not compressed instructions 2021-03-25 13:02:26 -04:00
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
08f4ce4438 More progress on icache controller 2021-03-25 13:01:11 -04:00
Jarred Allen
fff70bccbc Begin rewrite of icache module to use a direct-mapped scheme 2021-03-25 13:01:10 -04:00
Jarred Allen
5a86225e1c Fix bug in cache line 2021-03-25 12:59:30 -04:00
Jarred Allen
abedaf62a8 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
Jarred Allen
2f5d854f87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/uncore/dtim.sv
 2021-03-25 12:10:26 -04:00
Teo Ene
7c3963547d Config file for ppa experiments 2021-03-25 10:23:21 -05:00
David Harris
1158b3aa73 Added PPA README 2021-03-25 11:21:31 -04:00
Thomas Fleming
89a2fe5741 Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
4f01aae844 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
d52c71086a added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
ca392225df added 1 tick delay on tim reads 2021-03-25 02:15:28 -04:00
Jarred Allen
9cbdb44728 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
bbracker
6edb055f26 instrfault direspecting stalls bugfix 2021-03-25 00:44:35 -04:00
bbracker
5327dcfcc8 instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
a8b7d7a248 upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
3e656fc035 future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
f2604797fb Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Teo Ene
1e691e120b Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
9f44eb36ef Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-24 17:04:48 -05:00
Teo Ene
6a7b69ff2d Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Katherine Parry
123e63b440 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Teo Ene
07f7df82e3 Added BPTYPE to coremark_bare config 2021-03-24 16:38:29 -05:00
Ross Thompson
cdb7d15709 Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. 2021-03-24 15:56:55 -05:00
Ross Thompson
a768c0406c Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Domenico Ottolia
3909158619 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Jarred Allen
0776127c75 Give some cache mem inputs a better name 2021-03-24 12:31:50 -04:00
Jarred Allen
abf9f3b3cb Fix compile errors from const not actually being constant (why does Verilog do this) 2021-03-24 00:58:56 -04:00
Ross Thompson
ace39940b4 Fixed RAS errors. Still some room for improvement with the BTB and RAS. 2021-03-23 23:00:44 -05:00
Jarred Allen
1f01a12be9 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Ross Thompson
72d25d4443 Fixed a bunch of bugs with the RAS. 2021-03-23 21:49:16 -05:00
Katherine Parry
fb78dedae2 fixed various bugs in the FMA 2021-03-24 01:35:32 +00:00
Ross Thompson
c318606f05 Fixed the valid bit issue. Now the branch predictor is actually predicting instructions. 2021-03-23 20:20:23 -05:00
Ross Thompson
9d5c351340 fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. 2021-03-23 20:06:45 -05:00
Ross Thompson
dee5d16850 fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. 2021-03-23 16:53:48 -05:00
Jarred Allen
ebd2c60b74 Begin work on direct-mapped cache 2021-03-23 17:03:02 -04:00
Teo Ene
8556c07261 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
Ross Thompson
4836e8fe2c Simulation definitely shows the branch predictor counters and branch predictor don't work. :( 2021-03-23 14:04:58 -05:00
Ross Thompson
c7e34bd4a0 added a whole bunch of interseting test code for branches which does not work. 2021-03-23 13:54:59 -05:00
Ross Thompson
c4f7c65210 updated the branch predictor config. 2021-03-23 13:54:59 -05:00
Ross Thompson
9909bdd4d5 Added first benchmark. 2021-03-23 13:54:59 -05:00
Ross Thompson
cebb2bc44d Temporary exe2memfile0.pl script to support starting addresses of 0. 2021-03-23 13:54:59 -05:00
Ross Thompson
e6aef66853 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. 2021-03-23 13:54:59 -05:00
Noah Boorstin
355961f834 busybear: more progress 2021-03-23 14:49:30 -04:00
Shreya Sanghai
09b90557f7 PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
c16605a105 Remove deleted signal from waves 2021-03-23 14:17:17 -04:00
Noah Boorstin
0dae5401f3 busybear: more progress moving from instrf to instrrawd 2021-03-23 14:06:21 -04:00
Noah Boorstin
7fb2ebec50 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Jarred Allen
789c189260 Another tweak to regression-wally.py comments 2021-03-23 00:18:38 -04:00
Jarred Allen
34cc9b4aeb Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
e4ebb4e31e Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
2c4eda2ba3 Slight change to regression-wally.py comments 2021-03-23 00:02:40 -04:00
Jarred Allen
c47a80213e Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Noah Boorstin
3c131bb2bd start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
1592332d41 Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
43d23e3d9b busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
4160bf50b0 busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
4be19421c4 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
b4166e9fd0 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
bbracker
c3a6d6bf42 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
Jarred Allen
307e33bc7e Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00
Jarred Allen
99fa8beef3 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
7350b9f18f busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
507d8ed120 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
c4fb51fad1 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
2269879459 Merge branch 'main' into cache 2021-03-22 13:47:48 -04:00
bbracker
eea7e2e47e first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Katherine Parry
9af0ad815c fixed various bugs in the FMA 2021-03-21 22:53:04 +00:00
Jarred Allen
bab0e3b90f Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
e32291bcc2 Put Imperas testbench back 2021-03-20 18:19:51 -04:00
Jarred Allen
066dc2caac Fix bug with PC incrementing 2021-03-20 18:06:03 -04:00
Jarred Allen
e531a1b5ee Merge branch 'main' into cache 2021-03-20 17:56:25 -04:00
Jarred Allen
665c244ba1 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
43a8cb0354 Revert "Change flop to listen to StallF" 
This reverts commit f069b759be.
 2021-03-20 17:34:19 -04:00
Jarred Allen
639a718312 Fix conflicts in ahb-waves that snuck through manual merging 2021-03-20 17:16:50 -04:00
Jarred Allen
f069b759be Change flop to listen to StallF 2021-03-20 17:04:13 -04:00
Katherine Parry
fd381e60d7 messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic 2021-03-20 02:05:16 +00:00
Jarred Allen
50c961bbe4 Merge changes from main 2021-03-18 18:58:10 -04:00
Jarred Allen
bf2fbf49ee Add icache's read request to ahb wavs 2021-03-18 18:52:03 -04:00
bbracker
df51d9908d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
bbracker
11ba96f2e3 maybe AHB works now 2021-03-18 17:47:00 -04:00
Shreya Sanghai
804407eab7 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
181a28e875 Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
f35d3b39c8 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
859d242d81 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-18 14:36:42 -04:00
Thomas Fleming
062c4d40da Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Thomas Fleming
f04e554e35 Improve page table creation in python file 2021-03-18 14:27:09 -04:00
Noah Boorstin
847bf0b9a6 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
fa1407f6e3 everyone gets a bootram 2021-03-18 12:35:37 -04:00
Noah Boorstin
a226e24ed3 busybear: update memory map, add GPIO 2021-03-18 12:17:35 -04:00
Teo Ene
0ff785549e Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
db164462ed adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Jarred Allen
e39ead0460 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
29634f1475 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
e6661ea26a fix to last commit 2021-03-17 15:07:02 -05:00
Teo Ene
90946d61c5 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
083a24c06b addition to last commit 2021-03-17 14:52:31 -05:00
Teo Ene
ca901513c8 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
bccd37d778 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
74ebe0bef2 replicating coremark changes into coremark bare 2021-03-17 14:36:34 -04:00
Elizabeth Hedenberg
a3b2ffb2c9 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
7bc95ba073 Fixed issue with sim-wally-batch. Are people still using this script? 2021-03-17 11:17:52 -05:00
Ross Thompson
0e2352a6de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
31ad619a21 Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Domenico Ottolia
150faf8dd8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-16 23:27:09 -04:00
Domenico Ottolia
0b880110c9 Add test runner for privileged 2021-03-16 23:26:59 -04:00
Noah Boorstin
45ed2742cf busybear: add seperate message on bad memory access becasue its confusing 2021-03-16 21:42:26 -04:00
Noah Boorstin
162955de69 busybear: add COUNTERS define 2021-03-16 21:08:47 -04:00
Domenico Ottolia
c9d70a1778 Add privileged testbench 2021-03-16 20:28:38 -04:00
Domenico Ottolia
a40b0c6392 Add privileged tests for mcause 2021-03-16 19:22:36 -04:00
Domenico Ottolia
e44a265b9e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-16 19:12:21 -04:00
Jarred Allen
ed68d8240b Undo accidental change 2021-03-16 18:16:00 -04:00
Jarred Allen
ba7bfa9056 Condense the parallel and non-parallel wally-pipelined-batch.do files into one 2021-03-16 18:15:13 -04:00
Jarred Allen
6e7fc07fcf Change busybear to only check that first 100k instructions load 2021-03-16 17:43:39 -04:00
Shreya Sanghai
d9b1e7d67f added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Jarred Allen
3fc36b978d Fix icache for jumping into misaligned instructions 2021-03-16 16:57:51 -04:00
Domenico Ottolia
4330e6614b Add privileged tests folder 2021-03-16 16:11:20 -04:00
Shreya Sanghai
a79e26f9d8 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
98db312574 Merge remote-tracking branch 'origin/main' into cache 2021-03-16 14:17:39 -04:00
Shreya Sanghai
23a7c8cd92 made performance counters count branch misprediction 2021-03-16 11:24:17 -04:00
Shreya Sanghai
518618ad38 Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
Jarred Allen
662ab53746 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Noah Boorstin
cd58f8a12d remove regression-wally.sh 2021-03-15 19:03:57 -04:00
Noah Boorstin
6d8bcfe6bf copy Ross's branch predictor preload change into busybear 2021-03-15 18:27:27 -04:00
Ross Thompson
8e51935082 Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Ross Thompson
69aacbad4f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
The last commit message about rv32ic having issues is now invalid. Looks like the issue was resolved.
 2021-03-15 12:06:18 -05:00
Ross Thompson
d341e2d5cb Fixed the parallel script so the rv64ic passes. 
rv32ic and busybear still have issues.
 2021-03-15 12:04:59 -05:00
Jarred Allen
5b174adc2a Fix BEQZ tests 2021-03-14 15:42:27 -04:00
Jarred Allen
003242ae8a Merge upstream changes 2021-03-14 14:57:53 -04:00
Jarred Allen
c2f2caa3f6 Get non-jump case working 2021-03-14 14:46:21 -04:00
bbracker
b30ea396b8 slightly smarter dtim HREADY 2021-03-13 07:03:33 -05:00
bbracker
63bfd79009 slightly smarter dtim HREADY 2021-03-13 06:55:34 -05:00
bbracker
12721837f0 imem rd2 adrbits bugfix 2021-03-13 00:10:41 -05:00
Ross Thompson
1f37d9d2db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 20:18:35 -06:00
Ross Thompson
0edaa625e3 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
bbracker
0f49108ee6 clint HREADY signal update 2021-03-12 20:23:55 -05:00
Ross Thompson
2b9044b9aa Cleaned up the function radix exractFunctionRadix script. I should change the name as this is no longer a modelsim radix. 2021-03-12 15:29:02 -06:00
Ross Thompson
ccaaa829ce Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
0637874cac Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
David Harris
4465854423 Drafted rv32a tests 2021-03-12 00:06:23 -05:00
David Harris
d4e84c58ed 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Ross Thompson
b1d1f3995c Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Noah Boorstin
be0bd317e9 test regression script: add commented out rv32ic tests 2021-03-11 12:57:54 -05:00
Noah Boorstin
641a320894 add rv32ic regression test 2021-03-11 12:40:29 -05:00
Noah Boorstin
2dfb944d15 test regression script: parallalize better 2021-03-11 12:25:20 -05:00
Noah Boorstin
b13365365b test regression script: try adding verilator checking also 2021-03-11 07:32:31 +00:00
Noah Boorstin
8717f3604b try adding delays to test regression script 2021-03-11 06:59:50 +00:00
Noah Boorstin
c5b6ca4cc6 this is just a test for now, try to reimplement regression-wally in bash 2021-03-11 06:45:45 +00:00
Noah Boorstin
f31d7a7f5c busybear: account for CSR moving 2021-03-11 06:45:14 +00:00
Thomas Fleming
e57b6cf18c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
fe4d288589 Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
Jarred Allen
ff48a9e992 Return testbench to normal 2021-03-10 22:58:41 -05:00
Ross Thompson
f1f7884e10 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2 Added debug option to disable the function radix if not needed. 
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
 2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb I finally think I got the function radix debugger working across both 32 and 64 bit applications. 2021-03-10 14:43:44 -06:00
Noah Boorstin
2d1f63b590 change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
Ross Thompson
7b7cacbaf0 Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand. 2021-03-10 11:00:51 -06:00
Jarred Allen
c0ee17b6ac Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
81b29a3891 More progress 2021-03-09 21:16:07 -05:00
David Harris
0baa004bb4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59 WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Noah Boorstin
87e2a9b920 busybear: better NOPing out of float instructions 2021-03-08 21:24:19 +00:00
Noah Boorstin
9274d09ae2 busybear: better instrF checking 
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
 2021-03-08 19:48:12 +00:00
Noah Boorstin
08e3691e59 busybear: make a second .do file with better optimization for command line mode 2021-03-08 19:35:00 +00:00
Noah Boorstin
1fc00d41c2 busybear: load mem files from verilog instead of .do 2021-03-08 19:26:26 +00:00
David Harris
52d4a04eb0 Created atomic test vector and directories 2021-03-08 09:38:55 -05:00
Ross Thompson
a3759f585d Updated the paths to the branch predictor memory preloads for busy bear. 2021-03-05 15:36:00 -06:00
Ross Thompson
d6bc34121f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
718bfecf46 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 16:20:53 -05:00
Noah Boorstin
d3bf36b15f busybear: add branch preditor loading to do file 
(sorry to add more loading to the do instead of less)
 2021-03-05 21:01:41 +00:00
Thomas Fleming
ca2a65770c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 15:46:51 -05:00
Noah Boorstin
f0a103687e Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
Noah Boorstin
6981907521 fix wally-pipelined-batch.do to match wally-pipelined.do 2021-03-05 20:27:01 +00:00
bbracker
612f7a9ee4 added a delay to sel signals 2021-03-05 15:07:34 -05:00
bbracker
a1223ee13b more merging fixes 2021-03-05 14:36:07 -05:00
bbracker
2cd0f19129 remove deprecated mem signals 2021-03-05 14:27:38 -05:00
bbracker
420c9a11c2 refactored sim file 2021-03-05 14:25:16 -05:00
bbracker
62dd9e3075 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Noah Boorstin
464c1de03d busybear: slight testbench update 2021-03-05 19:00:40 +00:00
Thomas Fleming
97e9baa316 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
85dcbee86b Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
e48dc38869 Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Noah Boorstin
0af002eb2f busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Noah Boorstin
7208b9bcf2 busybear: better implenetation of sim-busybear-batch 2021-03-05 00:39:03 +00:00
Ross Thompson
a982ad7a9a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Ross Thompson
7902c3fdb6 updated the function radix to look at wally signals. 2021-03-04 17:31:12 -06:00
Jarred Allen
5da98b5381 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Noah Boorstin
cfcd7d1518 busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Katherine Parry
5374dca1b9 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
4591b25c86 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
6fa2bc8efe fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
10b179399c fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
8e3b74c772 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
4e6b35c8b2 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
3c86d0912a fixed various bugs 2021-03-04 22:18:19 +00:00
Jarred Allen
b0f4d8e8d4 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Thomas Fleming
38bd683f2d Merge branch 'walker' into main 2021-03-04 15:27:03 -05:00
Noah Boorstin
5c456e2d7f busybear: comment out instraccessfaultf for imem for now 2021-03-04 20:26:41 +00:00
Noah Boorstin
fde94f9057 Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
a8cd4f2b2e Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Shreya Sanghai
f95a1eadd9 fixed bugs 2021-03-04 12:59:45 -05:00
Shreya Sanghai
7cd8f1a592 added performance counters 2021-03-04 11:42:52 -05:00
bbracker
7852d866ef JALR testing 2021-03-04 10:37:30 -05:00
Ross Thompson
d0223da2f7 Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Teo Ene
27a807db95 Added stop to coremark_bare testbench 2021-03-04 07:47:07 -06:00
Teo Ene
95ce4b7daa Edited assemby of bare-metal coremark to make it run 2021-03-04 07:45:40 -06:00
Teo Ene
2723b21988 Linux CoreMark and baremetal CoreMark split into two separate tests/configs 2021-03-04 07:44:33 -06:00
Teo Ene
80f6d6c944 Linux CoreMark is operational 2021-03-04 05:58:18 -06:00
Thomas Fleming
8c410b6fbe Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
ab6ae6d3f1 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00
Thomas Fleming
7a9f866120 Move tlb into mmu directory 2021-03-04 02:39:08 -05:00
Teo Ene
b15ef47d24 Fix to 32-bit option of commit 2d40898158 2021-03-04 01:33:34 -06:00
Teo Ene
0c009fb1e6 In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches 2021-03-04 01:27:05 -06:00
Thomas Fleming
d821a1dbfa Merge branch 'main' into tlb_toy 2021-03-04 01:18:04 -05:00
Thomas Fleming
c03b540956 Generalize tlb module 
- number of tlb entries is now parameterized
- tlb now supports rv64i
 2021-03-04 01:13:31 -05:00
Teo Ene
a82a123069 Implemented fix disucssed with Elizabeth 2021-03-03 18:17:53 -06:00
Thomas Fleming
692d4152fa Begin hardware page table walker 2021-03-03 17:13:45 -05:00
Thomas Fleming
5fd521d333 Create virtual memory ad-hoc test 
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
 2021-03-03 17:06:37 -05:00
Teo Ene
d3a1afe50e Fix to last push 2021-03-03 15:20:38 -06:00
Teo Ene
b50faef94d Updated coremark .do file for easier debugging 2021-03-03 15:10:39 -06:00
Teo Ene
e30645a4f1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-02 17:23:44 -06:00
Teo Ene
d02e22feac Updated coremark .do file for easier debugging 2021-03-02 17:23:39 -06:00
Noah Boorstin
beb2beabfd busybear: add sim-busybear and sim-busybear-batch based on sim-wally 2021-03-01 21:01:15 +00:00
Noah Boorstin
923489fe16 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
b6dc0a8707 busybear: only check pc when it actually changes 2021-03-01 19:08:35 +00:00
Noah Boorstin
b3247eadd2 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
Noah Boorstin
f11b3108d8 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
David Harris
23a1cf63b3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-01 00:09:55 -05:00
David Harris
6f4e8b723e Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Teo Ene
2d40898158 Properly implemented the fix from commit 5fee65231e 2021-02-28 22:22:04 -06:00
Noah Boorstin
a267115635 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
17715085ba busybear: start preloading bootmem 2021-02-28 20:43:57 +00:00
Noah Boorstin
932bc0ef85 busybear: check instead of providing InstrF 2021-02-28 16:46:53 +00:00
Noah Boorstin
856a1079cc busybear: change sstatus, mstatus reset value 2021-02-28 16:19:03 +00:00
Noah Boorstin
2769b147cb busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489 busybear: remove gpio, start adding 2nd ram 2021-02-28 06:02:40 +00:00
Noah Boorstin
0596d61a2a busybear: instantiate normal wallypipelinedsoc 2021-02-28 06:02:21 +00:00
Ross Thompson
6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6 Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
David Harris
73920282af Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
0258901865 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
kaveh pezeshki
e8b306bcba merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
Noah Boorstin
4c7b185d90 busybear: add main ram loading, better instr checking also 2021-02-26 20:26:54 +00:00
kaveh Pezeshki
2782ca2480 fixed sensitivity list on error checking always block, removed useless once and for all 2021-02-26 13:41:16 -05:00
kaveh pezeshki
adadc21fc6 restored 2021-02-26 02:22:08 -08:00
David Harris
225102047a Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
1b61d78ac2 Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
David Harris
bad180fc15 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-25 15:49:38 -05:00
David Harris
f57096a5d2 Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
Brett Mathis
b0a5052bcf FPU Assembly tests 2021-02-25 14:32:36 -06:00
Teo Ene
a35fdac75b Fixed previous commit 2021-02-25 11:24:44 -06:00
Teo Ene
5fee65231e Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. 2021-02-25 11:23:01 -06:00
Teo Ene
b9701293a0 Changed TIMBASE in coremark config file 2021-02-25 11:03:41 -06:00
Teo Ene
8491deb1a9 Changed .do file back to run all 2021-02-25 09:58:54 -06:00
David Harris
cd4ba8831c Merged bus into main 2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3 Added provisional coremark files from work with Elizabeth 2021-02-24 20:07:07 -06:00
kaveh pezeshki
251aa982eb condensed always blocks to avoid race conditions 2021-02-24 11:35:28 -08:00
Noah Boorstin
ddaf67c043 busybear: preload bootram 
thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
 2021-02-24 18:46:09 +00:00
David Harris
38b8cc652c All tests passing with bus interface 2021-02-24 07:25:03 -05:00
kaveh pezeshki
06f73fe5fe added comments for RAM and bootram, removed trailing whitepace 2021-02-23 21:28:33 -08:00
Noah Boorstin
b7f4e72eec busybear: add bootram section in the same manner as ram 2021-02-24 02:02:28 +00:00
Noah Boorstin
914a36e3e8 busybear: add support for subwords in ram 
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
 2021-02-24 01:51:18 +00:00
Noah Boorstin
7b7e87bd0b busybear: start adding ram 2021-02-23 22:01:23 +00:00
Katherine Parry
07641203ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-23 20:21:53 +00:00
Katherine Parry
906ec30339 inital FMA push 2021-02-23 20:19:12 +00:00
Noah Boorstin
5394d38e4a busybear: remove unused signals 2021-02-23 19:38:19 +00:00
Noah Boorstin
c42c485377 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
David Harris
7737b0f709 Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8 Debugging Bus interface 2021-02-22 13:48:30 -05:00
kaveh pezeshki
e146946e58 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
c856003f73 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
06e975ac2f minor change to wave file. 2021-02-19 09:08:13 -06:00
Ross Thompson
7d6093b302 Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
Thomas Fleming
ca51e7ca1c Create simple TLB 
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
 2021-02-18 18:06:09 -05:00
David Harris
87ad559a90 Updated creation date of mul 2021-02-18 08:13:08 -05:00
Ross Thompson
8cbc9f7e51 Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. 
Once combined with some simulation verilog this will display the current function in modelsim.
 2021-02-17 22:20:28 -06:00
Ross Thompson
bbe0db3ebe Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
David Harris
fe7299c155 Resotred part of multiplier for lab 2 2021-02-17 16:14:04 -05:00
David Harris
492ec0ee78 Removed multiplier for lab 2 2021-02-17 16:06:16 -05:00
David Harris
e8d3c7d9e7 Multiplier tweaks 2021-02-17 16:00:27 -05:00
David Harris
e64e8afb7f Started to integrate OSU divider 2021-02-17 15:38:44 -05:00
David Harris
a7dd20b388 Multiply instructions working 2021-02-17 15:29:20 -05:00
Noah Boorstin
43f9abdbed busybear testbench: check (almost) all the CSRs 2021-02-16 20:03:24 -05:00
David Harris
adc5d5bc1a Added MUL 2021-02-15 22:27:35 -05:00
Ross Thompson
ca546beaf8 We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. 
This is not yet tested but the system verilog does compile.
 2021-02-15 14:51:39 -06:00
David Harris
3900abeb86 WALLY ALU tests 2021-02-15 10:16:31 -05:00
David Harris
cc42655789 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
Domenico Ottolia
3ee975dd5a Add privileged test cases 2021-02-14 17:01:46 -05:00
Ross Thompson
935e9e59e9 added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior. 2021-02-14 15:13:55 -06:00
Ross Thompson
8486f426b7 The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables. 2021-02-14 11:06:31 -06:00
Shreya Sanghai
4e887f83a3 added branch tests 2021-02-12 22:40:08 -05:00
Noah Boorstin
84d856d1e5 busybear: allow testbench to ignore lack of MMU for now 
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing

If it is, we're at 1M instructions!
 2021-02-12 20:08:56 +00:00
Noah Boorstin
dd3a5b74a1 busybear: slightly neater error handling 2021-02-12 17:21:56 +00:00
bbracker
deb7780897 bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
Noah Boorstin
79fb83409f bump into virtual/physcial memory? 2021-02-11 23:06:12 -05:00
Noah Boorstin
e89af96bc0 busybear: more updates 
now gets to instruction 839037 before failing
also updates to match new gdb output format

umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
 2021-02-11 22:42:58 -05:00
Tejus Rao
fb6a4bbbf0 added test cases for ADDW, SUBW, SLLW, SRLW, SRAW 2021-02-11 13:38:38 -05:00
Teo Ene
5f84ed407c Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts 2021-02-10 20:48:39 -06:00
ethan-falicov
7925fe3131 Fixed merge conflict stuff 2021-02-10 10:03:30 -05:00
ethan-falicov
06517631cc More merge conflicts yay 2021-02-10 09:54:30 -05:00
ethan-falicov
863796b3c1 Merge conflict fixing 2021-02-10 09:45:47 -05:00
ethan-falicov
67662b888e Adding I Type test cases from Lab 1 2021-02-10 09:39:43 -05:00
David Harris
b121b90b28 Debugging bus interface. 2021-02-10 01:43:54 -05:00
David Harris
842c374de9 Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
74bc4c0444 Fixed lw by delaying read value by one cycle 2021-02-07 23:28:21 -05:00
David Harris
33110ed636 Data memory bus integration 2021-02-07 23:21:55 -05:00
Jarred Allen
e334475ab5 Fix compile error in imperas testbench 2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
805817cda4 merge conflict? 2021-02-07 02:34:49 -05:00
Noah Boorstin
01b1b1705d Busybear: next week of updates 
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
 - parsed first 1M instructions, and now parse from split GDB runs
 - now at about 230k instructions, can't progress further for now since atomic instructions
   aren't implemented yet
 2021-02-07 03:14:48 +00:00
Jarred Allen
29b7a0cd25 Actually run the WALLY-LOAD tests 2021-02-06 14:56:40 -05:00
Jarred Allen
a3f2f4c7bc Add test vector set for load instructions 2021-02-06 13:05:59 -05:00
bbracker
15c0b4af22 JAL testing 2021-02-05 08:08:42 -05:00
Noah Boorstin
c03f69fb80 Change CSR reset and available bits to conform to OVPsim 
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
 2021-02-04 22:03:45 +00:00
Thomas Fleming
8d7a515ae7 Complete STORE tests 2021-02-04 15:38:22 -05:00
Noah Boorstin
fc734eb14e busybear: add more CSRs 2021-02-04 20:13:36 +00:00
Noah Boorstin
77a88d8019 busybear: check initial values also 2021-02-04 19:22:09 +00:00
Brett Mathis
11e2666bb2 Parallel FSR's and F CTRL logic 2021-02-04 02:25:55 -06:00
Jarred Allen
088fbbcbf0 Change busybear test to use work-busybear library 2021-02-03 11:12:47 -05:00
Jarred Allen
f700efc2b3 Start on a test set for loads 2021-02-03 00:37:43 -05:00
David Harris
2a80bcf543 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 19:44:43 -05:00
David Harris
756352f129 Minor tweaks 2021-02-02 19:44:37 -05:00
Jarred Allen
e5bd749e2a Refactor regression test 2021-02-02 17:22:29 -05:00
Noah Boorstin
d2064987e9 Add busybear testbench to nightly regression checking 
If you don't like how I did this please feel free to undo it
 2021-02-02 22:05:35 +00:00
Noah Boorstin
b5f474d9f5 same thing but do that right this time 2021-02-02 21:47:15 +00:00
Noah Boorstin
6dd5c42d55 change undefined syntax in extend.sv 
don't need verilator execption anymore
 2021-02-02 21:39:20 +00:00
David Harris
429f48e766 Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
David Harris
9f9c3bcece Changed DTIM latency to 2 cycles 2021-02-02 14:22:12 -05:00
David Harris
616830a3f0 Cleaned up hazard interface 2021-02-02 13:53:13 -05:00
David Harris
587a343dac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 13:42:35 -05:00
David Harris
229bde5953 Moved LoadStall generation to IEU 2021-02-02 13:42:23 -05:00
David Harris
bb83fda1d8 Moved writeback pipeline registers from datapth into DMEM and CSR 2021-02-02 13:02:31 -05:00
Jarred Allen
da43b2be53 Fix intermittent errors caused by weird library stuff 2021-02-02 11:20:09 -05:00
Noah Boorstin
f1768ee50b Busybear: start checking CSRs 
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)

and 3 of the CSRs referenced are skipped because of weird locations for them

oh and this doesn't check their initial state, just their changing. This could be a problem
 2021-02-02 06:06:03 +00:00
David Harris
92bf1674b4 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
Jarred Allen
f143518b23 Fix issues in parallel regression testing 2021-02-01 23:29:03 -05:00
Noah Boorstin
38265c03b7 busybear: start adding CSR checking 
@kaveh is there a less verbose way to do this?
 2021-02-01 22:08:51 -05:00
Brett Mathis
bcb722272e OSU FPU IP initial commit 2021-02-01 19:33:43 -06:00
Noah Boorstin
d592db79c9 busybear: change register file checking to only store register changed 
this should make parsedRegs.txt much smaller
 2021-02-02 01:27:43 +00:00
Noah Boorstin
71f5bb0ce8 Add PCW checking 
for now, doesn't check InstrW because it fails on compressed instructions
 2021-02-01 23:57:33 +00:00
David Harris
1a3963bed0 Renamed DCU to DMEM 2021-02-01 18:52:22 -05:00
Jarred Allen
5cf3d188c6 Parallelize regression-wally.p 2021-02-01 15:40:27 -05:00
Noah Boorstin
1b9ec8b339 busybear: print warning when NOPing out instructions 2021-02-01 19:44:56 +00:00
Noah Boorstin
a82f8977c6 busybear: NOP out floating point instructions for now 
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
 2021-01-30 19:52:47 +00:00
Noah Boorstin
cca60ed06d update busybear testbench to conform to new structure 
aaaaaaaaaaaaaaaaaahhhh so many changes

also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
 2021-01-30 19:19:00 +00:00
David Harris
07af481b67 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
David Harris
29313a108b Working on reading instruction from TIM 2021-01-30 01:57:51 -05:00
David Harris
5429424871 Adding stalls for memory delays 2021-01-30 01:43:49 -05:00
David Harris
26c560fba3 Added HCLK and HRESETn 2021-01-30 00:56:12 -05:00
David Harris
9511dcac84 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
9297376873 Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team 2021-01-29 18:06:36 -05:00
David Harris
6c76962847 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 17:29:01 -05:00
David Harris
9530039e3d Implemented adrdec for uncore 2021-01-29 17:28:53 -05:00
Teo Ene
5e5e03c717 - Removed latch on CSRCReadValM in csrc.sv 
- Changed top level to wallypipelinedhart
 2021-01-29 15:56:51 -06:00
David Harris
6d5b01357d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 15:38:01 -05:00
David Harris
d104e5a4be Moving data memory to uncore 2021-01-29 15:37:51 -05:00
Teo Ene
f0bbd71874 Added AHBW to rv32ic config file as well 2021-01-29 12:29:08 -06:00
Noah Boorstin
7183910c84 update busybear testbench to conform to new structure 2021-01-29 17:46:50 +00:00
David Harris
4687d6998a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 01:07:22 -05:00
David Harris
e4e95bf941 Added ahblite bus interface unit 2021-01-29 01:07:17 -05:00
Noah Boorstin
0fa7cffb11 busybear: lie about MISA to match OVP's MISA 2021-01-29 00:58:56 -05:00
Noah Boorstin
84e4193db6 busybear testbench: test on first 100k instrs 
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
 2021-01-29 00:14:23 -05:00
David Harris
aedadb7703 Renamed modules in privileged unit 2021-01-28 23:21:12 -05:00
David Harris
70554b94c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-28 21:40:57 -05:00
David Harris
004cc525e2 Hint to optimize ifu 2021-01-28 21:40:48 -05:00
Noah Boorstin
c4964352f0 busybear: simulate first 10k instructions 
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
 2021-01-28 19:44:58 -05:00
Noah Boorstin
96ceac0e80 busybear: fix misaligned writing checking 2021-01-28 19:35:09 -05:00
Noah Boorstin
df1d174aea busybear: add more test instructions 
currently testing first 1k instrs
 2021-01-28 16:41:37 -05:00
Noah Boorstin
9c0580f2e1 oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench 2021-01-28 16:35:12 -05:00
Noah Boorstin
cbab07967a more of the same fixes 2021-01-28 16:26:15 -05:00
Noah Boorstin
03cea6e29b more misaligned read fixing 
I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
 2021-01-28 16:14:35 -05:00
David Harris
3e786729ac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-28 15:44:14 -05:00
David Harris
1ad69b52d5 Fixed floating signals in clint and ieu 2021-01-28 15:44:05 -05:00
Noah Boorstin
e65166bec5 busybear testbench: understand bytemask for writes 2021-01-28 15:42:47 -05:00
David Harris
8eebf01dca Fixed c.jr instruction improperly writing ra 2021-01-28 15:18:23 -05:00
Noah Boorstin
9a45b49536 busybear: ret is only 1 word 2021-01-28 14:47:40 -05:00
Noah Boorstin
5a5237b908 add speculative exception for compressed instructions 2021-01-28 14:40:35 -05:00
Noah Boorstin
632fecf43a testbench now understands lw not aligned to 8 bytes 
also busybear now has first 500 instead of 100 instrs
and prints current instrs less
 2021-01-28 13:33:22 -05:00
Noah Boorstin
e19af0a52a busybear testbench: check for read data address also 
and check for more end of files better
 2021-01-28 13:16:38 -05:00
Noah Boorstin
7fd73d12e9 update busybear testbench to conform to new structure 2021-01-28 01:21:47 -05:00
Noah Boorstin
be3d024527 Busybear test now processes first 100 instrs correctly! 
- changed test parser to recognize lw in addition to lw

also, added temporary questa files (wlft*) to .gitignore
 2021-01-28 01:19:27 -05:00
Noah Boorstin
ed85fda42a fix memory write address decoding for busybear tests 2021-01-28 01:19:26 -05:00
David Harris
52d6a01cea Created DCU and moved memdp into DCU 2021-01-28 01:03:12 -05:00
David Harris
01e37210ea Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-28 00:22:11 -05:00
David Harris
af25784b61 Provided PC + 2 or 4 (PCLink) for JAL 2021-01-28 00:22:05 -05:00
Noah Boorstin
840528a05f update busybear testbench to conform to new structure 2021-01-27 23:42:19 -05:00
David Harris
9d821aab0f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 22:49:55 -05:00
David Harris
37a58cea17 Repartitioned with Instruction Fetch Unit, Integer Execution Unit 2021-01-27 22:49:47 -05:00
Noah Boorstin
74e57a8472 update busybear testbench to conform to new structure 2021-01-27 12:54:09 -05:00
David Harris
db5f45c240 Moved privileged unit from datapath to hart 2021-01-27 07:46:52 -05:00
David Harris
092edf953e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 06:40:39 -05:00
David Harris
4318629b32 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
Noah Boorstin
91564c7ab1 show instruction assembly in waveform 2021-01-26 12:34:12 -05:00
Noah Boorstin
91dcffa26f Update busybear tests to conform to new directory structure 2021-01-25 20:37:18 -05:00
Noah Boorstin
09c92a6b5d Fixed mem write checking 
now passes around 50 instructions!
 2021-01-25 20:07:08 -05:00
Noah Boorstin
05d4f2d33d fix speculation ignoring for PC fetching 2021-01-25 20:07:06 -05:00
David Harris
b7988e536f Reset Vector moved to config file 2021-01-25 15:57:36 -05:00
David Harris
bf07ec92b5 Added test configurations 2021-01-25 11:28:43 -05:00
Noah Boorstin
1d71282332 small busybear testbench changes 2021-01-24 20:43:47 -05:00
Noah Boorstin
7afa48d4ea Linux testbench works now 
Added parameterized PCSTART to allow compatibility between imperas and busybear tests
Hopefully we are done with the "busybear" branch, please don't use it for future work
 2021-01-24 17:10:00 -05:00
Noah Boorstin
c7e2259af0 Merge branch 'busybear' into main 
Merging busybear testbench into main, keeping main edits of wally src
 2021-01-24 16:28:36 -05:00
Noah Boorstin
6d84658369 sucessfully simulate first 30 instructions 
still need to find a better solution to InstrAccessFault/DataAccessFault though
 2021-01-23 19:01:44 -05:00
Noah Boorstin
71883dca82 More linux testbench fixes 
So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(

This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.

Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
 2021-01-23 17:52:05 -05:00
Noah Boorstin
117713be89 Linux test now gets through first 8 instructions! 
fixes the python parser:
  get the value, not function name, of PC
  only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
 2021-01-23 16:46:45 -05:00
David Harris
b77ef491fc Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh 2021-01-23 10:48:12 -05:00
David Harris
556e815c4b Cleaned up regfile x0 tied to gnd 2021-01-23 10:22:20 -05:00
David Harris
c6c5dcb2ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-23 10:19:28 -05:00
David Harris
b28129fcc3 Initial checkin of UART 2021-01-23 10:19:09 -05:00
Noah Boorstin
a66bd9008c slightly more info on errors, add instruction decoding 2021-01-22 21:14:45 -05:00
Noah Boorstin
cdcacb8dbe change how testbench reads data 
we're not sure if this is a good idea, but for now, we broke things up into 3 seperate
files, each read seperately. One for pc and instructions, one for registers, and one for
memory reads. Each is scrolled through essentially independantly: new pc data is read and checked
whenever pc changes, new register data is checked whenever any register changes, and a new mem
read value is gotten whenever DataAdrM or MemRWM changes and MemRWM is not zero. I'm not super
sure about the last one. Currently it looks like things should be working, but it goes wrong after,
like, 3 instructions.
 2021-01-22 20:27:01 -05:00
Noah Boorstin
379fc6d5ca change regfile to not hold state of x0 2021-01-22 15:12:33 -05:00
Noah Boorstin
adfeb29b77 change regfile to not hold state of x0 2021-01-22 15:11:55 -05:00
Noah Boorstin
5b0070ac0b Start adding register checking 
I'm now realizing we need to simulate loads, or else these will all be wrong
 2021-01-22 15:11:13 -05:00
Noah Boorstin
6d88c57f0f load instructions from file line by line 2021-01-22 14:11:17 -05:00
Noah Boorstin
3f2820646d More testbench setup work 
- Copy bare-bones testbench from E85
   - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier
 - Create .gitignore for vsim files
 - Make PC reset a macro, change to 0x1000 to conform to the bootloader

I don't know a good way to put the linux register trace file we're generating on git,
since its both nontrivial to make and way to big to keep in a git repo

for now it lives in /mnt/scratch/riscv_testbench/
 2021-01-21 17:55:05 -05:00
Noah Boorstin
b93a37cdb6 copy testbench to modify for busybear 2021-01-21 16:17:34 -05:00
David Harris
2f24249d17 testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64 2021-01-20 01:04:28 -05:00
David Harris
9679345cae testgen-ADD-SUB initial untested 2021-01-19 22:58:56 -05:00
David Harris
820312bc87 Initial testgen checkin 2021-01-19 13:09:56 -05:00
David Harris
f9ad54f18c Changed to . notation for instantiation, cleaned up dmem 2021-01-18 20:16:53 -05:00
David Harris
dacc392c95 cleanup 2021-01-18 00:42:40 -05:00
David Harris
dc4f00c975 Sped up exe2memfile.pl 2021-01-17 18:45:19 -05:00