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More linux testbench fixes

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So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(

This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.

Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
This commit is contained in:
Noah Boorstin 2021-01-23 17:52:05 -05:00
parent 117713be89
commit 71883dca82
2 changed files with 10 additions and 6 deletions
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6
wally-pipelined/src/testbench-busybear.sv
View File

@ -15,6 +15,10 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
logic InstrAccessFaultF, DataAccessFaultM;
logic TimerIntM, SwIntM; // from CLINT
logic ExtIntM = 0; // not yet connected
// for now, seem to need these to be zero until we get a better idea
assign InstrAccessFaultF = 0;
assign DataAccessFaultM = 0;
// instantiate processor and memories
wallypipelinedhart #(XLEN, MISA, ZCSR, ZCOUNTERS) dut(.ALUResultM(DataAdrM), .*);
@ -101,7 +105,7 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
// then expected PC value
scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
//check things!
if (PCF != pcExpected) begin
if (PCF !== pcExpected) begin
$display("%t ps: PC does not equal PC expected: %x, %x", $time, PCF, pcExpected);
// $stop;
end

10
wally-pipelined/wally-busybear.do
View File

@ -78,11 +78,11 @@ add wave -hex /testbench_busybear/dut/dp/regf/rf[29]
add wave -hex /testbench_busybear/dut/dp/regf/rf[30]
add wave -hex /testbench_busybear/dut/dp/regf/rf[31]
add wave /testbench_busybear/InstrFName
##add wave -hex /testbench_busybear/dut/dp/PCD
add wave -hex /testbench_busybear/dut/dp/PCD
#add wave -hex /testbench_busybear/dut/dp/InstrD
add wave /testbench_busybear/InstrDName
#add wave -divider
##add wave -hex /testbench_busybear/dut/dp/PCE
add wave -hex /testbench_busybear/dut/dp/PCE
##add wave -hex /testbench_busybear/dut/dp/InstrE
add wave /testbench_busybear/InstrEName
#add wave -hex /testbench_busybear/dut/dp/SrcAE
@ -90,14 +90,14 @@ add wave /testbench_busybear/InstrEName
#add wave -hex /testbench_busybear/dut/dp/ALUResultE
#add wave /testbench_busybear/dut/dp/PCSrcE
#add wave -divider
##add wave -hex /testbench_busybear/dut/dp/PCM
add wave -hex /testbench_busybear/dut/dp/PCM
##add wave -hex /testbench_busybear/dut/dp/InstrM
add wave /testbench_busybear/InstrMName
#add wave /testbench_busybear/dut/dmem/dtim/memwrite
#add wave -hex /testbench_busybear/dut/dmem/AdrM
#add wave -hex /testbench_busybear/dut/dmem/WriteDataM
#add wave -divider
#add wave -hex /testbench_busybear/dut/dp/PCW
add wave -hex /testbench_busybear/dut/dp/PCW
##add wave -hex /testbench_busybear/dut/dp/InstrW
add wave /testbench_busybear/InstrWName
#add wave /testbench_busybear/dut/dp/RegWriteW
@ -121,6 +121,6 @@ add wave /testbench_busybear/InstrWName
#set DefaultRadix hexadecimal
#
#-- Run the Simulation
run 100
run 300
#run -all
##quit