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https://github.com/openhwgroup/cvw
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busybear: start adding ram
This commit is contained in:
Noah Boorstin
parent
5394d38e4a
commit
7b7e87bd0b
@ -48,6 +48,8 @@ add wave /testbench_busybear/lastInstrF
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add wave /testbench_busybear/speculative
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add wave /testbench_busybear/lastPC2
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add wave -divider
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add wave -hex /testbench_busybear/readPC
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add wave -hex /testbench_busybear/readRAM
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
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@ -140,18 +140,18 @@ module testbench_busybear();
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if ($time == 0) begin
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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$display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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`ERROR
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end
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end else begin
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scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (i != regNumExpected) begin
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$display("%t ps, instr %0d: wrong register changed: %0d, %0d expected", $time, instrs, i, regNumExpected);
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$display("%0t ps, instr %0d: wrong register changed: %0d, %0d expected", $time, instrs, i, regNumExpected);
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`ERROR
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end
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if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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$display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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`ERROR
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end
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if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
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@ -162,6 +162,27 @@ module testbench_busybear();
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end
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end
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endgenerate
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`define MAX_RAM 'h8000000
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logic [`XLEN-1:0] RAM[`MAX_RAM:0];
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logic [`XLEN-1:0] readRAM, readPC;
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integer RAMAdr, RAMPC;
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assign RAMAdr = HADDR - 'h80000000;
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assign RAMPC = PCF - 'h80000000;
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always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
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if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
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if (HWRITE) begin
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RAM[RAMAdr] = HWDATA;
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end else begin
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readRAM = RAM[RAMAdr];
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end
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end
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end
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always @(PCF) begin
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if (PCF >= 'h80000000 && PCF <= 'h87FFFFFF) begin
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readPC = RAM[RAMPC];
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end
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end
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logic [`XLEN-1:0] readAdrExpected;
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// this might need to change
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@ -175,7 +196,12 @@ module testbench_busybear();
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scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
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#1;
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if (~equal(HADDR,readAdrExpected,4)) begin
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$display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
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$display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
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`ERROR
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end
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if (HRDATA != readRAM && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
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$display("warning %0t ps, instr %0d: HRDATA does not equal readRAM: %x, %x from address %x", $time, instrs, HRDATA, readRAM, HADDR);
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warningCount += 1;
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`ERROR
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end
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end
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@ -183,7 +209,7 @@ module testbench_busybear();
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logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
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// this might need to change
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always @(HWDATA or HADDR or HSIZE) begin
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always @(HWDATA or HADDR or HSIZE or HWRITE) begin
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#1;
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if (HWRITE) begin
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if($feof(data_file_memW)) begin
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@ -193,11 +219,11 @@ module testbench_busybear();
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
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if (writeDataExpected != HWDATA) begin
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$display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
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$display("%0t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
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`ERROR
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end
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if (~equal(writeAdrExpected,HADDR,1)) begin
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$display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected);
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$display("%0t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected);
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`ERROR
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end
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end
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@ -226,17 +252,17 @@ module testbench_busybear();
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scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
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scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
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if(CSR.icompare(`"CSR`")) begin \
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$display("%t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \
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$display("%0t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \
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end \
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if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
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$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
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$display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
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`ERROR \
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end \
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end else begin \
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for(integer j=0; j<totalCSR; j++) begin \
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if(!StartCSRname[j].icompare(`"CSR`")) begin \
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if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
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$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
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$display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
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`ERROR \
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end \
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end \
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@ -299,11 +325,11 @@ module testbench_busybear();
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// then expected PC value
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scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
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if(~equal(dut.hart.ifu.PCW,PCWExpected,2)) begin
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$display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.hart.ifu.PCW, PCWExpected);
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$display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.hart.ifu.PCW, PCWExpected);
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`ERROR
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end
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//if(it.InstrW != InstrWExpected) begin
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// $display("%t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected);
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// $display("%0t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected);
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//end
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end
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end
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@ -372,9 +398,13 @@ module testbench_busybear();
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//check things!
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if ((~speculative) && (~equal(PCF,pcExpected,3))) begin
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$display("%t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
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$display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
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`ERROR
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end
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if (readPC != InstrF) begin
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$display("%0t ps, instr %0d: readPC does not equal InstrF: %x, %x", $time, instrs, readPC, InstrF);
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warningCount += 1;
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end
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end
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end
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