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https://github.com/openhwgroup/cvw
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Fix bugs with privileged tests
This commit is contained in:
Domenico Ottolia
parent
ed37e933e5
commit
fb00d0f209
63
wally-pipelined/regression/wally-privileged.do
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63
wally-pipelined/regression/wally-privileged.do
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@ -0,0 +1,63 @@
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# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined.do ../config/rv32ic
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switch $argc {
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0 {vlog +incdir+../config/rv64ic ../testbench/testbench-privileged.sv ../src/*/*.sv -suppress 2583}
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1 {vlog +incdir+$1 ../testbench/testbench-privileged.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
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}
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench -o workopt
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vsim workopt
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view wave
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-- display input and output signals as hexidecimal values
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do ./wave-dos/default-waves.do
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-- Set Wave Output Items
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TreeUpdate [SetDefaultTree]
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WaveRestoreZoom {0 ps} {100 ps}
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 140
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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set DefaultRadix hexadecimal
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-- Run the Simulation
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#run 4100
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run -all
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#quit
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@ -1,12 +1,11 @@
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///////////////////////////////////////////
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// testbench-privileged.sv
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// testbench-imperas.sv
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//
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// Written: Ben Bracker (bbracker@hmc.edu) 11 Feb. 2021, Tiny Modifications: Domenico Ottolia (dottolia@hmc.edu) 16 Mar. 2021
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// Based on: testbench-imperas.sv by David Harris
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs meant to test peripherals
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// These tests assume the processor itself is already working!
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// Applies test programs from the Imperas suite
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//
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// A component of the Wally configurable RISC-V project.
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//
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@ -28,6 +27,9 @@
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`include "wally-config.vh"
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module testbench();
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parameter DEBUG = 0;
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parameter TESTSBP = 0;
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logic clk;
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logic reset;
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@ -36,13 +38,13 @@ module testbench();
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logic [`XLEN-1:0] signature[0:10000];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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//logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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//string tests64i[] =
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string tests[] = '{
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"rv64p/WALLY-CAUSE", "0"
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};
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"rv64p/WALLY-CAUSE", "4000"
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};
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string ProgramAddrMapFile, ProgramLabelMapFile;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] HADDR;
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@ -57,9 +59,26 @@ module testbench();
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// pick tests based on modes supported
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// *** actually I no longer support this
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// would need to put this back in if you wanted to test anything other than rv64i
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//initial
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// if (`XLEN == 64) begin // RV64
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// if(TESTSBP) begin
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// tests = testsBP64;
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// end else begin
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// tests = {tests64i};
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// if (`C_SUPPORTED) tests = {tests, tests64ic};
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// else tests = {tests, tests64iNOc};
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// if (`M_SUPPORTED) tests = {tests, tests64m};
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// if (`A_SUPPORTED) tests = {tests, tests64a};
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// end
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// // tests = {tests64a, tests};
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// end else begin // RV32
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// // *** add the 32 bit bp tests
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// tests = {tests32i};
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// if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
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// else tests = {tests, tests32iNOc};
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// if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
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// if (`A_SUPPORTED) tests = {tests, tests32a};
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// end
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string signame, memfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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@ -75,10 +94,10 @@ module testbench();
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wallypipelinedsoc dut(.*);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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InstrDName, InstrEName, InstrMName, InstrWName);
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instrTrackerTBPriv it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// initialize tests
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initial
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@ -97,7 +116,10 @@ module testbench();
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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reset = 1; # 22; reset = 0;
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ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
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$display("Read memfile %s", memfilename);
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reset = 1; # 42; reset = 0;
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end
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// generate clock to sequence tests
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@ -170,25 +192,43 @@ module testbench();
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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$display("Read memfile %s", memfilename);
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ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
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reset = 1; # 17; reset = 0;
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end
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end
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end
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end // always @ (negedge clk)
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// track the current function or global label
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if (DEBUG == 1) begin : functionRadix
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function_radix function_radix(.reset(reset),
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.ProgramAddrMapFile(ProgramAddrMapFile),
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.ProgramLabelMapFile(ProgramLabelMapFile));
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end
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// initialize the branch predictor
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initial begin
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
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end
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endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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module instrTrackerTB(
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module instrTrackerTBPriv(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrD,
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input logic [31:0] InstrF, InstrD,
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input logic [31:0] InstrE, InstrM,
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output logic [31:0] InstrW,
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output string InstrDName, InstrEName, InstrMName, InstrWName);
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input logic [31:0] InstrW,
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// output logic [31:0] InstrW,
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output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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// flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB fdec(InstrF, InstrFName);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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@ -247,10 +287,18 @@ module instrNameDecTB(
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else name = "ILLEGAL";
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10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
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else if (funct7 == 7'b0100000) name = "SUBW";
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else if (funct7 == 7'b0000001) name = "MULW";
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else name = "ILLEGAL";
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10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
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else if (funct7 == 7'b0000001) name = "DIVW";
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else name = "ILLEGAL";
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10'b0111011_001: name = "SLLW";
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10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
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else if (funct7 == 7'b0100000) name = "SRAW";
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else if (funct7 == 7'b0000001) name = "DIVUW";
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else name = "ILLEGAL";
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10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
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else name = "ILLEGAL";
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10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
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else name = "ILLEGAL";
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10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
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else if (funct7 == 7'b0000001) name = "MUL";
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@ -263,10 +311,10 @@ module instrNameDecTB(
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else if (funct7 == 7'b0000001) name = "MULHSU";
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else name = "ILLEGAL";
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10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
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else if (funct7 == 7'b0000001) name = "DIV";
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else if (funct7 == 7'b0000001) name = "MULHU";
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else name = "ILLEGAL";
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10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
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else if (funct7 == 7'b0000001) name = "MUL";
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else if (funct7 == 7'b0000001) name = "DIV";
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else name = "ILLEGAL";
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10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
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else if (funct7 == 7'b0000001) name = "DIVU";
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@ -299,6 +347,30 @@ module instrNameDecTB(
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10'b1110011_101: name = "CSRRWI";
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10'b1110011_110: name = "CSRRSI";
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10'b1110011_111: name = "CSRRCI";
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10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W";
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else if (funct7[6:2] == 5'b00011) name = "SC.W";
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else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
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else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
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else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
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else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
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else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
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else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
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else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
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else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
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else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
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else name = "ILLEGAL";
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10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D";
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else if (funct7[6:2] == 5'b00011) name = "SC.D";
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else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
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else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
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else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
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else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
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else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
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else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
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else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
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else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
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else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
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else name = "ILLEGAL";
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10'b0001111_???: name = "FENCE";
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default: name = "ILLEGAL";
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endcase
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@ -1,8 +1,8 @@
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#!/usr/bin/python3
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##################################
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# testgen-CAUSE.py
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# testgen-ADD-SUB.py
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#
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# dottolia@hmc.edu 16 Mar 2021
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# ushakya@hmc.edu & dottolia@hmc.edu 14 Feb 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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##################################
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@ -13,7 +13,6 @@
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from datetime import datetime
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from random import randint
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from random import seed
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from enum import Enum
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from random import getrandbits
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##################################
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@ -30,160 +29,85 @@ from random import getrandbits
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# # exit(1)
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def randRegs():
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reg1 = randint(1,30)
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reg2 = randint(1,30)
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reg3 = randint(1,30)
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reg1 = randint(1,31)
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reg2 = randint(1,31)
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reg3 = randint(1,31)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return reg1, reg2, reg3
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def writeVectors(storecmd):
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def writeVector(a, b, storecmd):
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global testnum
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#expected = computeExpected(a, b, test)
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#expected = expected % 2**xlen # drop carry if necessary
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#if (expected < 0): # take twos complement
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# expected = 2**xlen + expected
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csr = "mscratch"
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reg1, reg2, reg3 = randRegs()
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lines = "\n# Testcase " + str(testnum) + ": " + csr + "\n"
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lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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lines = lines + "li x" + str(reg2) + ", MASK_XLEN(0)\n"
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# t5 gets written with mtvec?
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# Page 6 of unpriviledged spec
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# For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects
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# lines = f"""
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expected = a
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# li x{reg1}, 0
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# csrwi mtvec, 80002000
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# .data 00000000
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# j _done{testnum}
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if test == "csrrw":
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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# _trap{testnum}:
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# csrrs x{reg1}, mcause, x0
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# ecall
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elif test == "csrrs": # at some point, try writing a non-zero value first
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lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0
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# _done{testnum}:
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# add x0, x0, x0
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# """
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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elif test == "csrrc": # at some point, try writing a non-one value first
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allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF"
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#lines =
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lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n"
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lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones
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lines += "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF
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elif test == "csrrwi":
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a = a & 0x1F # imm is only 5 bits
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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expected = a
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elif test == "csrrsi": # at some point, try writing a non-zero value first
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a = a & 0x1F
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lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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expected = a
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elif test == "csrrci": # at some point, try writing a non-one value first
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a = a & 0x1F
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allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF"
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||||
|
||||
lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n"
|
||||
lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones
|
||||
|
||||
lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
|
||||
lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
|
||||
|
||||
expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
|
||||
# https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html
|
||||
|
||||
lines = f"""
|
||||
j _setup
|
||||
csrrs x31, mcause, x0
|
||||
csrrs x30, mepc, x0
|
||||
addi x30, x30, 0x100
|
||||
csrrw x0, mepc, x30
|
||||
mret
|
||||
|
||||
_setup:
|
||||
li x2, 0x80000004
|
||||
csrrw x0, mtvec, x2
|
||||
|
||||
"""
|
||||
lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n"
|
||||
lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
|
||||
f.write(lines)
|
||||
|
||||
# # User Software Interrupt
|
||||
# write(f"""
|
||||
# li x3, 0x8000000
|
||||
# {storecmd} x2, 0(x3)
|
||||
# """, storecmd, True, 0, "u")
|
||||
|
||||
# # A supervisor-level software interrupt is triggered on the current hart by writing 1 to its supervisor software interrupt-pending (SSIP) bit in the sip register.
|
||||
# # page 58 of priv spec
|
||||
# # Supervisor Software Interrupt
|
||||
# write(f"""
|
||||
# li x3, 0x8000000
|
||||
# {storecmd} x2, 0(x3)
|
||||
# """, storecmd, True, 0, "s")
|
||||
|
||||
# # Machine Software Interrupt
|
||||
# write(f"""
|
||||
# li x3, 0x8000000
|
||||
# {storecmd} x2, 0(x3)
|
||||
# """, storecmd, True, 3)
|
||||
|
||||
# User Timer Interrupt
|
||||
#write(f"""
|
||||
# lw x2, mtimecmp
|
||||
# {storecmd} x2, mtimecmp
|
||||
#""", storecmd, True, 4, "u")
|
||||
|
||||
# # Supervisor Timer Interrupt
|
||||
#write(f"""
|
||||
# lw x2, mtimecmp
|
||||
# {storecmd} x2, mtimecmp
|
||||
#""", storecmd, True, 5, "s")
|
||||
|
||||
# Machine Timer Interrupt
|
||||
#write(f"""
|
||||
# lw x2, mtimecmp
|
||||
# {storecmd} x2, mtimecmp
|
||||
#""", storecmd, True, 6)
|
||||
|
||||
# User external interrupt True, 8
|
||||
# Supervisor external interrupt True, 9
|
||||
|
||||
# Instr Addr Misalign
|
||||
write(f"""
|
||||
li x2, 0x00000000
|
||||
lw x3, 11(x2)
|
||||
""", storecmd, False, 0)
|
||||
|
||||
# Instr Access Fault False, 1
|
||||
# Not possible in machine mode, because we can access all memory
|
||||
|
||||
# Illegal Instruction
|
||||
# . fill 1, 2, 0 outputs all 0s
|
||||
write(f"""
|
||||
.fill 1, 2, 0
|
||||
""", storecmd, False, 2)
|
||||
|
||||
# Breakpoint
|
||||
write(f"""
|
||||
ebreak
|
||||
""", storecmd, False, 3)
|
||||
|
||||
# Load Addr Misalign
|
||||
write(f"""
|
||||
li x2, 0x00000000
|
||||
lw x3, 11(x2)
|
||||
""", storecmd, False, 4)
|
||||
|
||||
# Load Access Fault False, 5
|
||||
# Not possible in machine mode, because we can access all memory
|
||||
|
||||
|
||||
# Store/AMO address misaligned
|
||||
write(f"""
|
||||
li x2, 0x00000000
|
||||
{storecmd} x3, 11(x2)
|
||||
""", storecmd, False, 6)
|
||||
|
||||
# Store/AMO access fault False, 7
|
||||
# Not possible in machine mode, because we can access all memory
|
||||
|
||||
# Environment call from U-mode
|
||||
# Environment call from S-mode
|
||||
|
||||
def write(lines, storecmd, interrupt, code, mode = "m"):
|
||||
global testnum
|
||||
|
||||
# generate expected interrupt code
|
||||
expected = (0 if not interrupt else (2**31 if xlen == 32 else 2**63)) + code
|
||||
|
||||
lines = f"""
|
||||
# Testcase {testnum}
|
||||
li x31, 0
|
||||
{lines}
|
||||
|
||||
{storecmd} x31, {str(wordsize*testnum)}(x6)
|
||||
# RVTEST_IO_ASSERT_GPR_EQ(x0, 0, {formatstr.format(expected)})
|
||||
"""
|
||||
|
||||
#if mode == "s":
|
||||
# go to supervisor mode
|
||||
#elif mode == "u":
|
||||
# go to user mode
|
||||
|
||||
f.write(lines)
|
||||
|
||||
if (xlen == 32):
|
||||
line = formatrefstr.format(expected)+"\n"
|
||||
else:
|
||||
@ -195,38 +119,15 @@ def write(lines, storecmd, interrupt, code, mode = "m"):
|
||||
# main body
|
||||
##################################
|
||||
|
||||
# name: (interrupt?, code)
|
||||
# tests = {
|
||||
# 'User software interrupt': (1, '0'),
|
||||
# 'Supervisor software interrupt': (1, '1'),
|
||||
# 'Machine software interrupt': (1, '3'),
|
||||
# 'User timer interrupt': (1, '4'),
|
||||
# 'Supervisor timer interrupt': (1, '5'),
|
||||
# 'Machine timer interrupt': (1, '7'),
|
||||
# 'User external interrupt': (1, '8'),
|
||||
# 'Supervisor external interrupt': (1, '9'),
|
||||
# 'Machine external interrupt': (1, '11'),
|
||||
# 'Instruction address misaligned': (0, '0'),
|
||||
# 'Instruction access fault': (0, '1'),
|
||||
# 'Illegal instruction': (0, '2'),
|
||||
# 'Breakpoint': (0, '3'),
|
||||
# 'Load address misaligned': (0, '4'),
|
||||
# 'Load access fault': (0, '5'),
|
||||
# 'Store/AMO address misaligned': (0, '6'),
|
||||
# 'Store/AMO access fault': (0, '7'),
|
||||
# 'Environment call from U-mode': (0, '8'),
|
||||
# 'Environment call from S-mode': (0, '9'),
|
||||
# 'Environment call from M-mode': (0, '11'),
|
||||
# 'Instruction page fault': (0, '12'),
|
||||
# 'Load page fault': (0, '13'),
|
||||
# 'Store/AMO page fault': (0, '15'),
|
||||
# }
|
||||
author = "Domenico Ottolia (dottolia@hmc.edu)"
|
||||
# change these to suite your tests
|
||||
# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
|
||||
tests = ["csrrw"]
|
||||
author = "ushakya@hmc.edu & dottolia@hmc.edu"
|
||||
xlens = [32, 64]
|
||||
numrand = 60;
|
||||
|
||||
# setup
|
||||
seed(0xC395DDEB9173AD42) # make tests reproducible
|
||||
seed(0xC365DDEB9173AB42) # make tests reproducible
|
||||
|
||||
# generate files for each test
|
||||
for xlen in xlens:
|
||||
@ -239,41 +140,51 @@ for xlen in xlens:
|
||||
else:
|
||||
storecmd = "sd"
|
||||
wordsize = 8
|
||||
for test in tests:
|
||||
corners = [
|
||||
0, 1, 2, 0x1E, 0x1F, 0xFF,
|
||||
0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
|
||||
2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
|
||||
]
|
||||
imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
|
||||
basename = "WALLY-CAUSE"
|
||||
fname = imperaspath + "src/" + basename + ".S"
|
||||
refname = imperaspath + "references/" + basename + ".reference_output"
|
||||
testnum = 0
|
||||
|
||||
imperaspath = f"""../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/"""
|
||||
basename = "WALLY-CAUSE"
|
||||
fname = imperaspath + "src/" + basename + ".S"
|
||||
refname = imperaspath + "references/" + basename + ".reference_output"
|
||||
testnum = 0
|
||||
# print custom header part
|
||||
f = open(fname, "w")
|
||||
r = open(refname, "w")
|
||||
line = "///////////////////////////////////////////\n"
|
||||
f.write(line)
|
||||
lines="// "+fname+ "\n// " + author + "\n"
|
||||
f.write(lines)
|
||||
line ="// Created " + str(datetime.now())
|
||||
f.write(line)
|
||||
|
||||
# print custom header part
|
||||
f = open(fname, "w")
|
||||
r = open(refname, "w")
|
||||
line = "///////////////////////////////////////////\n"
|
||||
f.write(line)
|
||||
lines="// "+fname+ "\n// " + author + "\n"
|
||||
f.write(lines)
|
||||
line ="// Created " + str(datetime.now())
|
||||
f.write(line)
|
||||
# insert generic header
|
||||
h = open("../testgen_header.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# insert generic header
|
||||
# h = open("../testgen_header.S", "r")
|
||||
# for line in h:
|
||||
# f.write(line)
|
||||
|
||||
# print directed and random test vectors
|
||||
writeVectors(storecmd)
|
||||
# print directed and random test vectors
|
||||
for a in corners:
|
||||
for b in corners:
|
||||
writeVector(a, b, storecmd)
|
||||
for i in range(0,numrand):
|
||||
a = getrandbits(xlen)
|
||||
b = getrandbits(xlen)
|
||||
writeVector(a, b, storecmd)
|
||||
|
||||
|
||||
# print footer
|
||||
# h = open("../testgen_footer.S", "r")
|
||||
# for line in h:
|
||||
# f.write(line)
|
||||
|
||||
# Finish
|
||||
# lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
|
||||
# lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
|
||||
# f.write(lines)
|
||||
f.close()
|
||||
r.close()
|
||||
# print footer
|
||||
h = open("../testgen_footer.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# Finish
|
||||
lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
|
||||
lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
|
||||
f.write(lines)
|
||||
f.close()
|
||||
r.close()
|
||||
Loading…
Reference in New Issue
Block a user