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Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh

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This commit is contained in:
David Harris 2021-01-23 10:48:12 -05:00
parent 556e815c4b
commit b77ef491fc
35 changed files with 411 additions and 398 deletions

2
wally-pipelined/src/alu.sv
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@ -23,7 +23,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module alu #(parameter WIDTH=32) (
input logic [WIDTH-1:0] a, b,

12
wally-pipelined/src/clint.sv
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@ -24,14 +24,14 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module clint #(parameter XLEN=32) (
module clint (
input logic clk, reset,
input logic [1:0] MemRWclintM,
input logic [15:0] AdrM,
input logic [XLEN-1:0] MaskedWriteDataM,
output logic [XLEN-1:0] RdCLINTM,
input logic [`XLEN-1:0] MaskedWriteDataM,
output logic [`XLEN-1:0] RdCLINTM,
output logic TimerIntM, SwIntM);
logic [63:0] MTIMECMP, MTIME;
@ -45,7 +45,7 @@ module clint #(parameter XLEN=32) (
// word aligned reads
generate
if (XLEN==64)
if (`XLEN==64)
assign #2 entry = {AdrM[15:3], 3'b000};
else
assign #2 entry = {AdrM[15:2], 2'b00};
@ -54,7 +54,7 @@ module clint #(parameter XLEN=32) (
// register access
generate
if (XLEN==64) begin
if (`XLEN==64) begin
always_comb begin
case(entry)
16'h0000: RdCLINTM = {63'b0, MSIP};

2
wally-pipelined/src/controller.sv
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@ -23,7 +23,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module controller(

99
wally-pipelined/src/csr.sv
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@ -24,43 +24,43 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module csr #(parameter XLEN = 64, MISA = 0, ZCSR = 1, ZCOUNTERS = 1) (
module csr (
input logic clk, reset,
input logic [31:0] InstrM,
input logic [XLEN-1:0] PCM, SrcAM,
input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrValidW, FloatRegWriteW, LoadStallD,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic [XLEN-1:0] CauseM, NextFaultMtvalM,
input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STATUS_TSR,
output logic [XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
output logic [XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW,
output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW,
output logic [11:0] MIP_REGW, MIE_REGW,
output logic STATUS_MIE, STATUS_SIE,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
output logic [XLEN-1:0] CSRReadValM,
output logic [`XLEN-1:0] CSRReadValM,
output logic IllegalCSRAccessM
);
logic [XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM;
logic [XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM;
logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM;
logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM;
logic [XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW;
logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW;
logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM;
logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM;
logic [XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
logic [XLEN-1:0] zero = 0;
logic [XLEN-1:0] resetExceptionVector = {{(XLEN-32){1'b0}}, 32'h80000000}; // initial exception vector at reset
logic [`XLEN-1:0] zero = 0;
logic [`XLEN-1:0] resetExceptionVector = {{(`XLEN-32){1'b0}}, 32'h80000000}; // initial exception vector at reset
logic [11:0] CSRAdrM;
logic [11:0] SIP_REGW, SIE_REGW;
@ -72,7 +72,7 @@ module csr #(parameter XLEN = 64, MISA = 0, ZCSR = 1, ZCOUNTERS = 1) (
// modify CSRs
always_comb begin
// Choose either rs1 or uimm[4:0] as source
CSRSrcM = InstrM[14] ? {{(XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
// Compute AND/OR modification
CSRRWM = CSRSrcM;
CSRRSM = CSRReadValM | CSRSrcM;
@ -88,75 +88,20 @@ module csr #(parameter XLEN = 64, MISA = 0, ZCSR = 1, ZCOUNTERS = 1) (
// write CSRs
assign CSRAdrM = InstrM[31:20];
assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[XLEN-1:1], 1'b0} : {UnalignedNextEPCM[XLEN-1:2], 2'b00}; // 3.1.15 alignment
assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
assign NextMtvalM = TrapM? NextFaultMtvalM : CSRWriteValM;
assign CSRMWriteM = CSRWriteM && (PrivilegeModeW == `M_MODE);
assign CSRSWriteM = CSRWriteM && (PrivilegeModeW[0]);
assign CSRUWriteM = CSRWriteM;
csri #(XLEN, MISA) csri(.*);
csrsr #(XLEN, MISA) csrsr(.*);
csrc #(XLEN, ZCOUNTERS) counters(.*);
csrm #(XLEN, MISA) csrm(.*); // Machine Mode CSRs
csrs #(XLEN, MISA) csrs(.*);
csrn #(XLEN, MISA) csrn(.CSRNWriteM(CSRUWriteM), .*); // User Mode Exception Registers
csru #(XLEN, MISA) csru(.*); // Floating Point Flags are part of User MOde
/*
csri #(XLEN, MISA) csri(
clk, reset, CSRMWriteM, CSRSWriteM, CSRAdrM, ExtIntM, TimerIntM, SwIntM,
MIDELEG_REGW, MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, CSRWriteValM);
csrsr #(XLEN, MISA) csrsr(
clk, reset,
WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM, TrapM, FloatRegWriteW,
NextPrivilegeModeM, PrivilegeModeW,
mretM, sretM, uretM,
CSRWriteValM,
MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW,
STATUS_MPP, STATUS_SPP, STATUS_TSR, STATUS_MIE, STATUS_SIE);
csrc #(XLEN, ZCOUNTERS) counters(
clk, reset,
InstrValidW, LoadStallD, CSRMWriteM, CSRAdrM, PrivilegeModeW, CSRWriteValM,
MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
CSRCReadValM, IllegalCSRCAccessM);
// Machine Mode CSRs
csrm #(XLEN, MISA) csrm(
clk, reset,
CSRMWriteM, MTrapM, CSRAdrM,
resetExceptionVector,
NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
CSRWriteValM, CSRMReadValM, MEPC_REGW, MTVEC_REGW, MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
MEDELEG_REGW, MIDELEG_REGW, MIP_REGW, MIE_REGW, WriteMIPM, WriteMIEM, WriteMSTATUSM, IllegalCSRMAccessM
);
csrs #(XLEN, MISA) csrs(
clk, reset,
CSRSWriteM, STrapM, CSRAdrM,
resetExceptionVector,
NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
CSRWriteValM, CSRSReadValM, SEPC_REGW, STVEC_REGW, SCOUNTEREN_REGW,
SEDELEG_REGW, SIDELEG_REGW, SIP_REGW, SIE_REGW, WriteSIPM, WriteSIEM, WriteSSTATUSM, IllegalCSRSAccessM
);
csrn #(XLEN, MISA) csrn( // User Mode Exception Registers
clk, reset,
CSRUWriteM, UTrapM, CSRAdrM,
resetExceptionVector,
NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW,
CSRWriteValM, CSRNReadValM, UEPC_REGW, UTVEC_REGW,
UIP_REGW, UIE_REGW, WriteUIPM, WriteUIEM, WriteUSTATUSM, IllegalCSRNAccessM
);
csru #(XLEN, MISA) csru( // Floating Point Flags are part of User MOde
clk, reset, CSRUWriteM, CSRAdrM,
CSRWriteValM, CSRUReadValM, SetFflagsM, FRM_REGW, IllegalCSRUAccessM
);
*/
csri csri(.*);
csrsr csrsr(.*);
csrc counters(.*);
csrm csrm(.*); // Machine Mode CSRs
csrs csrs(.*);
csrn csrn(.CSRNWriteM(CSRUWriteM), .*); // User Mode Exception Registers
csru csru(.*); // Floating Point Flags are part of User MOde
// merge CSR Reads
assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM;

32
wally-pipelined/src/csrc.sv
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@ -24,9 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module csrc #(parameter XLEN=64, ZCOUNTERS = 1,
module csrc #(parameter
MCYCLE = 12'hB00,
// MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive
// MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT
@ -67,9 +67,9 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1,
input logic InstrValidW, LoadStallD, CSRMWriteM,
input logic [11:0] CSRAdrM,
input logic [1:0] PrivilegeModeW,
input logic [XLEN-1:0] CSRWriteValM,
input logic [`XLEN-1:0] CSRWriteValM,
input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
output logic [XLEN-1:0] CSRCReadValM,
output logic [`XLEN-1:0] CSRCReadValM,
output logic IllegalCSRCAccessM
);
@ -80,9 +80,9 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1,
logic [63:0] HPMCOUNTER3_REGW, HPMCOUNTER4_REGW; // add more performance counters here if desired
logic [63:0] CYCLEPlusM, TIMEPlusM, INSTRETPlusM;
logic [63:0] HPMCOUNTER3PlusM, HPMCOUNTER4PlusM;
// logic [XLEN-1:0] NextTIMEM;
logic [XLEN-1:0] NextCYCLEM, NextINSTRETM;
logic [XLEN-1:0] NextHPMCOUNTER3M, NextHPMCOUNTER4M;
// logic [`XLEN-1:0] NextTIMEM;
logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
logic [`XLEN-1:0] NextHPMCOUNTER3M, NextHPMCOUNTER4M;
logic WriteTIMEM, WriteTIMECMPM, WriteCYCLEM, WriteINSTRETM;
logic WriteHPMCOUNTER3M, WriteHPMCOUNTER4M;
logic [4:0] CounterNumM;
@ -101,15 +101,15 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1,
assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~MCOUNTINHIBIT_REGW[2]};
assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls
assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[XLEN-1:0];
// assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[XLEN-1:0];
assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[XLEN-1:0];
assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[XLEN-1:0];
assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[XLEN-1:0];
assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0];
// assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0];
assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[`XLEN-1:0];
assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[`XLEN-1:0];
assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[`XLEN-1:0];
// Write / update counters
// Only the Machine mode versions of the counter CSRs are writable
if (XLEN==64) begin// 64-bit counters
if (`XLEN==64) begin// 64-bit counters
// flopr #(64) TIMEreg(clk, reset, WriteTIMEM ? CSRWriteValM : TIME_REGW + 1, TIME_REGW); // may count off a different clock***
// flopenr #(64) TIMECMPreg(clk, reset, WriteTIMECMPM, CSRWriteValM, TIMECMP_REGW);
flopr #(64) CYCLEreg(clk, reset, NextCYCLEM, CYCLE_REGW);
@ -119,8 +119,8 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1,
end else begin // 32-bit low and high counters
logic WriteTIMEHM, WriteTIMECMPHM, WriteCYCLEHM, WriteINSTRETHM;
logic WriteHPMCOUNTER3HM, WriteHPMCOUNTER4HM;
logic [XLEN-1:0] NextCYCLEHM, NextTIMEHM, NextINSTRETHM;
logic [XLEN-1:0] NextHPMCOUNTER3HM, NextHPMCOUNTER4HM;
logic [`XLEN-1:0] NextCYCLEHM, NextTIMEHM, NextINSTRETHM;
logic [`XLEN-1:0] NextHPMCOUNTER3HM, NextHPMCOUNTER4HM;
// Write Enables
// assign WriteTIMEHM = CSRMWriteM && (CSRAdrM == MTIMEH);
@ -160,7 +160,7 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1,
// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
if (XLEN==64) // 64-bit counter reads
if (`XLEN==64) // 64-bit counter reads
always_comb
if (PrivilegeModeW == `M_MODE ||
MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin

10
wally-pipelined/src/csri.sv
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@ -24,9 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module csri #(parameter XLEN=64, MISA=0,
module csri #(parameter
// Machine CSRs
MIE = 12'h304,
MIP = 12'h344,
@ -36,15 +36,15 @@ module csri #(parameter XLEN=64, MISA=0,
input logic CSRMWriteM, CSRSWriteM,
input logic [11:0] CSRAdrM,
input logic ExtIntM, TimerIntM, SwIntM,
input logic [XLEN-1:0] MIDELEG_REGW,
input logic [`XLEN-1:0] MIDELEG_REGW,
output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
input logic [XLEN-1:0] CSRWriteValM
input logic [`XLEN-1:0] CSRWriteValM
);
logic [11:0] IntInM, IP_REGW, IE_REGW;
logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK;
logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
logic [XLEN-1:0] zero = 0;
logic [`XLEN-1:0] zero = 0;
// Determine which interrupts need to be set
// assumes no N-mode user interrupts

53
wally-pipelined/src/csrm.sv
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@ -24,9 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module csrm #(parameter XLEN=64, MISA=0,
module csrm #(parameter
// Machine CSRs
MVENDORID = 12'hF11,
MARCHID = 12'hF12,
@ -64,30 +64,31 @@ module csrm #(parameter XLEN=64, MISA=0,
input logic clk, reset,
input logic CSRMWriteM, MTrapM,
input logic [11:0] CSRAdrM,
input logic [XLEN-1:0] resetExceptionVector,
input logic [XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
input logic [XLEN-1:0] CSRWriteValM,
output logic [XLEN-1:0] CSRMReadValM, MEPC_REGW, MTVEC_REGW,
input logic [`XLEN-1:0] resetExceptionVector,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRMReadValM, MEPC_REGW, MTVEC_REGW,
output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
output logic [XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
input logic [11:0] MIP_REGW, MIE_REGW,
output logic WriteMIPM, WriteMIEM,
output logic WriteMSTATUSM,
output logic IllegalCSRMAccessM
);
logic [XLEN-1:0] MISA_REGW;
logic [XLEN-1:0] MSCRATCH_REGW,MCAUSE_REGW, MTVAL_REGW;
logic [XLEN-1:0] zero = 0;
logic [`XLEN-1:0] MISA_REGW;
logic [`XLEN-1:0] MSCRATCH_REGW,MCAUSE_REGW, MTVAL_REGW;
logic [`XLEN-1:0] zero = 0;
logic [31:0] allones = {32{1'b1}};
logic [XLEN-1:0] MEDELEG_MASK = ~(zero | 1'b1 << 11); // medeleg[11] hardwired to zero per Privileged Spec 3.1.8
logic [XLEN-1:0] MIDELEG_MASK = {{(XLEN-12){1'b0}}, 12'h222}; // only allow delegating interrupts to supervisor mode
logic [`XLEN-1:0] MEDELEG_MASK = ~(zero | 1'b1 << 11); // medeleg[11] hardwired to zero per Privileged Spec 3.1.8
logic [`XLEN-1:0] MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}; // only allow delegating interrupts to supervisor mode
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
logic [25:0] MISAbits = `MISA;
// MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally
assign MISA_REGW = {(XLEN == 32 ? 2'b01 : 2'b10), {(XLEN-28){1'b0}}, MISA[25:0]};
assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISAbits};
// Write machine Mode CSRs
assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS);
@ -104,23 +105,23 @@ module csrm #(parameter XLEN=64, MISA=0,
assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT);
// CSRs
flopenl #(XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, resetExceptionVector, MTVEC_REGW);
flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, resetExceptionVector, MTVEC_REGW);
generate
if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist
flopenl #(XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, zero, MEDELEG_REGW);
flopenl #(XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK, zero, MIDELEG_REGW);
flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, zero, MEDELEG_REGW);
flopenl #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK, zero, MIDELEG_REGW);
end else begin
assign MEDELEG_REGW = 0;
assign MIDELEG_REGW = 0;
end
endgenerate
// flopenl #(XLEN) MIPreg(clk, reset, WriteMIPM, CSRWriteValM, zero, MIP_REGW);
// flopenl #(XLEN) MIEreg(clk, reset, WriteMIEM, CSRWriteValM, zero, MIE_REGW);
flopenr #(XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
flopenr #(XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW);
flopenl #(XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, zero, MCAUSE_REGW);
flopenr #(XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
// flopenl #(`XLEN) MIPreg(clk, reset, WriteMIPM, CSRWriteValM, zero, MIP_REGW);
// flopenl #(`XLEN) MIEreg(clk, reset, WriteMIEM, CSRWriteValM, zero, MIE_REGW);
flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW);
flopenl #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, zero, MCAUSE_REGW);
flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], allones, MCOUNTEREN_REGW);
flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], allones, MCOUNTINHIBIT_REGW);
@ -139,14 +140,14 @@ module csrm #(parameter XLEN=64, MISA=0,
MTVEC: CSRMReadValM = MTVEC_REGW;
MEDELEG: CSRMReadValM = MEDELEG_REGW;
MIDELEG: CSRMReadValM = MIDELEG_REGW;
MIP: CSRMReadValM = {{(XLEN-12){1'b0}}, MIP_REGW};
MIE: CSRMReadValM = {{(XLEN-12){1'b0}}, MIE_REGW};
MIP: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW};
MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW};
MSCRATCH: CSRMReadValM = MSCRATCH_REGW;
MEPC: CSRMReadValM = MEPC_REGW;
MCAUSE: CSRMReadValM = MCAUSE_REGW;
MTVAL: CSRMReadValM = MTVAL_REGW;
MCOUNTEREN:CSRMReadValM = {{(XLEN-32){1'b0}}, MCOUNTEREN_REGW};
MCOUNTINHIBIT:CSRMReadValM = {{(XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW};
MCOUNTINHIBIT:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
default: begin
CSRMReadValM = 0;
IllegalCSRMAccessM = 1;

36
wally-pipelined/src/csrn.sv
View File

@ -24,9 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module csrn #(parameter XLEN=64, MISA=0,
module csrn #(parameter
USTATUS =12'h000,
UIE = 12'h004,
UTVEC = 12'h005,
@ -38,17 +38,17 @@ module csrn #(parameter XLEN=64, MISA=0,
input logic clk, reset,
input logic CSRNWriteM, UTrapM,
input logic [11:0] CSRAdrM,
input logic [XLEN-1:0] resetExceptionVector,
input logic [XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW,
input logic [XLEN-1:0] CSRWriteValM,
output logic [XLEN-1:0] CSRNReadValM, UEPC_REGW, UTVEC_REGW,
input logic [`XLEN-1:0] resetExceptionVector,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRNReadValM, UEPC_REGW, UTVEC_REGW,
input logic [11:0] UIP_REGW, UIE_REGW,
output logic WriteUIPM, WriteUIEM,
output logic WriteUSTATUSM,
output logic IllegalCSRNAccessM
);
logic [XLEN-1:0] zero = 0;
logic [`XLEN-1:0] zero = 0;
// User mode CSRs below only needed when user mode traps are supported
generate
@ -56,8 +56,8 @@ module csrn #(parameter XLEN=64, MISA=0,
logic WriteUTVECM;
logic WriteUSCRATCHM, WriteUEPCM;
logic WriteUCAUSEM, WriteUTVALM;
logic [XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW, UIP_REGW, UIE_REGW;
logic [XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW;
logic [`XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW, UIP_REGW, UIE_REGW;
logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW;
// Write enables
assign WriteUSTATUSM = CSRNWriteM && (CSRAdrM == USTATUS);
@ -69,13 +69,13 @@ module csrn #(parameter XLEN=64, MISA=0,
assign WriteUTVALM = UTrapM | (CSRNWriteM && (CSRAdrM == UTVAL));
// CSRs
flopenl #(XLEN) UTVECreg(clk, reset, WriteUTVECM, CSRWriteValM, resetExceptionVector, UTVEC_REGW);
// flopenl #(XLEN) UIPreg(clk, reset, WriteUIPM, CSRWriteValM, zero, UIP_REGW);
// flopenl #(XLEN) UIEreg(clk, reset, WriteUIEM, CSRWriteValM, zero, UIE_REGW);
flopenr #(XLEN) USCRATCHreg(clk, reset, WriteUSCRATCHM, CSRWriteValM, USCRATCH_REGW);
flopenr #(XLEN) UEPCreg(clk, reset, WriteUEPCM, NextEPCM, UEPC_REGW);
flopenr #(XLEN) UCAUSEreg(clk, reset, WriteUCAUSEM, NextCauseM, UCAUSE_REGW);
flopenr #(XLEN) UTVALreg(clk, reset, WriteUTVALM, NextMtvalM, UTVAL_REGW);
flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, CSRWriteValM, resetExceptionVector, UTVEC_REGW);
// flopenl #(`XLEN) UIPreg(clk, reset, WriteUIPM, CSRWriteValM, zero, UIP_REGW);
// flopenl #(`XLEN) UIEreg(clk, reset, WriteUIEM, CSRWriteValM, zero, UIE_REGW);
flopenr #(`XLEN) USCRATCHreg(clk, reset, WriteUSCRATCHM, CSRWriteValM, USCRATCH_REGW);
flopenr #(`XLEN) UEPCreg(clk, reset, WriteUEPCM, NextEPCM, UEPC_REGW);
flopenr #(`XLEN) UCAUSEreg(clk, reset, WriteUCAUSEM, NextCauseM, UCAUSE_REGW);
flopenr #(`XLEN) UTVALreg(clk, reset, WriteUTVALM, NextMtvalM, UTVAL_REGW);
// CSR Reads
always_comb begin
@ -83,8 +83,8 @@ module csrn #(parameter XLEN=64, MISA=0,
case (CSRAdrM)
USTATUS: CSRNReadValM = USTATUS_REGW;
UTVEC: CSRNReadValM = UTVEC_REGW;
UIP: CSRNReadValM = {{(XLEN-12){1'b0}}, UIP_REGW};
UIE: CSRNReadValM = {{(XLEN-12){1'b0}}, UIE_REGW};
UIP: CSRNReadValM = {{(`XLEN-12){1'b0}}, UIP_REGW};
UIE: CSRNReadValM = {{(`XLEN-12){1'b0}}, UIE_REGW};
USCRATCH: CSRNReadValM = USCRATCH_REGW;
UEPC: CSRNReadValM = UEPC_REGW;
UCAUSE: CSRNReadValM = UCAUSE_REGW;

44
wally-pipelined/src/csrs.sv
View File

@ -24,9 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module csrs #(parameter XLEN=64, MISA=0,
module csrs #(parameter
// Supervisor CSRs
SSTATUS = 12'h100,
SEDELEG = 12'h102,
@ -43,21 +43,21 @@ module csrs #(parameter XLEN=64, MISA=0,
input logic clk, reset,
input logic CSRSWriteM, STrapM,
input logic [11:0] CSRAdrM,
input logic [XLEN-1:0] resetExceptionVector,
input logic [XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
input logic [XLEN-1:0] CSRWriteValM,
output logic [XLEN-1:0] CSRSReadValM, SEPC_REGW, STVEC_REGW,
input logic [`XLEN-1:0] resetExceptionVector,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRSReadValM, SEPC_REGW, STVEC_REGW,
output logic [31:0] SCOUNTEREN_REGW,
output logic [XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW,
output logic [`XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW,
input logic [11:0] SIP_REGW, SIE_REGW,
output logic WriteSIPM, WriteSIEM,
output logic WriteSSTATUSM,
output logic IllegalCSRSAccessM
);
logic [XLEN-1:0] zero = 0;
logic [`XLEN-1:0] zero = 0;
logic [31:0] allones = {32{1'b1}};
logic [XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8
logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8
// Supervisor mode CSRs sometimes supported
generate
@ -65,7 +65,7 @@ module csrs #(parameter XLEN=64, MISA=0,
logic WriteSTVECM, WriteSEDELEGM, WriteSIDELEGM;
logic WriteSSCRATCHM, WriteSEPCM;
logic WriteSCAUSEM, WriteSTVALM, WriteSCOUNTERENM;
logic [XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW;
logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW;
assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS);
assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC);
@ -80,17 +80,17 @@ module csrs #(parameter XLEN=64, MISA=0,
assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN);
// CSRs
flopenl #(XLEN) STVECreg(clk, reset, WriteSTVECM, CSRWriteValM, resetExceptionVector, STVEC_REGW);
// flopenl #(XLEN) SIPreg(clk, reset, WriteSIPM, CSRWriteValM, zero, SIP_REGW);
// flopenl #(XLEN) SIEreg(clk, reset, WriteSIEM, CSRWriteValM, zero, SIE_REGW);
flopenr #(XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
flopenr #(XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW);
flopenl #(XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, zero, SCAUSE_REGW);
flopenr #(XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, CSRWriteValM, resetExceptionVector, STVEC_REGW);
// flopenl #(`XLEN) SIPreg(clk, reset, WriteSIPM, CSRWriteValM, zero, SIP_REGW);
// flopenl #(`XLEN) SIEreg(clk, reset, WriteSIEM, CSRWriteValM, zero, SIE_REGW);
flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW);
flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, zero, SCAUSE_REGW);
flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW);
if (`N_SUPPORTED) begin
flopenl #(XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, zero, SEDELEG_REGW);
flopenl #(XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, zero, SIDELEG_REGW);
flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, zero, SEDELEG_REGW);
flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, zero, SIDELEG_REGW);
end else begin
assign SEDELEG_REGW = 0;
assign SIDELEG_REGW = 0;
@ -104,13 +104,13 @@ module csrs #(parameter XLEN=64, MISA=0,
STVEC: CSRSReadValM = STVEC_REGW;
SEDELEG: CSRSReadValM = SEDELEG_REGW;
SIDELEG: CSRSReadValM = SIDELEG_REGW;
SIP: CSRSReadValM = {{(XLEN-12){1'b0}}, SIP_REGW};
SIE: CSRSReadValM = {{(XLEN-12){1'b0}}, SIE_REGW};
SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIP_REGW};
SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIE_REGW};
SSCRATCH: CSRSReadValM = SSCRATCH_REGW;
SEPC: CSRSReadValM = SEPC_REGW;
SCAUSE: CSRSReadValM = SCAUSE_REGW;
STVAL: CSRSReadValM = STVAL_REGW;
SCOUNTEREN:CSRSReadValM = {{(XLEN-32){1'b0}}, SCOUNTEREN_REGW};
SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW};
default: begin
CSRSReadValM = 0;
IllegalCSRSAccessM = 1;

10
wally-pipelined/src/csrsr.sv
View File

@ -24,15 +24,15 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module csrsr #(parameter XLEN=64, MISA = 0)(
module csrsr (
input logic clk, reset,
input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM, TrapM, FloatRegWriteW,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic mretM, sretM, uretM,
input logic [XLEN-1:0] CSRWriteValM,
output logic [XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW,
output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STATUS_TSR,
output logic STATUS_MIE, STATUS_SIE
@ -47,7 +47,7 @@ module csrsr #(parameter XLEN=64, MISA = 0)(
// Lower privilege status registers are a subset of the full status register
// *** consider adding MBE, SBE, UBE fields later from 20210108 draft spec
generate
if (XLEN==64) begin// RV64
if (`XLEN==64) begin// RV64
assign MSTATUS_REGW = {STATUS_SD, 27'b0, STATUS_SXL, STATUS_UXL, 9'b0,
STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,

14
wally-pipelined/src/csru.sv
View File

@ -25,17 +25,17 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module csru #(parameter XLEN=64, MISA=0,
module csru #(parameter
FFLAGS = 12'h001,
FRM = 12'h002,
FCSR = 12'h003) (
input logic clk, reset,
input logic CSRUWriteM,
input logic [11:0] CSRAdrM,
input logic [XLEN-1:0] CSRWriteValM,
output logic [XLEN-1:0] CSRUReadValM,
input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] CSRUReadValM,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
output logic IllegalCSRUAccessM
@ -66,9 +66,9 @@ module csru #(parameter XLEN=64, MISA=0,
always_comb begin
IllegalCSRUAccessM = 0;
case (CSRAdrM)
FFLAGS: CSRUReadValM = {{(XLEN-5){1'b0}}, FFLAGS_REGW};
FRM: CSRUReadValM = {{(XLEN-3){1'b0}}, FRM_REGW};
FCSR: CSRUReadValM = {{(XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW};
FFLAGS: CSRUReadValM = {{(`XLEN-5){1'b0}}, FFLAGS_REGW};
FRM: CSRUReadValM = {{(`XLEN-3){1'b0}}, FRM_REGW};
FCSR: CSRUReadValM = {{(`XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW};
default: begin
CSRUReadValM = 0;
IllegalCSRUAccessM = 1;

108
wally-pipelined/src/datapath.sv
View File

@ -23,13 +23,13 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
module datapath (
input logic clk, reset,
// Fetch stage signals
input logic StallF,
output logic [XLEN-1:0] PCF,
output logic [`XLEN-1:0] PCF,
input logic [31:0] InstrF,
// Decode stage signals
output logic [6:0] OpD,
@ -55,8 +55,8 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
input logic TimerIntM, ExtIntM, SwIntM,
output logic InstrMisalignedFaultM,
input logic [2:0] Funct3M,
output logic [XLEN-1:0] WriteDataM, ALUResultM,
input logic [XLEN-1:0] ReadDataM,
output logic [`XLEN-1:0] WriteDataM, ALUResultM,
input logic [`XLEN-1:0] ReadDataM,
output logic [7:0] ByteMaskM,
output logic RetM, TrapM,
input logic [4:0] SetFflagsM,
@ -73,51 +73,51 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
output logic [4:0] RdE, RdM, RdW);
// Fetch stage signals
logic [XLEN-1:0] PCPlus2or4F;
logic [`XLEN-1:0] PCPlus2or4F;
// Decode stage signals
logic [31:0] InstrD;
logic [XLEN-1:0] PCD, PCPlus2or4D;
logic [XLEN-1:0] RD1D, RD2D;
logic [XLEN-1:0] ExtImmD;
logic [`XLEN-1:0] PCD, PCPlus2or4D;
logic [`XLEN-1:0] RD1D, RD2D;
logic [`XLEN-1:0] ExtImmD;
logic [31:0] InstrDecompD;
logic [4:0] RdD;
// Execute stage signals
logic [31:0] InstrE;
logic [XLEN-1:0] RD1E, RD2E;
logic [XLEN-1:0] PCE, ExtImmE;
logic [XLEN-1:0] PreSrcAE, SrcAE, SrcBE;
logic [XLEN-1:0] ALUResultE;
logic [XLEN-1:0] WriteDataE;
logic [XLEN-1:0] TargetBaseE;
logic [`XLEN-1:0] RD1E, RD2E;
logic [`XLEN-1:0] PCE, ExtImmE;
logic [`XLEN-1:0] PreSrcAE, SrcAE, SrcBE;
logic [`XLEN-1:0] ALUResultE;
logic [`XLEN-1:0] WriteDataE;
logic [`XLEN-1:0] TargetBaseE;
// Memory stage signals
logic [31:0] InstrM;
logic [XLEN-1:0] PCM;
logic [XLEN-1:0] SrcAM;
logic [XLEN-1:0] ReadDataExtM;
logic [XLEN-1:0] WriteDataFullM;
logic [XLEN-1:0] CSRReadValM;
logic [XLEN-1:0] PrivilegedNextPCM;
logic [`XLEN-1:0] PCM;
logic [`XLEN-1:0] SrcAM;
logic [`XLEN-1:0] ReadDataExtM;
logic [`XLEN-1:0] WriteDataFullM;
logic [`XLEN-1:0] CSRReadValM;
logic [`XLEN-1:0] PrivilegedNextPCM;
logic LoadMisalignedFaultM, LoadAccessFaultM;
logic StoreMisalignedFaultM, StoreAccessFaultM;
logic [XLEN-1:0] InstrMisalignedAdrM;
logic [`XLEN-1:0] InstrMisalignedAdrM;
// Writeback stage signals
logic [XLEN-1:0] ALUResultW;
logic [XLEN-1:0] ReadDataW;
logic [XLEN-1:0] PCW;
logic [XLEN-1:0] CSRValW;
logic [XLEN-1:0] ResultW;
logic [`XLEN-1:0] ALUResultW;
logic [`XLEN-1:0] ReadDataW;
logic [`XLEN-1:0] PCW;
logic [`XLEN-1:0] CSRValW;
logic [`XLEN-1:0] ResultW;
logic [31:0] nop = 32'h00000013; // instruction for NOP
// Fetch stage pipeline register and logic; also Ex stage for branches
pclogic #(XLEN, MISA) pclogic(.*);
pclogic pclogic(.*);
// Decode stage pipeline register and logic
flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrD);
flopenrc #(XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
flopenrc #(XLEN) PCPlus2or4DReg(clk, reset, FlushD, ~StallD, PCPlus2or4F, PCPlus2or4D);
flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
flopenrc #(`XLEN) PCPlus2or4DReg(clk, reset, FlushD, ~StallD, PCPlus2or4F, PCPlus2or4D);
instrDecompress #(XLEN, MISA) decomp(.*);
instrDecompress decomp(.*);
assign OpD = InstrDecompD[6:0];
assign Funct3D = InstrDecompD[14:12];
assign Funct7b5D = InstrDecompD[30];
@ -125,45 +125,45 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
assign Rs2D = InstrDecompD[24:20];
assign RdD = InstrDecompD[11:7];
regfile #(XLEN) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D);
extend #(XLEN) ext(.InstrDecompD(InstrDecompD[31:7]), .*);
regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D);
extend ext(.InstrDecompD(InstrDecompD[31:7]), .*);
// Execute stage pipeline register and logic
floprc #(XLEN) RD1EReg(clk, reset, FlushE, RD1D, RD1E);
floprc #(XLEN) RD2EReg(clk, reset, FlushE, RD2D, RD2E);
floprc #(XLEN) PCEReg(clk, reset, FlushE, PCD, PCE);
floprc #(XLEN) ExtImmEReg(clk, reset, FlushE, ExtImmD, ExtImmE);
floprc #(`XLEN) RD1EReg(clk, reset, FlushE, RD1D, RD1E);
floprc #(`XLEN) RD2EReg(clk, reset, FlushE, RD2D, RD2E);
floprc #(`XLEN) PCEReg(clk, reset, FlushE, PCD, PCE);
floprc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ExtImmD, ExtImmE);
flopr #(32) InstrEReg(clk, reset, FlushE ? nop : InstrDecompD, InstrE);
floprc #(5) Rs1EReg(clk, reset, FlushE, Rs1D, Rs1E);
floprc #(5) Rs2EReg(clk, reset, FlushE, Rs2D, Rs2E);
floprc #(5) RdEReg(clk, reset, FlushE, RdD, RdE);
mux3 #(XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE);
mux3 #(XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE);
mux2 #(XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE);
mux2 #(XLEN) srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE);
alu #(XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUResultE, FlagsE);
mux2 #(XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE);
mux3 #(`XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE);
mux3 #(`XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE);
mux2 #(`XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE);
mux2 #(`XLEN) srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE);
alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUResultE, FlagsE);
mux2 #(`XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE);
// Memory stage pipeline register
floprc #(XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM);
floprc #(XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM);
floprc #(XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataFullM);
floprc #(XLEN) PCMReg(clk, reset, FlushM, PCE, PCM);
floprc #(`XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM);
floprc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM);
floprc #(`XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataFullM);
floprc #(`XLEN) PCMReg(clk, reset, FlushM, PCE, PCM);
flopr #(32) InstrMReg(clk, reset, FlushM ? nop : InstrE, InstrM);
floprc #(5) RdMEg(clk, reset, FlushM, RdE, RdM);
memdp #(XLEN) memdp(.AdrM(ALUResultM), .*);
memdp memdp(.AdrM(ALUResultM), .*);
// Priveleged block operates in M and W stages, handling CSRs and exceptions
privileged #(XLEN, MISA, ZCSR, ZCOUNTERS) priv(.IllegalInstrFaultInM(IllegalInstrFaultM), .*);
privileged priv(.IllegalInstrFaultInM(IllegalInstrFaultM), .*);
// Writeback stage pipeline register and logic
floprc #(XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
floprc #(XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataExtM, ReadDataW);
floprc #(XLEN) PCWReg(clk, reset, FlushW, PCM, PCW);
floprc #(XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRValW);
floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataExtM, ReadDataW);
floprc #(`XLEN) PCWReg(clk, reset, FlushW, PCM, PCW);
floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRValW);
floprc #(5) RdWEg(clk, reset, FlushW, RdM, RdW);
mux4 #(XLEN) resultmux(ALUResultW, ReadDataW, PCW, CSRValW, ResultSrcW, ResultW);
mux4 #(`XLEN) resultmux(ALUResultW, ReadDataW, PCW, CSRValW, ResultSrcW, ResultW);
endmodule

36
wally-pipelined/src/dmem.sv
View File

@ -23,16 +23,16 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
// *** need idiom to map onto cache RAM with byte writes
// *** and use memread signal to reduce power when reads aren't needed
module dmem #(parameter XLEN=32) (
module dmem (
input logic clk, reset,
input logic [1:0] MemRWM,
input logic [7:0] ByteMaskM,
input logic [XLEN-1:0] AdrM, WriteDataM,
output logic [XLEN-1:0] ReadDataM,
input logic [`XLEN-1:0] AdrM, WriteDataM,
output logic [`XLEN-1:0] ReadDataM,
output logic DataAccessFaultM,
output logic TimerIntM, SwIntM,
input logic [31:0] GPIOPinsIn,
@ -40,47 +40,47 @@ module dmem #(parameter XLEN=32) (
input logic UARTSin,
output logic UARTSout);
logic [XLEN-1:0] MaskedWriteDataM;
logic [XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM, RdUARTM;
logic [`XLEN-1:0] MaskedWriteDataM;
logic [`XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM, RdUARTM;
logic TimEnM, CLINTEnM, GPIOEnM, UARTEnM;
logic [1:0] MemRWdtimM, MemRWclintM, MemRWgpioM;
logic UARTIntr;// *** will need to tie INTR to an interrupt handler
// Address decoding
generate
if (XLEN == 64)
assign TimEnM = ~(|AdrM[XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x000...80000000 - 0x000...8007FFFF
if (`XLEN == 64)
assign TimEnM = ~(|AdrM[`XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x000...80000000 - 0x000...8007FFFF
else
assign TimEnM = AdrM[31] & ~(|AdrM[30:19]); // 0x80000000 - 0x8007FFFF
endgenerate
assign CLINTEnM = ~(|AdrM[XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF
assign CLINTEnM = ~(|AdrM[`XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF
assign GPIOEnM = (AdrM[31:8] == 24'h10012); // 0x10012000-0x100120FF
assign UARTEnM = ~(|AdrM[XLEN-1:29]) & AdrM[28] & ~(|AdrM[27:3]); // 0x10000000-0x10000007
assign UARTEnM = ~(|AdrM[`XLEN-1:29]) & AdrM[28] & ~(|AdrM[27:3]); // 0x10000000-0x10000007
assign MemRWdtimM = MemRWM & {2{TimEnM}};
assign MemRWclintM = MemRWM & {2{CLINTEnM}};
assign MemRWgpioM = MemRWM & {2{GPIOEnM}};
// tightly integrated memory
dtim #(XLEN) dtim(.AdrM(AdrM[18:0]), .*);
dtim dtim(.AdrM(AdrM[18:0]), .*);
// memory-mapped I/O peripherals
clint #(XLEN) clint(.AdrM(AdrM[15:0]), .*);
gpio #(XLEN) gpio(.AdrM(AdrM[7:0]), .*); // *** may want to add GPIO interrupts
uart #(XLEN) uart(.TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
.DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1),
.RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
clint clint(.AdrM(AdrM[15:0]), .*);
gpio gpio(.AdrM(AdrM[7:0]), .*); // *** may want to add GPIO interrupts
uart uart(.TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
.DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1),
.RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
// *** add cache and interface to external memory & other peripherals
// merge reads
assign ReadDataM = ({XLEN{TimEnM}} & RdTimM) | ({XLEN{CLINTEnM}} & RdCLINTM) | ({XLEN{GPIOEnM}} & RdGPIOM);
assign ReadDataM = ({`XLEN{TimEnM}} & RdTimM) | ({`XLEN{CLINTEnM}} & RdCLINTM) | ({`XLEN{GPIOEnM}} & RdGPIOM);
assign DataAccessFaultM = ~(|TimEnM | CLINTEnM | GPIOEnM);
// byte masking
// write each byte based on the byte mask
generate
if (XLEN==64) begin
if (`XLEN==64) begin
always_comb begin
MaskedWriteDataM=ReadDataM;
if (ByteMaskM[0]) MaskedWriteDataM[7:0] = WriteDataM[7:0];

16
wally-pipelined/src/dtim.sv
View File

@ -23,18 +23,18 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module dtim #(parameter XLEN=32) (
module dtim (
input logic clk,
input logic [1:0] MemRWdtimM,
input logic [7:0] ByteMaskM,
input logic [18:0] AdrM,
input logic [XLEN-1:0] WriteDataM,
output logic [XLEN-1:0] RdTimM);
input logic [`XLEN-1:0] WriteDataM,
output logic [`XLEN-1:0] RdTimM);
logic [XLEN-1:0] RAM[0:65535];
logic [XLEN-1:0] write;
logic [`XLEN-1:0] RAM[0:65535];
logic [`XLEN-1:0] write;
logic [15:0] entry;
logic memread, memwrite;
@ -43,7 +43,7 @@ module dtim #(parameter XLEN=32) (
// word aligned reads
generate
if (XLEN==64)
if (`XLEN==64)
assign #2 entry = AdrM[18:3];
else
assign #2 entry = AdrM[17:2];
@ -56,7 +56,7 @@ module dtim #(parameter XLEN=32) (
// from dmem
generate
if (XLEN==64) begin
if (`XLEN==64) begin
always_comb begin
write=RdTimM;
if (ByteMaskM[0]) write[7:0] = WriteDataM[7:0];

16
wally-pipelined/src/extend.sv
View File

@ -23,25 +23,25 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module extend #(parameter XLEN=32) (
module extend (
input logic [31:7] InstrDecompD,
input logic [2:0] ImmSrcD,
output logic [XLEN-1:0] ExtImmD);
output logic [`XLEN-1:0] ExtImmD);
always_comb
case(ImmSrcD)
// I-type
3'b000: ExtImmD = {{(XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:20]};
3'b000: ExtImmD = {{(`XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:20]};
// S-type (stores)
3'b001: ExtImmD = {{(XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:25], InstrDecompD[11:7]};
3'b001: ExtImmD = {{(`XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:25], InstrDecompD[11:7]};
// B-type (branches)
3'b010: ExtImmD = {{(XLEN-12){InstrDecompD[31]}}, InstrDecompD[7], InstrDecompD[30:25], InstrDecompD[11:8], 1'b0};
3'b010: ExtImmD = {{(`XLEN-12){InstrDecompD[31]}}, InstrDecompD[7], InstrDecompD[30:25], InstrDecompD[11:8], 1'b0};
// J-type (jal)
3'b011: ExtImmD = {{(XLEN-20){InstrDecompD[31]}}, InstrDecompD[19:12], InstrDecompD[20], InstrDecompD[30:21], 1'b0};
3'b011: ExtImmD = {{(`XLEN-20){InstrDecompD[31]}}, InstrDecompD[19:12], InstrDecompD[20], InstrDecompD[30:21], 1'b0};
// U-type (lui, auipc)
3'b100: ExtImmD = {{(XLEN-31){InstrDecompD[31]}}, InstrDecompD[30:12], 12'b0};
3'b100: ExtImmD = {{(`XLEN-31){InstrDecompD[31]}}, InstrDecompD[30:12], 12'b0};
/* verilator lint_off WIDTH */
default: ExtImmD = 'bx; // undefined
/* verilator lint_on WIDTH */

2
wally-pipelined/src/flop.sv
View File

@ -23,7 +23,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
// ordinary flip-flop
module flop #(parameter WIDTH = 8) (

12
wally-pipelined/src/gpio.sv
View File

@ -25,15 +25,15 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module gpio #(parameter XLEN=32) (
module gpio (
input logic clk, reset,
input logic [1:0] MemRWgpioM,
input logic [7:0] ByteMaskM,
input logic [7:0] AdrM,
input logic [XLEN-1:0] MaskedWriteDataM,
output logic [XLEN-1:0] RdGPIOM,
input logic [`XLEN-1:0] MaskedWriteDataM,
output logic [`XLEN-1:0] RdGPIOM,
input logic [31:0] GPIOPinsIn,
output logic [31:0] GPIOPinsOut, GPIOPinsEn);
@ -47,7 +47,7 @@ module gpio #(parameter XLEN=32) (
// word aligned reads
generate
if (XLEN==64)
if (`XLEN==64)
assign #2 entry = {AdrM[7:3], 3'b000};
else
assign #2 entry = {AdrM[7:2], 2'b00};
@ -64,7 +64,7 @@ module gpio #(parameter XLEN=32) (
// register access
generate
if (XLEN==64) begin
if (`XLEN==64) begin
always_comb begin
case(entry)
8'h00: RdGPIOM = {INPUT_EN, INPUT_VAL};

2
wally-pipelined/src/hazard.sv
View File

@ -23,7 +23,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module hazard(
input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,

16
wally-pipelined/src/imem.sv
View File

@ -23,19 +23,19 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module imem #(parameter XLEN=32) (
input logic [XLEN-1:0] AdrF,
module imem (
input logic [`XLEN-1:0] AdrF,
output logic [31:0] InstrF,
output logic InstrAccessFaultF);
logic [XLEN-1:0] RAM[0:65535];
logic [`XLEN-1:0] RAM[0:65535];
logic [15:0] adrbits;
logic [XLEN-1:0] rd, rd2;
logic [`XLEN-1:0] rd, rd2;
generate
if (XLEN==32) assign adrbits = AdrF[17:2];
if (`XLEN==32) assign adrbits = AdrF[17:2];
else assign adrbits = AdrF[18:3];
endgenerate
@ -47,13 +47,13 @@ module imem #(parameter XLEN=32) (
// could be optimized to only stall when the instruction wrapping is 32 bits
assign #2 rd2 = RAM[adrbits+1];
generate
if (XLEN==32) begin
if (`XLEN==32) begin
assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd;
assign InstrAccessFaultF = ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF
end else begin
assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32])
: (AdrF[1] ? rd[47:16] : rd[31:0]);
assign InstrAccessFaultF = (|AdrF[XLEN-1:32]) | ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF]
assign InstrAccessFaultF = (|AdrF[`XLEN-1:32]) | ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF]
end
endgenerate
endmodule

16
wally-pipelined/src/instrDecompress.sv
View File

@ -23,9 +23,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module instrDecompress #(parameter XLEN=32, MISA=1) (
module instrDecompress (
input logic [31:0] InstrD,
output logic [31:0] InstrDecompD,
output logic IllegalCompInstrD);
@ -89,18 +89,18 @@ module instrDecompress #(parameter XLEN=32, MISA=1) (
end
5'b00001: InstrDecompD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
5'b00010: InstrDecompD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
5'b00011: if (XLEN==32)
5'b00011: if (`XLEN==32)
InstrDecompD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
else
InstrDecompD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
5'b00101: InstrDecompD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
5'b00110: InstrDecompD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
5'b00111: if (XLEN==32)
5'b00111: if (`XLEN==32)
InstrDecompD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
else
InstrDecompD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
5'b01000: InstrDecompD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
5'b01001: if (XLEN==32)
5'b01001: if (`XLEN==32)
InstrDecompD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
else
InstrDecompD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
@ -124,7 +124,7 @@ module instrDecompress #(parameter XLEN=32, MISA=1) (
InstrDecompD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
else // if (instr16[6:5] == 2'b11)
InstrDecompD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
else if (instr16[12:10] == 3'b111 && XLEN > 32)
else if (instr16[12:10] == 3'b111 && `XLEN > 32)
if (instr16[6:5] == 2'b00)
InstrDecompD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
else if (instr16[6:5] == 2'b01)
@ -143,7 +143,7 @@ module instrDecompress #(parameter XLEN=32, MISA=1) (
5'b10000: InstrDecompD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
5'b10001: InstrDecompD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
5'b10010: InstrDecompD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
5'b10011: if (XLEN == 32)
5'b10011: if (`XLEN == 32)
InstrDecompD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
else
InstrDecompD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
@ -162,7 +162,7 @@ module instrDecompress #(parameter XLEN=32, MISA=1) (
InstrDecompD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
5'b10101: InstrDecompD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
5'b10110: InstrDecompD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
5'b10111: if (XLEN==32)
5'b10111: if (`XLEN==32)
InstrDecompD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
else
InstrDecompD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp

16
wally-pipelined/src/memdp.sv
View File

@ -23,16 +23,16 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module memdp #(parameter XLEN=32) (
module memdp (
input logic [1:0] MemRWM,
input logic [XLEN-1:0] ReadDataM,
input logic [XLEN-1:0] AdrM,
input logic [`XLEN-1:0] ReadDataM,
input logic [`XLEN-1:0] AdrM,
input logic [2:0] Funct3M,
output logic [XLEN-1:0] ReadDataExtM,
input logic [XLEN-1:0] WriteDataFullM,
output logic [XLEN-1:0] WriteDataM,
output logic [`XLEN-1:0] ReadDataExtM,
input logic [`XLEN-1:0] WriteDataFullM,
output logic [`XLEN-1:0] WriteDataM,
output logic [7:0] ByteMaskM,
input logic DataAccessFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM,
@ -43,7 +43,7 @@ module memdp #(parameter XLEN=32) (
logic UnalignedM;
generate
if (XLEN == 64) begin
if (`XLEN == 64) begin
// bytMe mux
always_comb
case(AdrM[2:0])

2
wally-pipelined/src/mux.sv
View File

@ -23,7 +23,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module mux2 #(parameter WIDTH = 8) (

34
wally-pipelined/src/pclogic.sv
View File

@ -23,26 +23,26 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module pclogic #(parameter XLEN=64, MISA=0) (
module pclogic (
input logic clk, reset,
input logic StallF, PCSrcE,
input logic [31:0] InstrF,
input logic [XLEN-1:0] ExtImmE, TargetBaseE,
input logic [`XLEN-1:0] ExtImmE, TargetBaseE,
input logic RetM, TrapM,
input logic [XLEN-1:0] PrivilegedNextPCM,
output logic [XLEN-1:0] PCF, PCPlus2or4F,
input logic [`XLEN-1:0] PrivilegedNextPCM,
output logic [`XLEN-1:0] PCF, PCPlus2or4F,
output logic InstrMisalignedFaultM,
output logic [XLEN-1:0] InstrMisalignedAdrM);
output logic [`XLEN-1:0] InstrMisalignedAdrM);
logic [XLEN-1:0] UnalignedPCNextF, PCNextF, PCTargetE;
// logic [XLEN-1:0] ResetVector = 'h100;
// logic [XLEN-1:0] ResetVector = 'he4;
logic [XLEN-1:0] ResetVector = {{(XLEN-32){1'b0}}, 32'h80000000};
logic [`XLEN-1:0] UnalignedPCNextF, PCNextF, PCTargetE;
// logic [`XLEN-1:0] ResetVector = 'h100;
// logic [`XLEN-1:0] ResetVector = 'he4;
logic [`XLEN-1:0] ResetVector = {{(`XLEN-32){1'b0}}, 32'h80000000};
logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
logic StallExceptResolveBranchesF, PrivilegedChangePCM;
logic [XLEN-3:0] PCPlusUpperF;
logic [`XLEN-3:0] PCPlusUpperF;
logic CompressedF;
assign PrivilegedChangePCM = RetM | TrapM;
@ -50,20 +50,20 @@ module pclogic #(parameter XLEN=64, MISA=0) (
assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM);
assign PCTargetE = ExtImmE + TargetBaseE;
mux3 #(XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF);
assign PCNextF = {UnalignedPCNextF[XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
flopenl #(XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, ResetVector, PCF);
mux3 #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF);
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, ResetVector, PCF);
// pcadder
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
assign CompressedF = (InstrF[1:0] != 2'b11); // is it a 16-bit compressed instruction?
assign PCPlusUpperF = PCF[XLEN-1:2] + 1; // add 4 to PC
assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC
// choose PC+2 or PC+4
always_comb
if (CompressedF) // add 2
if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00};
else PCPlus2or4F = {PCF[XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
// Misaligned PC logic
@ -78,7 +78,7 @@ module pclogic #(parameter XLEN=64, MISA=0) (
// pipeline misaligned faults to M stage
assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned
flopr #(1) InstrMisalginedReg(clk, reset, BranchMisalignedFaultE, BranchMisalignedFaultM);
flopr #(XLEN) InstrMisalignedAdrReg(clk, reset, PCNextF, InstrMisalignedAdrM);
flopr #(`XLEN) InstrMisalignedAdrReg(clk, reset, PCNextF, InstrMisalignedAdrM);
assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM;
assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path

4
wally-pipelined/src/privilegeDecoder.sv
View File

@ -24,9 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module privilegeDecoder #(parameter MISA=0) (
module privilegeDecoder (
input logic [31:20] InstrM,
input logic PrivilegedM, IllegalInstrFaultInM, IllegalCSRAccessM,
input logic [1:0] PrivilegeModeW,

10
wally-pipelined/src/privilegeModeReg.sv
View File

@ -24,20 +24,20 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module privilegeModeReg #(parameter XLEN=32, MISA=0) (
module privilegeModeReg (
input logic clk, reset,
input logic mretM, sretM, uretM, TrapM,
input logic [1:0] STATUS_MPP,
input logic STATUS_SPP,
input logic [XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, CauseM,
input logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, CauseM,
output logic [1:0] NextPrivilegeModeM, PrivilegeModeW);
logic md, sd;
// get bits of DELEG registers based on CAUSE
assign md = CauseM[XLEN-1] ? MIDELEG_REGW[CauseM[4:0]] : MEDELEG_REGW[CauseM[4:0]];
assign sd = CauseM[XLEN-1] ? SIDELEG_REGW[CauseM[4:0]] : SEDELEG_REGW[CauseM[4:0]]; // depricated
assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[4:0]] : MEDELEG_REGW[CauseM[4:0]];
assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[4:0]] : SEDELEG_REGW[CauseM[4:0]]; // depricated
always_comb
if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode)

28
wally-pipelined/src/privileged.sv
View File

@ -24,16 +24,16 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)(
module privileged (
input logic clk, reset,
input logic CSRWriteM,
input logic [XLEN-1:0] SrcAM,
input logic [`XLEN-1:0] SrcAM,
input logic [31:0] InstrM,
input logic [XLEN-1:0] PCM,
output logic [XLEN-1:0] CSRReadValM,
output logic [XLEN-1:0] PrivilegedNextPCM,
input logic [`XLEN-1:0] PCM,
output logic [`XLEN-1:0] CSRReadValM,
output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM,
input logic InstrValidW, FloatRegWriteW, LoadStallD,
input logic PrivilegedM,
@ -41,16 +41,16 @@ module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)(
input logic LoadMisalignedFaultM, LoadAccessFaultM,
input logic StoreMisalignedFaultM, StoreAccessFaultM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic [XLEN-1:0] InstrMisalignedAdrM, ALUResultM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, ALUResultM,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW
);
logic [1:0] NextPrivilegeModeM, PrivilegeModeW;
logic [XLEN-1:0] CauseM, NextFaultMtvalM;
logic [XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW;
logic [XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW;
logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
// logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW;
logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
@ -66,10 +66,10 @@ module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)(
logic [11:0] MIP_REGW, MIE_REGW;
// track the current privilege level
privilegeModeReg #(XLEN, MISA) pmr (.*);
privilegeModeReg pmr(.*);
// decode privileged instructions
privilegeDecoder #(MISA) pmd(.InstrM(InstrM[31:20]), .*);
privilegeDecoder pmd(.InstrM(InstrM[31:20]), .*);
// Extract exceptions by name and handle them
assign BreakpointFaultM = ebreakM; // could have other causes too
@ -77,10 +77,10 @@ module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)(
assign InstrPageFaultM = 0;
assign LoadPageFaultM = 0;
assign StorePageFaultM = 0;
trap #(XLEN, MISA) trap(.*);
trap trap(.*);
// Control and Status Registers
csr #(XLEN, MISA, ZCSR, ZCOUNTERS) csr(.*);
csr csr(.*);
endmodule

10
wally-pipelined/src/regfile.sv
View File

@ -23,16 +23,16 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module regfile #(parameter XLEN=32) (
module regfile (
input logic clk, reset,
input logic we3,
input logic [ 4:0] a1, a2, a3,
input logic [XLEN-1:0] wd3,
output logic [XLEN-1:0] rd1, rd2);
input logic [`XLEN-1:0] wd3,
output logic [`XLEN-1:0] rd1, rd2);
logic [XLEN-1:0] rf[31:1];
logic [`XLEN-1:0] rf[31:1];
integer i;
// three ported register file

4
wally-pipelined/src/shifter.sv
View File

@ -23,7 +23,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module shifter #(parameter WIDTH=32) (
input logic [WIDTH-1:0] a,
@ -31,7 +31,7 @@ module shifter #(parameter WIDTH=32) (
input logic right, arith, w64,
output logic [WIDTH-1:0] y);
// The best shifter architecture differs based on XLEN.
// The best shifter architecture differs based on `XLEN.
// for RV32, only 32-bit shifts are needed. These are
// most efficiently implemented with a funnel shifter.
// For RV64, 32 and 64-bit shifts are needed, with sign

28
wally-pipelined/src/testbench.sv
View File

@ -23,22 +23,22 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module testbench #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOUNTERS = 1)();
module testbench();
logic clk;
logic reset;
logic [XLEN-1:0] WriteData, DataAdr;
logic [`XLEN-1:0] WriteData, DataAdr;
logic [1:0] MemRW;
int test, i, errors, totalerrors;
logic [31:0] sig32[0:10000];
logic [XLEN-1:0] signature[0:10000];
logic [XLEN-1:0] testadr;
logic [`XLEN-1:0] signature[0:10000];
logic [`XLEN-1:0] testadr;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW;
logic [XLEN-1:0] meminit;
logic [`XLEN-1:0] meminit;
string tests64ic[] = '{
"rv64ic/I-C-ADD-01", "3000",
@ -224,7 +224,7 @@ string tests32i[] = {
// pick tests based on modes supported
initial
if (XLEN == 64) begin // RV64
if (`XLEN == 64) begin // RV64
tests = {tests64i};
if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic};
else tests = {tests, tests64iNOc};
@ -240,13 +240,13 @@ string tests32i[] = {
// instantiate device to be tested
assign GPIOPinsIn = 0;
wallypipelined #(XLEN, MISA, ZCSR, ZCOUNTERS) dut(
wallypipelined dut(
clk, reset, WriteData, DataAdr, MemRW,
GPIOPinsIn, GPIOPinsOut, GPIOPinsEn, UARTSin, UARTSout
);
// Track names of instructions
instrTrackerTB #(XLEN) it(clk, reset, dut.hart.dp.FlushE,
instrTrackerTB it(clk, reset, dut.hart.dp.FlushE,
dut.hart.dp.InstrDecompD, dut.hart.dp.InstrE,
dut.hart.dp.InstrM, InstrW,
InstrDName, InstrEName, InstrMName, InstrWName);
@ -258,7 +258,7 @@ string tests32i[] = {
totalerrors = 0;
testadr = 0;
// fill memory with defined values to reduce Xs in simulation
if (XLEN == 32) meminit = 32'hFEDC0123;
if (`XLEN == 32) meminit = 32'hFEDC0123;
else meminit = 64'hFEDCBA9876543210;
for (i=0; i<=65535; i = i+1) begin
//dut.imem.RAM[i] = meminit;
@ -294,7 +294,7 @@ string tests32i[] = {
$readmemh(signame, sig32);
i = 0;
while (i < 10000) begin
if (XLEN == 32) begin
if (`XLEN == 32) begin
signature[i] = sig32[i];
i = i+1;
end else begin
@ -306,7 +306,7 @@ string tests32i[] = {
// Check errors
i = 0;
errors = 0;
if (XLEN == 32)
if (`XLEN == 32)
testadr = tests[test+1].atohex()/4;
else
testadr = tests[test+1].atohex()/8;
@ -319,7 +319,7 @@ string tests32i[] = {
// kind of hacky test for garbage right now
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
tests[test], i, (testadr+i)*XLEN/8, dut.dmem.dtim.RAM[testadr+i], signature[i]);
tests[test], i, (testadr+i)*`XLEN/8, dut.dmem.dtim.RAM[testadr+i], signature[i]);
end
end
i = i + 1;
@ -350,7 +350,7 @@ endmodule
/* verilator lint_on STMTDLY */
/* verilator lint_on WIDTH */
module instrTrackerTB #(parameter XLEN=32) (
module instrTrackerTB(
input logic clk, reset, FlushE,
input logic [31:0] InstrD,
input logic [31:0] InstrE, InstrM,

26
wally-pipelined/src/trap.sv
View File

@ -24,9 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module trap #(parameter XLEN=32, MISA=0) (
module trap (
input logic clk, reset,
input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
@ -34,13 +34,13 @@ module trap #(parameter XLEN=32, MISA=0) (
input logic LoadPageFaultM, StorePageFaultM,
input logic mretM, sretM, uretM,
input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
input logic [XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
input logic [11:0] MIP_REGW, MIE_REGW,
input logic STATUS_MIE, STATUS_SIE,
input logic [XLEN-1:0] InstrMisalignedAdrM, ALUResultM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, ALUResultM,
input logic [31:0] InstrM,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
output logic [XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
);
@ -76,18 +76,18 @@ module trap #(parameter XLEN=32, MISA=0) (
// Exceptions are of lower priority than all interrupts (3.1.9)
always_comb
if (reset) CauseM = 0; // hard reset 3.3
else if (PendingIntsM[11]) CauseM = (1 << (XLEN-1)) + 11; // Machine External Int
else if (PendingIntsM[3]) CauseM = (1 << (XLEN-1)) + 3; // Machine Sw Int
else if (PendingIntsM[7]) CauseM = (1 << (XLEN-1)) + 7; // Machine Timer Int
else if (PendingIntsM[9]) CauseM = (1 << (XLEN-1)) + 9; // Supervisor External Int
else if (PendingIntsM[1]) CauseM = (1 << (XLEN-1)) + 1; // Supervisor Sw Int
else if (PendingIntsM[5]) CauseM = (1 << (XLEN-1)) + 5; // Supervisor Timer Int
else if (PendingIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int
else if (PendingIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int
else if (PendingIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int
else if (PendingIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int
else if (PendingIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int
else if (PendingIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int
else if (InstrPageFaultM) CauseM = 12;
else if (InstrAccessFaultM) CauseM = 1;
else if (InstrMisalignedFaultM) CauseM = 0;
else if (IllegalInstrFaultM) CauseM = 2;
else if (BreakpointFaultM) CauseM = 3;
else if (EcallFaultM) CauseM = {{(XLEN-2){1'b0}}, PrivilegeModeW} + 8;
else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8;
else if (LoadMisalignedFaultM) CauseM = 4;
else if (StoreMisalignedFaultM) CauseM = 6;
else if (LoadPageFaultM) CauseM = 13;
@ -112,6 +112,6 @@ module trap #(parameter XLEN=32, MISA=0) (
else if (InstrPageFaultM) NextFaultMtvalM = 0; // *** implement
else if (LoadPageFaultM) NextFaultMtvalM = ALUResultM;
else if (StorePageFaultM) NextFaultMtvalM = ALUResultM;
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(XLEN-32){1'b0}}, InstrM};
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
else NextFaultMtvalM = 0;
endmodule

12
wally-pipelined/src/uart.sv
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@ -25,15 +25,15 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module uart #(parameter XLEN=32) (
module uart (
input logic clk, reset,
input logic [1:0] MemRWgpioM,
input logic [7:0] ByteMaskM,
input logic [XLEN-1:0] AdrM,
input logic [XLEN-1:0] MaskedWriteDataM,
output logic [XLEN-1:0] RdUARTM,
input logic [`XLEN-1:0] AdrM,
input logic [`XLEN-1:0] MaskedWriteDataM,
output logic [`XLEN-1:0] RdUARTM,
input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface
output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU
@ -50,7 +50,7 @@ module uart #(parameter XLEN=32) (
assign A = AdrM[2:0];
generate
if (XLEN == 64) begin
if (`XLEN == 64) begin
always_comb begin
/* RdUARTM = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
case (AdrM[2:0])

2
wally-pipelined/src/uartPC16550D.sv
View File

@ -29,7 +29,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module uartPC16550D(
// Processor Interface

67
wally-pipelined/src/wally-config.vh Normal file
View File

@ -0,0 +1,67 @@
//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
`define MISA (32'h00000104)
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define ZCOUNTERS_SUPPORTED 1
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
`define M_MODE (2'b11)
`define S_MODE (2'b01)
`define U_MODE (2'b00)
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
`define MEM_DCACHE 0
`define MEM_DTIM 1
`define MEM_ICACHE 0
`define MEM_VIRTMEM 0
// Test modes
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 0
// Hardware configuration
`define UART_PRESCALE 1
/* verilator lint_off STMTDLY */
/* verilator lint_off WIDTH */

14
wally-pipelined/src/wallypipelined.sv
View File

@ -50,11 +50,11 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module wallypipelined #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
module wallypipelined (
input logic clk, reset,
output logic [XLEN-1:0] WriteDataM, DataAdrM,
output logic [`XLEN-1:0] WriteDataM, DataAdrM,
output logic [1:0] MemRWM,
input logic [31:0] GPIOPinsIn,
output logic [31:0] GPIOPinsOut, GPIOPinsEn,
@ -62,7 +62,7 @@ module wallypipelined #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
output logic UARTSout
);
logic [XLEN-1:0] PCF, ReadDataM;
logic [`XLEN-1:0] PCF, ReadDataM;
logic [31:0] InstrF;
logic [7:0] ByteMaskM;
logic InstrAccessFaultF, DataAccessFaultM;
@ -70,8 +70,8 @@ module wallypipelined #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
logic ExtIntM = 0; // not yet connected
// instantiate processor and memories
wallypipelinedhart #(XLEN, MISA, ZCSR, ZCOUNTERS) hart(.ALUResultM(DataAdrM), .*);
wallypipelinedhart hart(.ALUResultM(DataAdrM), .*);
imem #(XLEN) imem(.AdrF(PCF), .*);
dmem #(XLEN) dmem(.AdrM(DataAdrM), .*);
imem imem(.AdrF(PCF), .*);
dmem dmem(.AdrM(DataAdrM), .*);
endmodule

14
wally-pipelined/src/wallypipelinedhart.sv
View File

@ -23,16 +23,16 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
`include "wally-config.vh"
module wallypipelinedhart #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
module wallypipelinedhart (
input logic clk, reset,
output logic [XLEN-1:0] PCF,
output logic [`XLEN-1:0] PCF,
input logic [31:0] InstrF,
output logic [1:0] MemRWM,
output logic [7:0] ByteMaskM,
output logic [XLEN-1:0] ALUResultM, WriteDataM,
input logic [XLEN-1:0] ReadDataM,
output logic [`XLEN-1:0] ALUResultM, WriteDataM,
input logic [`XLEN-1:0] ReadDataM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrAccessFaultF,
input logic DataAccessFaultM);
@ -70,8 +70,8 @@ module wallypipelinedhart #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1)
logic FloatRegWriteW;
controller c(.*);
datapath #(XLEN, MISA, ZCSR, ZCOUNTERS) dp(.*);
hazard hz(.*);
datapath dp(.*);
hazard hz(.*);
// add FPU here, with SetFflagsM, FRM_REGW
// presently stub out SetFlagsM and FloatRegWriteW