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plic subword access compliance
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@ -50,8 +50,9 @@ module plic (
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// N in config should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec
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localparam N=`PLIC_NUM_SRC;
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logic memread, memwrite, initTrans;
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logic [27:0] entry, A;
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logic memwrite, initTrans;
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logic [27:0] entry, entryd;
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logic [31:0] Din, Dout;
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logic [N:1] requests;
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logic [2:0] intPriority[N:1];
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@ -66,17 +67,34 @@ module plic (
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logic [7:1] threshMask;
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// AHB I/O
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assign entry = {HADDR[27:2],2'b0};
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assign initTrans = HREADY & HSELPLIC & (HTRANS != 2'b00);
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flopenrc #(1) memreadreg(HCLK, ~HRESETn, memread&HREADY, (memread&HREADY)|initTrans, HSELPLIC & ~HWRITE, memread);
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flopenrc #(1) memwritereg(HCLK, ~HRESETn, memwrite&HREADY, (memwrite&HREADY)|initTrans, HSELPLIC & HWRITE, memwrite);
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flopenr #(28) haddrreg(HCLK, ~HRESETn,initTrans, HADDR, A);
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flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite);
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flopr #(28) entrydflop(HCLK, ~HRESETn, entry, entryd);
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assign HRESPPLIC = 0; // OK
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assign HREADYPLIC = 1'b1; // will need to be modified if PLIC ever needs more than 1 cycle to do something
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assign HREADYPLIC = 1'b1; // PLIC never takes >1 cycle to respond
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// word aligned reads
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assign #2 entry = {A[27:2], 2'b00};
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// account for subword read/write circuitry
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// Note PLIC registers are 32 bits no matter what; access them with LW SW.
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generate
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if (`XLEN == 64) begin
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always_comb
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if (entryd[2]) begin
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Din = HWDATA[63:32];
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HREADPLIC = {Dout,32'b0};
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end else begin
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Din = HWDATA[31:0];
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HREADPLIC = {32'b0,Dout};
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end
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end else begin // 32-bit
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always_comb begin
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Din = HWDATA[31:0];
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HREADPLIC = Dout;
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end
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end
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endgenerate
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// register access
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// register interface
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genvar i;
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generate
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// priority registers
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@ -84,89 +102,62 @@ module plic (
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always @(posedge HCLK,negedge HRESETn)
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if (~HRESETn)
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intPriority[i] <= 3'b0;
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else if (entry == 28'hc000000+4*i) // *** make sure this does not synthesize into N 28-bit equality comparators
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if (memwrite) intPriority[i] <= #1 HWDATA[2:0];
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else HREADPLIC <= #1 {{(`XLEN-3){1'b0}},intPriority[i]};
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else begin
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if (entry == 28'hc000000+4*i) // *** make sure this does not synthesize into N 28-bit equality comparators
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Dout <= #1 {{(`XLEN-3){1'b0}},intPriority[i]};
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if ((entryd == 28'hc000000+4*i) && memwrite)
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intPriority[i] <= #1 Din[2:0];
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end
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// pending and enable registers
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if (N<32 && `XLEN==32)
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if (N<32)
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always @(posedge HCLK,negedge HRESETn)
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if (~HRESETn)
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intEn <= {N{1'b0}};
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else
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case(entry)
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28'hc001000: HREADPLIC <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0};
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28'hc002000: if (memwrite) intEn[N:1] <= #1 HWDATA[N:1];
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else HREADPLIC <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0};
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endcase
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else if (N>=32 && `XLEN==32)
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else begin
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if (entry == 28'hc001000)
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Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0};
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if (entry == 28'hc002000)
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Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0};
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if ((entryd == 28'hc002000) && memwrite)
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intEn[N:1] <= #1 Din[N:1];
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end
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else // N>=32
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always @(posedge HCLK,negedge HRESETn)
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if (~HRESETn)
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intEn <= {N{1'b0}};
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else
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case(entry)
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28'hc001000: HREADPLIC <= #1 {intPending[31:1],1'b0};
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28'hc001004: HREADPLIC <= #1 {{(63-N){1'b0}},intPending[N:32]};
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28'hc002000: if (memwrite) intEn[31:1] <= #1 HWDATA[31:1];
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else HREADPLIC <= #1 {intEn[31:1],1'b0};
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28'hc002004: if (memwrite) intEn[N:32] <= #1 HWDATA[31:0];
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else HREADPLIC <= #1 {{(63-N){1'b0}},intEn[N:32]};
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endcase
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else if (N<32 && `XLEN==64)
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always @(posedge HCLK,negedge HRESETn)
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if (~HRESETn)
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intEn <= {N{1'b0}};
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else
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case(entry)
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28'hc001000: HREADPLIC <= #1 {{(63-N){1'b0}},intPending[N:1],1'b0};
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28'hc002000: if (memwrite) intEn[N:1] <= #1 HWDATA[N:1];
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else HREADPLIC <= #1 {{(63-N){1'b0}},intEn[N:1],1'b0};
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endcase
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else if (N>=32 && `XLEN==64)
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always @(posedge HCLK,negedge HRESETn)
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if (~HRESETn)
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intEn <= {N{1'b0}};
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else
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case(entry)
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28'hc001000: HREADPLIC <= #1 {32'b0,intPending[31:1],1'b0};
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28'hc001004: HREADPLIC <= #1 {{(63-N){1'b0}},intPending[N:32],32'b0}; // rearranged so that you can access it with lw (when addr%8 = 4, subwordwrite thinks we are looking at the upper half of a 64bit word); *** is this reasonable? Why does SWW work like that anyways?; if we don't mind 32 and 64 bit versions having different memory maps, that might clean things up, but it might also be a departure of spec
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28'hc002000: if (memwrite) intEn[31:1] <= #1 HWDATA[31:1];
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else HREADPLIC <= #1 {intEn[31:1],1'b0};
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28'hc002004: if (memwrite) intEn[N:32] <= #1 HWDATA[63:32];
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else HREADPLIC <= #1 {{(63-N){1'b0}},intEn[N:32],32'b0};
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endcase
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else begin
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if (entry == 28'hc001000)
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Dout <= #1 {intPending[31:1],1'b0};
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if (entry == 28'hc001004)
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Dout <= #1 {{(63-N){1'b0}},intPending[N:32]};
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if (entry == 28'hc002000)
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Dout <= #1 {intEn[31:1],1'b0};
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if (entry == 28'hc002004)
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Dout <= #1 {{(63-N){1'b0}},intEn[N:32]};
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if ((entryd == 28'hc002000) && memwrite)
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intEn[31:1] <= #1 Din[31:1];
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if ((entryd == 28'hc002004) && memwrite)
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intEn[N:32] <= #1 Din[31:0];
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end
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// threshold and claim/complete registers
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if (`XLEN==32)
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always @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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intThreshold<=3'b0;
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intInProgress <= {N{1'b0}};
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end else
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case (HADDR)
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28'hc200000: if (memwrite) intThreshold[2:0] <= #1 HWDATA[2:0];
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else HREADPLIC <= #1 {{29{1'b0}},intThreshold[2:0]};
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28'hc200004: if (memwrite) intInProgress <= #1 intInProgress & ~(1'b1 << (HWDATA[5:0]-1)); // lower "InProgress" to signify completion
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else begin
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HREADPLIC <= #1 {{26{1'b0}},intClaim};
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intInProgress <= #1 intInProgress | (1'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
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end
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endcase
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else if (`XLEN==64)
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always @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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intThreshold<=3'b0;
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intInProgress <= {N{1'b0}};
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end else
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case (HADDR)
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28'hc200000: if (memwrite) intThreshold[2:0] <= #1 HWDATA[2:0];
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else HREADPLIC <= #1 {{61{1'b0}},intThreshold[2:0]};
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28'hc200004: if (memwrite) intInProgress <= #1 intInProgress & ~(1'b1 << (HWDATA[5:0]-1)); // lower "InProgress" to signify completion
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else begin
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HREADPLIC <= #1 {{26{1'b0}},intClaim,32'b0};
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intInProgress <= #1 intInProgress | (1'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
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end
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endcase
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always @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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intThreshold<=3'b0;
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intInProgress <= {N{1'b0}};
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end else begin
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if (entry == 28'hc200000)
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Dout <= #1 {29'b0,intThreshold[2:0]};
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if ((entryd == 28'hc200000) && memwrite)
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intThreshold[2:0] <= #1 Din[2:0];
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if (entry == 28'hc200004) begin
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Dout <= #1 {26'b0,intClaim};
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intInProgress <= #1 intInProgress | (1'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
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end
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if ((entryd == 28'hc200004) && memwrite)
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intInProgress <= #1 intInProgress & ~(1'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
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end
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endgenerate
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// connect sources to requests
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