mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 17:55:19 +00:00
Merged bus into main
This commit is contained in:
David Harris
commit
cd4ba8831c
@ -61,7 +61,7 @@
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// Bus Interface width
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`define AHBW 64
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// Peripheral Addresses
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// Peripheral Physiccal Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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@ -45,11 +45,14 @@ view wave
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add wave /testbench/clk
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add wave /testbench/reset
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add wave -divider
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add wave /testbench/dut/hart/ebu/IReadF
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#add wave /testbench/dut/hart/ebu/IReadF
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add wave /testbench/dut/hart/DataStall
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add wave /testbench/dut/hart/InstrStall
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add wave /testbench/dut/hart/StallF
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add wave /testbench/dut/hart/StallD
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add wave /testbench/dut/hart/StallE
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add wave /testbench/dut/hart/StallM
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add wave /testbench/dut/hart/StallW
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add wave /testbench/dut/hart/FlushD
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add wave /testbench/dut/hart/FlushE
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add wave /testbench/dut/hart/FlushM
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@ -59,26 +62,27 @@ add wave -divider
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add wave -hex /testbench/dut/hart/ifu/PCF
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add wave -hex /testbench/dut/hart/ifu/InstrF
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add wave /testbench/InstrFName
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#add wave -hex /testbench/dut/hart/ifu/PCD
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add wave -hex /testbench/dut/hart/ifu/PCD
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add wave -hex /testbench/dut/hart/ifu/InstrD
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add wave /testbench/InstrDName
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add wave -divider
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#add wave -hex /testbench/dut/hart/ifu/PCE
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#add wave -hex /testbench/dut/hart/ifu/InstrE
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add wave -hex /testbench/dut/hart/ifu/PCE
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add wave -hex /testbench/dut/hart/ifu/InstrE
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add wave /testbench/InstrEName
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add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
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add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
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add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
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add wave /testbench/dut/hart/ieu/dp/PCSrcE
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add wave -divider
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#add wave -hex /testbench/dut/hart/ifu/PCM
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#add wave -hex /testbench/dut/hart/ifu/InstrM
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add wave -hex /testbench/dut/hart/ifu/PCM
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add wave -hex /testbench/dut/hart/ifu/InstrM
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add wave /testbench/InstrMName
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add wave /testbench/dut/uncore/dtim/memwrite
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add wave -hex /testbench/dut/uncore/HADDR
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add wave -hex /testbench/dut/uncore/HWDATA
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add wave -divider
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add wave -hex /testbench/dut/hart/ifu/PCW
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add wave -hex /testbench/dut/hart/ifu/InstrW
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add wave /testbench/InstrWName
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add wave /testbench/dut/hart/ieu/dp/RegWriteW
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add wave -hex /testbench/dut/hart/ieu/dp/ResultW
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@ -101,6 +105,6 @@ configure wave -childrowmargin 2
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set DefaultRadix hexadecimal
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-- Run the Simulation
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#run 1000
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run -all
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run 2000
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#run -all
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#quit
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@ -30,19 +30,19 @@
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module dmem (
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input logic clk, reset,
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input logic FlushW,
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output logic DataStall,
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//output logic DataStall,
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// Memory Stage
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input logic [1:0] MemRWM,
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input logic [`XLEN-1:0] MemAdrM,
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input logic [2:0] Funct3M,
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input logic [`XLEN-1:0] ReadDataM,
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//input logic [`XLEN-1:0] ReadDataW,
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input logic [`XLEN-1:0] WriteDataM,
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output logic [`XLEN-1:0] MemPAdrM,
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output logic [1:0] MemRWAlignedM,
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output logic MemReadM, MemWriteM,
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output logic DataMisalignedM,
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// Writeback Stage
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input logic MemAckW,
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output logic [`XLEN-1:0] ReadDataW,
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input logic [`XLEN-1:0] ReadDataW,
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// faults
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input logic DataAccessFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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@ -52,9 +52,6 @@ module dmem (
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// Initially no MMU
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assign MemPAdrM = MemAdrM;
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// Pipeline register *** AHB data will eventually come back in W anyway
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floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataM, ReadDataW);
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// Determine if an Unaligned access is taking place
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always_comb
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case(Funct3M[1:0])
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@ -66,7 +63,9 @@ module dmem (
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// Squash unaligned data accesses
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// *** this is also the place to squash if the cache is hit
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assign MemRWAlignedM = MemRWM & {2{~DataMisalignedM}};
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assign MemReadM = MemRWM[1] & ~DataMisalignedM;
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assign MemWriteM = MemRWM[0] & ~DataMisalignedM;
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// assign MemRWAlignedM = MemRWM & {2{~DataMisalignedM}};
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// Determine if address is valid
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assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
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@ -75,7 +74,7 @@ module dmem (
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assign StoreAccessFaultM = DataAccessFaultM & MemRWM[0];
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// Data stall
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assign DataStall = 0;
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//assign DataStall = 0;
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endmodule
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@ -32,21 +32,21 @@
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module ahblite (
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input logic clk, reset,
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input logic StallW, FlushW,
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// Load control
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input logic UnsignedLoadM,
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// Signals from Instruction Cache
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input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram
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input logic IReadF,
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output logic [`XLEN-1:0] IRData,
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// output logic IReady,
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input logic InstrReadF,
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// input logic ResolveBranchD,
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output logic [`XLEN-1:0] InstrRData,
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// Signals from Data Cache
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input logic [`XLEN-1:0] MemPAdrM,
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input logic DReadM, DWriteM,
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input logic MemReadM, MemWriteM,
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input logic [`XLEN-1:0] WriteDataM,
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input logic [1:0] DSizeM,
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input logic [1:0] MemSizeM,
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// Return from bus
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output logic [`XLEN-1:0] DRData,
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// output logic DReady,
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output logic [`XLEN-1:0] ReadDataW,
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// AHB-Lite external signals
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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@ -59,48 +59,176 @@ module ahblite (
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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// Acknowledge
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output logic InstrAckD, MemAckW
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// Delayed signals for writes
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output logic [2:0] HADDRD,
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output logic [3:0] HSIZED,
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output logic HWRITED,
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// Stalls
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// output logic InstrStall, DataStall
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output logic InstrStall,/*InstrUpdate, */DataStall
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);
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logic GrantData;
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logic [2:0] ISize;
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logic [`AHBW-1:0] HRDATAMasked;
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logic [`AHBW-1:0] HRDATAMasked, ReadDataM, ReadDataPreW;
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logic IReady, DReady;
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logic CaptureDataM;
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// logic [3:0] HSIZED; // size delayed by one cycle for reads
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// logic [2:0] HADDRD; // address delayed for subword reads
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assign HCLK = clk;
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assign HRESETn = ~reset;
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// Arbitrate requests by giving data priority over instructions
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assign GrantData = DReadM | DWriteM;
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// *** initially support HABW = XLEN
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// track bus state
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// Data accesses have priority over instructions. However, if a data access comes
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// while an instruction read is occuring, the instruction read finishes before
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// the data access can take place.
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typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADMEMPENDING} statetype;
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statetype BusState, NextBusState;
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) BusState <= #1 IDLE;
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else BusState <= #1 NextBusState;
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always_comb
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case (BusState)
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IDLE: if (MemReadM) NextBusState = MEMREAD; // Memory has pirority over instructions
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else if (MemWriteM) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMREAD: if (~HREADY) NextBusState = MEMREAD;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMWRITE: if (~HREADY) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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INSTRREAD: //if (~HREADY & (MemReadM | MemWriteM)) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete
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if (~HREADY) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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INSTRREADMEMPENDING: if (~HREADY) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete
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else if (MemReadM) NextBusState = MEMREAD;
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else NextBusState = MEMWRITE; // must be write if not a read. Don't return to idle.
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endcase
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// stall signals
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assign #2 DataStall = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || (NextBusState == INSTRREADMEMPENDING);
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assign #1 InstrStall = (NextBusState == INSTRREAD);
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// assign InstrUpdate = (BusState == INSTRREADMEMPENDING) && (NextBusState != INSTRREADMEMPENDING);
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// DH 2/20/22: A cyclic path presently exists
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// HREADY->NextBusState->GrantData->HSIZE->HSELUART->HREADY
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// This is because the peripherals assert HREADY on the same cycle
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// When memory is working, also fix the peripherals to respond on the subsequent cycle
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// and this path should be fixed.
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// bus outputs
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assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
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assign #1 HADDR = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0];
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assign #1 HSIZE = GrantData ? {1'b0, MemSizeM} : ISize;
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assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
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assign HMASTLOCK = 0; // no locking supported
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assign HWRITE = (NextBusState == MEMWRITE);
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// delay write data by one cycle for
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flop #(`XLEN) wdreg(HCLK, WriteDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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// delay signals for subword writes
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flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
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flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
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flop #(1) writereg(HCLK, HWRITE, HWRITED);
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// Route signals to Instruction and Data Caches
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// *** assumes AHBW = XLEN
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// fix harris 2/24/21 to read all WLEN bits directly for instruction
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assign InstrRData = HRDATA;
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assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
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assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD);
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flopenr #(`XLEN) ReadDataPreWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataPreW); // *** this may break when there is no instruction read after data read
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flopenr #(`XLEN) ReadDataWReg(clk, reset, ~StallW, ReadDataPreW, ReadDataW);
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/*
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typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
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statetype AdrState, DataState, NextAdrState; // what is happening in the first and second phases of the bus
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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AdrState <= IDLE; DataState <= IDLE;
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HWDATA <= 0; // unnecessary but avoids x at startup
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HSIZED <= 0;
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HADDRD <= 0;
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HWRITED <= 0;
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end else begin
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if (HREADY || (DataState == IDLE)) begin // only advance bus state if bus is idle or previous transaction returns ready
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DataState <= AdrState;
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AdrState <= NextAdrState;
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if (HWRITE) HWDATA <= WriteDataM;
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HSIZED <= {UnsignedLoadM, HSIZE};
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HADDRD <= HADDR[2:0];
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HWRITED <= HWRITE;
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end
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end
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always_comb
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if (MemReadM) NextAdrState = MEMREAD;
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else if (MemWriteM) NextAdrState = MEMWRITE;
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else if (InstrReadF) NextAdrState = INSTRREAD;
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// else if (1) NextAdrState = INSTRREAD; // dm 2/9/2021 testing
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else NextAdrState = IDLE;
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// Generate acknowledges based on bus state and ready
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assign MemAckW = (AdrState == MEMREAD || AdrState == MEMWRITE) && HREADY;
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assign InstrAckD = (AdrState == INSTRREAD) && HREADY;
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// State machines for stalls (probably can merge with FSM above***)
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// Idle, DataBusy, InstrBusy. Stall while in busystate add suffixes
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logic MemState, NextMemState, InstrState, NextInstrState;
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flopr #(1) msreg(HCLK, ~HRESETn, NextMemState, MemState);
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flopr #(1) isreg(HCLK, ~HRESETn, NextInstrState, InstrState);
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/* always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) MemState <= 0;
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else MemState <= NextMemState;
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assign NextMemState = (MemState == 0 && InstrState == 0 && (MemReadM || MemWriteM)) || (MemState == 1 && ~MemAckW);
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assign DataStall = NextMemState;
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/* always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) InstrState <= 0;
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else InstrState <= NextInstrState;
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assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) ||
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(InstrState == 1 && ~InstrAckD) ||
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(InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later
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/* assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM)) ||
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(InstrState == 1 && ~InstrAckD); // *** removed InstrReadF above dh 2/9/20
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assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better
|
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// temporarily turn off stalls and check it works
|
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//assign DataStall = 0;
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//assign InstrStall = 0;
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assign DReady = HREADY & GrantData; // ***unused?
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assign IReady = HREADY & InstrReadF & ~GrantData; // maybe unused?***
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*/
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// Choose ISize based on XLen
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generate
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if (`AHBW == 32) assign ISize = 3'b010; // 32-bit transfers
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else assign ISize = 3'b011; // 64-bit transfers
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//if (`AHBW == 32) assign ISize = 3'b010; // 32-bit transfers
|
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//else assign ISize = 3'b011; // 64-bit transfers
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assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width
|
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endgenerate
|
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|
||||
/*
|
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// drive bus outputs
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assign HADDR = GrantData ? MemPAdrM[31:0] : InstrPAdrF[31:0];
|
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assign HWDATA = WriteDataM;
|
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//assign HWDATA = WriteDataW;
|
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//flop #(`XLEN) wdreg(HCLK, DWDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
|
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assign HWRITE = DWriteM;
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assign HSIZE = GrantData ? {1'b0, DSizeM} : ISize;
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assign HWRITE = MemWriteM;
|
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assign HSIZE = GrantData ? {1'b0, MemSizeM} : ISize;
|
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assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfHPROT
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assign HPROT = 4'b0011; // not used; see Section 3.7
|
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assign HTRANS = IReadF | DReadM | DWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
|
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assign HTRANS = InstrReadF | MemReadM | MemWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
|
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assign HMASTLOCK = 0; // no locking supported
|
||||
|
||||
// Route signals to Instruction and Data Caches
|
||||
// *** assumes AHBW = XLEN
|
||||
assign IRData = HRDATAMasked;
|
||||
assign IReady = HREADY & IReadF & ~GrantData; // maybe unused?***
|
||||
assign DRData = HRDATAMasked;
|
||||
assign DReady = HREADY & GrantData; // ***unused?
|
||||
*/
|
||||
|
||||
|
||||
// stalls
|
||||
// Stall MEM stage if data is being accessed and bus isn't yet ready
|
||||
|
||||
@ -28,9 +28,9 @@
|
||||
module subwordread (
|
||||
// from AHB Interface
|
||||
input logic [`XLEN-1:0] HRDATA,
|
||||
input logic [31:0] HADDR,
|
||||
input logic UnsignedLoadM,
|
||||
input logic [2:0] HSIZE,
|
||||
input logic [2:0] HADDRD,
|
||||
//input logic UnsignedLoadM,
|
||||
input logic [3:0] HSIZED,
|
||||
// to ifu/dmems
|
||||
output logic [`XLEN-1:0] HRDATAMasked
|
||||
);
|
||||
@ -42,7 +42,7 @@ module subwordread (
|
||||
if (`XLEN == 64) begin
|
||||
// ByteMe mux
|
||||
always_comb
|
||||
case(HADDR[2:0])
|
||||
case(HADDRD[2:0])
|
||||
3'b000: ByteM = HRDATA[7:0];
|
||||
3'b001: ByteM = HRDATA[15:8];
|
||||
3'b010: ByteM = HRDATA[23:16];
|
||||
@ -55,7 +55,7 @@ module subwordread (
|
||||
|
||||
// halfword mux
|
||||
always_comb
|
||||
case(HADDR[2:1])
|
||||
case(HADDRD[2:1])
|
||||
2'b00: HalfwordM = HRDATA[15:0];
|
||||
2'b01: HalfwordM = HRDATA[31:16];
|
||||
2'b10: HalfwordM = HRDATA[47:32];
|
||||
@ -65,14 +65,14 @@ module subwordread (
|
||||
logic [31:0] WordM;
|
||||
|
||||
always_comb
|
||||
case(HADDR[2])
|
||||
case(HADDRD[2])
|
||||
1'b0: WordM = HRDATA[31:0];
|
||||
1'b1: WordM = HRDATA[63:32];
|
||||
endcase
|
||||
|
||||
// sign extension
|
||||
always_comb
|
||||
case({UnsignedLoadM, HSIZE[1:0]})
|
||||
case({HSIZED[3], HSIZED[1:0]}) // HSIZED[3] indicates unsigned load
|
||||
3'b000: HRDATAMasked = {{56{ByteM[7]}}, ByteM}; // lb
|
||||
3'b001: HRDATAMasked = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
|
||||
3'b010: HRDATAMasked = {{32{WordM[31]}}, WordM[31:0]}; // lw
|
||||
@ -85,7 +85,7 @@ module subwordread (
|
||||
end else begin // 32-bit
|
||||
// byte mux
|
||||
always_comb
|
||||
case(HADDR[1:0])
|
||||
case(HADDRD[1:0])
|
||||
2'b00: ByteM = HRDATA[7:0];
|
||||
2'b01: ByteM = HRDATA[15:8];
|
||||
2'b10: ByteM = HRDATA[23:16];
|
||||
@ -94,14 +94,14 @@ module subwordread (
|
||||
|
||||
// halfword mux
|
||||
always_comb
|
||||
case(HADDR[1])
|
||||
case(HADDRD[1])
|
||||
1'b0: HalfwordM = HRDATA[15:0];
|
||||
1'b1: HalfwordM = HRDATA[31:16];
|
||||
endcase
|
||||
|
||||
// sign extension
|
||||
always_comb
|
||||
case({UnsignedLoadM, HSIZE[1:0]})
|
||||
case({HSIZED[3], HSIZED[1:0]})
|
||||
3'b000: HRDATAMasked = {{24{ByteM[7]}}, ByteM}; // lb
|
||||
3'b001: HRDATAMasked = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
|
||||
3'b010: HRDATAMasked = HRDATA; // lw
|
||||
|
||||
@ -47,6 +47,16 @@ module flopr #(parameter WIDTH = 8) (
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
// flop with enable
|
||||
module flopen #(parameter WIDTH = 8) (
|
||||
input logic clk, en,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (en) q <= #1 d;
|
||||
endmodule
|
||||
|
||||
// flop with enable, asynchronous reset, synchronous clear
|
||||
module flopenrc #(parameter WIDTH = 8) (
|
||||
input logic clk, reset, clear, en,
|
||||
|
||||
@ -34,12 +34,14 @@ module hazard(
|
||||
input logic LoadStallD, MulDivStallD,
|
||||
input logic InstrStall, DataStall,
|
||||
// Stall outputs
|
||||
output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW
|
||||
output logic StallF, StallD, StallE, StallM, StallW,
|
||||
output logic FlushD, FlushE, FlushM, FlushW
|
||||
);
|
||||
|
||||
logic BranchFlushDE;
|
||||
logic StallDCause, StallFCause, StallWCause;
|
||||
|
||||
logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
|
||||
logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
|
||||
|
||||
// stalls and flushes
|
||||
// loads: stall for one cycle if the subsequent instruction depends on the load
|
||||
// branches and jumps: flush the next two instructions if the branch is taken in EXE
|
||||
@ -54,14 +56,32 @@ module hazard(
|
||||
|
||||
assign BranchFlushDE = PCSrcE | RetM | TrapM;
|
||||
|
||||
assign StallDCause = LoadStallD | MulDivStallD;
|
||||
assign StallFCause = InstrStall | CSRWritePendingDEM;
|
||||
assign StallWCause = DataStall; // *** not yet used
|
||||
// changed 2/22/21 harris to turn off stallF when RetM or TrapM
|
||||
// changed 2/23/21 harris to BranchFlushDEM to solve bug in ECALL about JAL being ignored
|
||||
// assign StallFCause = /*InstrStall | */ CSRWritePendingDEM; // stall at fetch if unable to get the instruction,
|
||||
// assign StallFCause = /*InstrStall | */ CSRWritePendingDEM & ~(RetM | TrapM); // stall at fetch if unable to get the instruction,
|
||||
assign StallFCause = /*InstrStall | */ CSRWritePendingDEM & ~(BranchFlushDE); // stall at fetch if unable to get the instruction,
|
||||
// or if a CSR will be written and may change system behavior
|
||||
assign StallDCause = LoadStallD | MulDivStallD; // stall in decode if instruction is a load dependent on previous
|
||||
assign StallECause = 0;
|
||||
assign StallMCause = 0; // sDataStall; // not yet used***
|
||||
assign StallWCause = DataStall | InstrStall;
|
||||
|
||||
assign StallD = StallDCause;
|
||||
// Each stage stalls if the next stage is stalled or there is a cause to stall this stage.
|
||||
assign StallF = StallD | StallFCause;
|
||||
assign FlushD = BranchFlushDE | StallFCause; // PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM;
|
||||
assign FlushE = StallD | BranchFlushDE; //LoadStallD | PCSrcE | RetM | TrapM;
|
||||
assign FlushM = RetM | TrapM;
|
||||
assign FlushW = TrapM;
|
||||
assign StallD = StallE | StallDCause;
|
||||
assign StallE = StallM | StallECause;
|
||||
assign StallM = StallW | StallMCause;
|
||||
assign StallW = StallWCause;
|
||||
|
||||
assign FirstUnstalledD = (~StallD & StallF);
|
||||
assign FirstUnstalledE = (~StallE & StallD);
|
||||
assign FirstUnstalledM = (~StallM & StallE);
|
||||
assign FirstUnstalledW = (~StallW & StallM);;
|
||||
|
||||
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
|
||||
assign FlushD = FirstUnstalledD || BranchFlushDE; // PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM;
|
||||
assign FlushE = FirstUnstalledE || BranchFlushDE; //LoadStallD | PCSrcE | RetM | TrapM;
|
||||
assign FlushM = FirstUnstalledM || RetM || TrapM;
|
||||
assign FlushW = FirstUnstalledW | TrapM;
|
||||
endmodule
|
||||
|
||||
@ -37,8 +37,8 @@ module controller(
|
||||
input logic IllegalIEUInstrFaultD,
|
||||
output logic IllegalBaseInstrFaultD,
|
||||
// Execute stage control signals
|
||||
input logic FlushE,
|
||||
input logic [2:0] FlagsE,
|
||||
input logic StallE, FlushE,
|
||||
input logic [2:0] FlagsE,
|
||||
output logic PCSrcE, // for datapath and Hazard Unit
|
||||
output logic [4:0] ALUControlE,
|
||||
output logic ALUSrcAE, ALUSrcBE,
|
||||
@ -47,14 +47,14 @@ module controller(
|
||||
output logic [2:0] Funct3E,
|
||||
output logic MulDivE, W64E,
|
||||
// Memory stage control signals
|
||||
input logic FlushM,
|
||||
input logic StallM, FlushM,
|
||||
input logic DataMisalignedM,
|
||||
output logic [1:0] MemRWM,
|
||||
output logic CSRWriteM, PrivilegedM,
|
||||
output logic [2:0] Funct3M,
|
||||
output logic RegWriteM, // for Hazard Unit
|
||||
// Writeback stage control signals
|
||||
input logic FlushW,
|
||||
input logic StallW, FlushW,
|
||||
output logic RegWriteW, // for datapath and Hazard Unit
|
||||
output logic [2:0] ResultSrcW,
|
||||
output logic InstrValidW,
|
||||
@ -145,7 +145,7 @@ module controller(
|
||||
endcase
|
||||
|
||||
// Execute stage pipeline control register and logic
|
||||
floprc #(24) controlregE(clk, reset, FlushE,
|
||||
flopenrc #(24) controlregE(clk, reset, FlushE, ~StallE,
|
||||
{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, 1'b1},
|
||||
{RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, InstrValidE});
|
||||
|
||||
@ -168,12 +168,12 @@ module controller(
|
||||
assign MemReadE = MemRWE[1];
|
||||
|
||||
// Memory stage pipeline control register
|
||||
floprc #(12) controlregM(clk, reset, FlushM,
|
||||
flopenrc #(12) controlregM(clk, reset, FlushM, ~StallM,
|
||||
{RegWriteE, ResultSrcE, MemRWE, CSRWriteE, PrivilegedE, Funct3E, InstrValidE},
|
||||
{RegWriteM, ResultSrcM, MemRWM, CSRWriteM, PrivilegedM, Funct3M, InstrValidM});
|
||||
|
||||
// Writeback stage pipeline control register
|
||||
floprc #(5) controlregW(clk, reset, FlushW,
|
||||
flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
|
||||
{RegWriteM, ResultSrcM, InstrValidM},
|
||||
{RegWriteW, ResultSrcW, InstrValidW});
|
||||
|
||||
|
||||
@ -32,7 +32,7 @@ module datapath (
|
||||
input logic [2:0] ImmSrcD,
|
||||
input logic [31:0] InstrD,
|
||||
// Execute stage signals
|
||||
input logic FlushE,
|
||||
input logic StallE, FlushE,
|
||||
input logic [1:0] ForwardAE, ForwardBE,
|
||||
input logic PCSrcE,
|
||||
input logic [4:0] ALUControlE,
|
||||
@ -43,13 +43,13 @@ module datapath (
|
||||
output logic [`XLEN-1:0] PCTargetE,
|
||||
output logic [`XLEN-1:0] SrcAE, SrcBE,
|
||||
// Memory stage signals
|
||||
input logic FlushM,
|
||||
input logic StallM, FlushM,
|
||||
input logic [2:0] Funct3M,
|
||||
input logic RetM, TrapM,
|
||||
output logic [`XLEN-1:0] SrcAM,
|
||||
output logic [`XLEN-1:0] WriteDataM, MemAdrM,
|
||||
// Writeback stage signals
|
||||
input logic FlushW,
|
||||
input logic StallW, FlushW,
|
||||
input logic RegWriteW,
|
||||
input logic [2:0] ResultSrcW,
|
||||
input logic [`XLEN-1:0] PCLinkW,
|
||||
@ -85,12 +85,12 @@ module datapath (
|
||||
extend ext(.InstrD(InstrD[31:7]), .*);
|
||||
|
||||
// Execute stage pipeline register and logic
|
||||
floprc #(`XLEN) RD1EReg(clk, reset, FlushE, RD1D, RD1E);
|
||||
floprc #(`XLEN) RD2EReg(clk, reset, FlushE, RD2D, RD2E);
|
||||
floprc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ExtImmD, ExtImmE);
|
||||
floprc #(5) Rs1EReg(clk, reset, FlushE, Rs1D, Rs1E);
|
||||
floprc #(5) Rs2EReg(clk, reset, FlushE, Rs2D, Rs2E);
|
||||
floprc #(5) RdEReg(clk, reset, FlushE, RdD, RdE);
|
||||
flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, RD1D, RD1E);
|
||||
flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, RD2D, RD2E);
|
||||
flopenrc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ~StallE, ExtImmD, ExtImmE);
|
||||
flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
|
||||
flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
|
||||
flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
|
||||
|
||||
mux3 #(`XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE);
|
||||
mux3 #(`XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE);
|
||||
@ -101,15 +101,15 @@ module datapath (
|
||||
assign PCTargetE = ExtImmE + TargetBaseE;
|
||||
|
||||
// Memory stage pipeline register
|
||||
floprc #(`XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM);
|
||||
floprc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM);
|
||||
flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
|
||||
flopenrc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ~StallM, ALUResultE, ALUResultM);
|
||||
assign MemAdrM = ALUResultM;
|
||||
floprc #(`XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataM);
|
||||
floprc #(5) RdMEg(clk, reset, FlushM, RdE, RdM);
|
||||
flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
|
||||
flopenrc #(5) RdMEg(clk, reset, FlushM, ~StallM, RdE, RdM);
|
||||
|
||||
// Writeback stage pipeline register and logic
|
||||
floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
|
||||
floprc #(5) RdWEg(clk, reset, FlushW, RdM, RdW);
|
||||
flopenrc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ~StallW, ALUResultM, ALUResultW);
|
||||
flopenrc #(5) RdWEg(clk, reset, FlushW, ~StallW, RdM, RdW);
|
||||
|
||||
mux5 #(`XLEN) resultmux(ALUResultW, ReadDataW, PCLinkW, CSRReadValW, MulDivResultW, ResultSrcW, ResultW);
|
||||
endmodule
|
||||
|
||||
@ -30,7 +30,7 @@ module forward(
|
||||
input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
|
||||
input logic MemReadE, MulDivE,
|
||||
input logic RegWriteM, RegWriteW,
|
||||
// Forwaring controls
|
||||
// Forwarding controls
|
||||
output logic [1:0] ForwardAE, ForwardBE,
|
||||
output logic LoadStallD, MulDivStallD
|
||||
);
|
||||
|
||||
@ -49,7 +49,8 @@ module ieu (
|
||||
input logic [`XLEN-1:0] PCLinkW,
|
||||
output logic InstrValidW,
|
||||
// hazards
|
||||
input logic StallD, FlushD, FlushE, FlushM, FlushW,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
input logic RetM, TrapM,
|
||||
output logic LoadStallD, MulDivStallD,
|
||||
output logic PCSrcE,
|
||||
|
||||
@ -28,13 +28,16 @@
|
||||
|
||||
module ifu (
|
||||
input logic clk, reset,
|
||||
input logic StallF, StallD, FlushD, FlushE, FlushM, FlushW,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// Fetch
|
||||
input logic [31:0] InstrF,
|
||||
input logic [`XLEN-1:0] InstrInF,
|
||||
output logic [`XLEN-1:0] PCF,
|
||||
output logic [`XLEN-1:0] InstrPAdrF,
|
||||
output logic InstrReadF,
|
||||
// Decode
|
||||
output logic InstrStall,
|
||||
//output logic InstrStall,
|
||||
output logic ResolveBranchD,
|
||||
// Execute
|
||||
input logic PCSrcE,
|
||||
input logic [`XLEN-1:0] PCTargetE,
|
||||
@ -50,7 +53,9 @@ module ifu (
|
||||
input logic IllegalBaseInstrFaultD,
|
||||
output logic IllegalIEUInstrFaultD,
|
||||
output logic InstrMisalignedFaultM,
|
||||
output logic [`XLEN-1:0] InstrMisalignedAdrM
|
||||
output logic [`XLEN-1:0] InstrMisalignedAdrM,
|
||||
// bogus
|
||||
input logic [15:0] rd2
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] UnalignedPCNextF, PCNextF;
|
||||
@ -59,20 +64,25 @@ module ifu (
|
||||
logic IllegalCompInstrD;
|
||||
logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM;
|
||||
logic CompressedF;
|
||||
logic [31:0] InstrRawD, InstrE;
|
||||
logic [31:0] InstrF, InstrRawD, InstrE, InstrW;
|
||||
logic [31:0] nop = 32'h00000013; // instruction for NOP
|
||||
|
||||
// *** put memory interface on here, InstrF becomes output
|
||||
assign InstrStall = 0; // ***
|
||||
assign InstrPAdrF = PCF; // *** no MMU
|
||||
//assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
|
||||
assign InstrReadF = 1; // *** & ICacheMissF; add later
|
||||
|
||||
assign PrivilegedChangePCM = RetM | TrapM;
|
||||
|
||||
assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM);
|
||||
//assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM);
|
||||
|
||||
// dh 2/8/2022 keep in instruction fetch stall mode when taking branch
|
||||
//flopr #(1) rbreg(clk, reset, (PCSrcE | PrivilegedChangePCM), ResolveBranchD);
|
||||
|
||||
mux3 #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF);
|
||||
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
|
||||
flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF);
|
||||
// flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF);
|
||||
flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
|
||||
|
||||
// pcadder
|
||||
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
|
||||
@ -86,6 +96,15 @@ module ifu (
|
||||
else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
|
||||
else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
|
||||
|
||||
// harris 2/23/21 Add code to fetch instruction split across two words
|
||||
generate
|
||||
if (`XLEN==32) begin
|
||||
assign InstrF = PCF[1] ? {rd2[15:0], InstrInF[31:16]} : InstrInF;
|
||||
end else begin
|
||||
assign InstrF = PCF[2] ? (PCF[1] ? {rd2[15:0], InstrInF[63:48]} : InstrInF[63:32])
|
||||
: (PCF[1] ? InstrInF[47:16] : InstrInF[31:0]);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Decode stage pipeline register and logic
|
||||
flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrRawD);
|
||||
@ -107,25 +126,26 @@ module ifu (
|
||||
|
||||
// pipeline misaligned faults to M stage
|
||||
assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned
|
||||
flopr #(1) InstrMisalginedReg(clk, reset, BranchMisalignedFaultE, BranchMisalignedFaultM);
|
||||
flopr #(`XLEN) InstrMisalignedAdrReg(clk, reset, PCNextF, InstrMisalignedAdrM);
|
||||
flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, BranchMisalignedFaultM);
|
||||
flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
|
||||
assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM;
|
||||
assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path
|
||||
|
||||
flopr #(32) InstrEReg(clk, reset, FlushE ? nop : InstrD, InstrE);
|
||||
flopr #(32) InstrMReg(clk, reset, FlushM ? nop : InstrE, InstrM);
|
||||
flopr #(`XLEN) PCEReg(clk, reset, PCD, PCE);
|
||||
flopr #(`XLEN) PCMReg(clk, reset, PCE, PCM);
|
||||
flopr #(`XLEN) PCWReg(clk, reset, PCM, PCW); // *** probably not needed; delete later
|
||||
flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE);
|
||||
flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM);
|
||||
flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later
|
||||
flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
|
||||
flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later
|
||||
|
||||
// seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL.
|
||||
// either have ALU compute PC+2/4 and feed into ALUResult input of ResultMux or
|
||||
// have dedicated adder in Mem stage based on PCM + 2 or 4
|
||||
// *** redo this
|
||||
flopr #(`XLEN) PCPDReg(clk, reset, PCPlus2or4F, PCLinkD);
|
||||
flopr #(`XLEN) PCPEReg(clk, reset, PCLinkD, PCLinkE);
|
||||
flopr #(`XLEN) PCPMReg(clk, reset, PCLinkE, PCLinkM);
|
||||
flopr #(`XLEN) PCPWReg(clk, reset, PCLinkM, PCLinkW);
|
||||
flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
|
||||
flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
|
||||
flopenr #(`XLEN) PCPMReg(clk, reset, ~StallM, PCLinkE, PCLinkM);
|
||||
flopenr #(`XLEN) PCPWReg(clk, reset, ~StallW, PCLinkM, PCLinkW);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
|
||||
module csr (
|
||||
input logic clk, reset,
|
||||
input logic FlushW,
|
||||
input logic FlushW, StallW,
|
||||
input logic [31:0] InstrM,
|
||||
input logic [`XLEN-1:0] PCM, SrcAM,
|
||||
input logic CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
|
||||
@ -102,7 +102,9 @@ module csr (
|
||||
|
||||
// merge CSR Reads
|
||||
assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM;
|
||||
floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRReadValW);
|
||||
// *** add W stall 2/22/21 dh to try fixing memory stalls
|
||||
// floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRReadValW);
|
||||
flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
|
||||
|
||||
// merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
|
||||
assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 && PrivilegeModeW != `M_MODE) ||
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module csrsr (
|
||||
input logic clk, reset,
|
||||
input logic clk, reset, StallW,
|
||||
input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM,
|
||||
input logic TrapM, FloatRegWriteW,
|
||||
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
|
||||
@ -118,7 +118,7 @@ module csrsr (
|
||||
STATUS_MIE <= 0; // Per Priv 3.3
|
||||
STATUS_SIE <= `S_SUPPORTED;
|
||||
STATUS_UIE <= `U_SUPPORTED;
|
||||
end else begin
|
||||
end else if (~StallW) begin
|
||||
if (WriteMSTATUSM) begin
|
||||
STATUS_SUM_INT <= CSRWriteValM[18];
|
||||
STATUS_MPRV_INT <= CSRWriteValM[17];
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
///////////////////////////////////////////
|
||||
// exceptions.sv
|
||||
// privileged.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 5 January 2021
|
||||
// Modified:
|
||||
@ -45,7 +45,7 @@ module privileged (
|
||||
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
|
||||
input logic [4:0] SetFflagsM,
|
||||
output logic [2:0] FRM_REGW,
|
||||
input logic FlushD, FlushE, FlushM, StallD
|
||||
input logic FlushD, FlushE, FlushM, StallD, StallW
|
||||
);
|
||||
|
||||
logic [1:0] NextPrivilegeModeM, PrivilegeModeW;
|
||||
@ -81,8 +81,8 @@ module privileged (
|
||||
|
||||
// PrivilegeMode FSM
|
||||
always_comb
|
||||
if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode)
|
||||
else if (mretM) NextPrivilegeModeM = STATUS_MPP;
|
||||
/* if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode) // moved reset to flop
|
||||
else */ if (mretM) NextPrivilegeModeM = STATUS_MPP;
|
||||
else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
|
||||
else if (uretM) NextPrivilegeModeM = `U_MODE;
|
||||
else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
|
||||
@ -96,7 +96,7 @@ module privileged (
|
||||
else NextPrivilegeModeM = `M_MODE;
|
||||
end else NextPrivilegeModeM = PrivilegeModeW;
|
||||
|
||||
flop #(2) privmodereg(clk, NextPrivilegeModeM, PrivilegeModeW);
|
||||
flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
|
||||
|
||||
///////////////////////////////////////////
|
||||
// decode privileged instructions
|
||||
|
||||
@ -54,6 +54,11 @@ module clint (
|
||||
assign #2 entry = {HADDR[15:2], 2'b00};
|
||||
endgenerate
|
||||
|
||||
// DH 2/20/21: Eventually allow MTIME to run off a separate clock
|
||||
// This will require synchronizing MTIME to the system clock
|
||||
// before it is read or compared to MTIMECMP.
|
||||
// It will also require synchronizing the write to MTIMECMP.
|
||||
// Use req and ack signals synchronized across the clock domains.
|
||||
|
||||
// register access
|
||||
generate
|
||||
|
||||
@ -36,6 +36,9 @@ module dtim (
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] RAM[0:65535];
|
||||
logic [18:0] HWADDR;
|
||||
logic [`XLEN-1:0] HREADTim0;
|
||||
|
||||
// logic [`XLEN-1:0] write;
|
||||
logic [15:0] entry;
|
||||
logic memread, memwrite;
|
||||
@ -48,74 +51,56 @@ module dtim (
|
||||
end else begin
|
||||
if (HREADYTim & HSELTim) begin
|
||||
busycount <= 0;
|
||||
HREADYTim <= 0;
|
||||
HREADYTim <= #1 0;
|
||||
end else if (~HREADYTim) begin
|
||||
if (busycount == 0) begin // TIM latency, for testing purposes
|
||||
HREADYTim <= 1;
|
||||
end else
|
||||
if (busycount == 2) begin // TIM latency, for testing purposes
|
||||
HREADYTim <= #1 1;
|
||||
end else begin
|
||||
busycount <= busycount + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/* always_ff @(posedge HCLK, negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
HREADYTim <= 0;
|
||||
end else begin
|
||||
HREADYTim <= HSELTim; // always respond one cycle later
|
||||
end */
|
||||
|
||||
|
||||
assign memread = MemRWtim[1];
|
||||
assign memwrite = MemRWtim[0];
|
||||
// always_ff @(posedge HCLK)
|
||||
// memwrite <= MemRWtim[0]; // delay memwrite to write phase
|
||||
assign HRESPTim = 0; // OK
|
||||
// assign HREADYTim = 1; // Respond immediately; *** extend this
|
||||
|
||||
|
||||
// Model memory read and write
|
||||
|
||||
// word aligned reads
|
||||
generate
|
||||
if (`XLEN==64)
|
||||
assign #2 entry = HADDR[18:3];
|
||||
else
|
||||
assign #2 entry = HADDR[17:2];
|
||||
endgenerate
|
||||
assign HREADTim = RAM[entry];
|
||||
// assign HREADTim = HREADYTim ? RAM[entry] : ~RAM[entry]; // *** temproary mess up read value before ready
|
||||
|
||||
// write each byte based on the byte mask
|
||||
// UInstantiate a byte-writable memory here if possible
|
||||
// and drop tihs masking logic. Otherwise, use the masking
|
||||
// from dmem
|
||||
/*generate
|
||||
|
||||
if (`XLEN==64) begin
|
||||
always_comb begin
|
||||
write=HREADTim;
|
||||
if (ByteMaskM[0]) write[7:0] = HWDATA[7:0];
|
||||
if (ByteMaskM[1]) write[15:8] = HWDATA[15:8];
|
||||
if (ByteMaskM[2]) write[23:16] = HWDATA[23:16];
|
||||
if (ByteMaskM[3]) write[31:24] = HWDATA[31:24];
|
||||
if (ByteMaskM[4]) write[39:32] = HWDATA[39:32];
|
||||
if (ByteMaskM[5]) write[47:40] = HWDATA[47:40];
|
||||
if (ByteMaskM[6]) write[55:48] = HWDATA[55:48];
|
||||
if (ByteMaskM[7]) write[63:56] = HWDATA[63:56];
|
||||
end
|
||||
always_ff @(posedge clk)
|
||||
if (memwrite) RAM[HADDR[18:3]] <= write;
|
||||
end else begin // 32-bit
|
||||
always_comb begin
|
||||
write=HREADTim;
|
||||
if (ByteMaskM[0]) write[7:0] = HWDATA[7:0];
|
||||
if (ByteMaskM[1]) write[15:8] = HWDATA[15:8];
|
||||
if (ByteMaskM[2]) write[23:16] = HWDATA[23:16];
|
||||
if (ByteMaskM[3]) write[31:24] = HWDATA[31:24];
|
||||
end
|
||||
always_ff @(posedge clk)
|
||||
if (memwrite) RAM[HADDR[17:2]] <= write;
|
||||
if (`XLEN == 64) begin
|
||||
// always_ff @(negedge HCLK)
|
||||
// if (memwrite) RAM[HWADDR[17:3]] <= HWDATA;
|
||||
always_ff @(posedge HCLK) begin
|
||||
//if (memwrite) RAM[HADDR[17:3]] <= HWDATA;
|
||||
HWADDR <= HADDR;
|
||||
HREADTim0 <= RAM[HADDR[17:3]];
|
||||
if (memwrite && HREADYTim) RAM[HWADDR[17:3]] <= HWDATA;
|
||||
end
|
||||
end else begin
|
||||
// always_ff @(negedge HCLK)
|
||||
// if (memwrite) RAM[HWADDR[17:2]] <= HWDATA;
|
||||
always_ff @(posedge HCLK) begin
|
||||
//if (memwrite) RAM[HADDR[17:2]] <= HWDATA;
|
||||
HWADDR <= HADDR;
|
||||
HREADTim0 <= RAM[HADDR[17:2]];
|
||||
if (memwrite && HREADYTim) RAM[HWADDR[17:2]] <= HWDATA;
|
||||
end
|
||||
end
|
||||
endgenerate */
|
||||
generate
|
||||
if (`XLEN == 64)
|
||||
always_ff @(posedge HCLK) begin
|
||||
if (memwrite) RAM[HADDR[17:3]] <= HWDATA;
|
||||
// HREADTim <= RAM[HADDR[17:3]];
|
||||
end
|
||||
else
|
||||
always_ff @(posedge HCLK) begin
|
||||
if (memwrite) RAM[HADDR[17:2]] <= HWDATA;
|
||||
// HREADTim <= RAM[HADDR[17:2]];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign HREADTim = HREADYTim ? HREADTim0 : 'bz;
|
||||
endmodule
|
||||
|
||||
|
||||
@ -28,6 +28,7 @@
|
||||
module imem (
|
||||
input logic [`XLEN-1:1] AdrF,
|
||||
output logic [31:0] InstrF,
|
||||
output logic [15:0] rd2, // bogus, delete when real multicycle fetch works
|
||||
output logic InstrAccessFaultF);
|
||||
|
||||
/* verilator lint_off UNDRIVEN */
|
||||
@ -35,7 +36,7 @@ module imem (
|
||||
/* verilator lint_on UNDRIVEN */
|
||||
logic [15:0] adrbits;
|
||||
logic [`XLEN-1:0] rd;
|
||||
logic [15:0] rd2;
|
||||
// logic [15:0] rd2;
|
||||
|
||||
generate
|
||||
if (`XLEN==32) assign adrbits = AdrF[17:2];
|
||||
|
||||
@ -27,37 +27,35 @@
|
||||
|
||||
module subwordwrite (
|
||||
input logic [`XLEN-1:0] HRDATA,
|
||||
input logic [31:0] HADDR,
|
||||
input logic [2:0] HSIZE,
|
||||
input logic [2:0] HADDRD,
|
||||
input logic [3:0] HSIZED,
|
||||
input logic [`XLEN-1:0] HWDATAIN,
|
||||
output logic [`XLEN-1:0] HWDATA
|
||||
);
|
||||
|
||||
logic [7:0] ByteM; // *** declare locally to generate as either 4 or 8 bits
|
||||
logic [15:0] HalfwordM;
|
||||
logic [`XLEN-1:0] WriteDataSubwordDuplicated;
|
||||
logic [7:0] ByteMaskM;
|
||||
|
||||
generate
|
||||
if (`XLEN == 64) begin
|
||||
logic [7:0] ByteMaskM;
|
||||
// Compute write mask
|
||||
always_comb
|
||||
case(HSIZE[1:0])
|
||||
2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[HADDR[2:0]] = 1; end // sb
|
||||
2'b01: case (HADDR[2:1])
|
||||
case(HSIZED[1:0])
|
||||
2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[HADDRD[2:0]] = 1; end // sb
|
||||
2'b01: case (HADDRD[2:1])
|
||||
2'b00: ByteMaskM = 8'b00000011;
|
||||
2'b01: ByteMaskM = 8'b00001100;
|
||||
2'b10: ByteMaskM = 8'b00110000;
|
||||
2'b11: ByteMaskM = 8'b11000000;
|
||||
endcase
|
||||
2'b10: if (HADDR[2]) ByteMaskM = 8'b11110000;
|
||||
2'b10: if (HADDRD[2]) ByteMaskM = 8'b11110000;
|
||||
else ByteMaskM = 8'b00001111;
|
||||
2'b11: ByteMaskM = 8'b11111111;
|
||||
endcase
|
||||
|
||||
// Handle subword writes
|
||||
always_comb
|
||||
case(HSIZE[1:0])
|
||||
case(HSIZED[1:0])
|
||||
2'b00: WriteDataSubwordDuplicated = {8{HWDATAIN[7:0]}}; // sb
|
||||
2'b01: WriteDataSubwordDuplicated = {4{HWDATAIN[15:0]}}; // sh
|
||||
2'b10: WriteDataSubwordDuplicated = {2{HWDATAIN[31:0]}}; // sw
|
||||
@ -77,19 +75,20 @@ module subwordwrite (
|
||||
end
|
||||
|
||||
end else begin // 32-bit
|
||||
logic [3:0] ByteMaskM;
|
||||
// Compute write mask
|
||||
always_comb
|
||||
case(HSIZE[1:0])
|
||||
2'b00: begin ByteMaskM = 8'b0000; ByteMaskM[{1'b0, HADDR[1:0]}] = 1; end // sb
|
||||
2'b01: if (HADDR[1]) ByteMaskM = 8'b1100;
|
||||
else ByteMaskM = 8'b0011;
|
||||
2'b10: ByteMaskM = 8'b1111;
|
||||
default: ByteMaskM = 8'b111; // shouldn't happen
|
||||
case(HSIZED[1:0])
|
||||
2'b00: begin ByteMaskM = 4'b0000; ByteMaskM[HADDRD[1:0]] = 1; end // sb
|
||||
2'b01: if (HADDRD[1]) ByteMaskM = 4'b1100;
|
||||
else ByteMaskM = 4'b0011;
|
||||
2'b10: ByteMaskM = 4'b1111;
|
||||
default: ByteMaskM = 4'b111; // shouldn't happen
|
||||
endcase
|
||||
|
||||
// Handle subword writes
|
||||
always_comb
|
||||
case(HSIZE[1:0])
|
||||
case(HSIZED[1:0])
|
||||
2'b00: WriteDataSubwordDuplicated = {4{HWDATAIN[7:0]}}; // sb
|
||||
2'b01: WriteDataSubwordDuplicated = {2{HWDATAIN[15:0]}}; // sh
|
||||
2'b10: WriteDataSubwordDuplicated = HWDATAIN; // sw
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
//
|
||||
// Purpose: Universial Asynchronous Receiver/ Transmitter with FIFOs
|
||||
// Emulates interface of Texas Instruments PC16550D
|
||||
// https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/PC16550D.pdf
|
||||
// Compatible with UART in Imperas Virtio model ***
|
||||
//
|
||||
// Compatible with most of PC16550D with the following known exceptions:
|
||||
|
||||
@ -43,6 +43,10 @@ module uncore (
|
||||
input logic HREADYEXT, HRESPEXT,
|
||||
output logic [`AHBW-1:0] HRDATA,
|
||||
output logic HREADY, HRESP,
|
||||
// delayed signals
|
||||
input logic [2:0] HADDRD,
|
||||
input logic [3:0] HSIZED,
|
||||
input logic HWRITED,
|
||||
// bus interface
|
||||
output logic DataAccessFaultM,
|
||||
// peripheral pins
|
||||
@ -71,7 +75,7 @@ module uncore (
|
||||
assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported
|
||||
|
||||
// Enable read or write based on decoded address
|
||||
assign MemRW = {~HWRITE, HWRITE};
|
||||
assign MemRW = {~HWRITE, HWRITED};
|
||||
assign MemRWtim = MemRW & {2{HSELTim}};
|
||||
assign MemRWclint = MemRW & {2{HSELCLINT}};
|
||||
assign MemRWgpio = MemRW & {2{HSELGPIO}};
|
||||
|
||||
@ -29,12 +29,13 @@
|
||||
module wallypipelinedhart (
|
||||
input logic clk, reset,
|
||||
output logic [`XLEN-1:0] PCF,
|
||||
input logic [31:0] InstrF,
|
||||
// input logic [31:0] InstrF,
|
||||
// Privileged
|
||||
input logic TimerIntM, ExtIntM, SwIntM,
|
||||
input logic InstrAccessFaultF,
|
||||
input logic DataAccessFaultM,
|
||||
// Bus Interface
|
||||
input logic [15:0] rd2, // bogus, delete when real multicycle fetch works
|
||||
input logic [`AHBW-1:0] HRDATA,
|
||||
input logic HREADY, HRESP,
|
||||
output logic HCLK, HRESETn,
|
||||
@ -45,11 +46,16 @@ module wallypipelinedhart (
|
||||
output logic [2:0] HBURST,
|
||||
output logic [3:0] HPROT,
|
||||
output logic [1:0] HTRANS,
|
||||
output logic HMASTLOCK
|
||||
output logic HMASTLOCK,
|
||||
// Delayed signals for subword write
|
||||
output logic [2:0] HADDRD,
|
||||
output logic [3:0] HSIZED,
|
||||
output logic HWRITED
|
||||
);
|
||||
|
||||
logic [1:0] ForwardAE, ForwardBE;
|
||||
logic StallF, StallD, FlushD, FlushE, FlushM, FlushW;
|
||||
// logic [1:0] ForwardAE, ForwardBE;
|
||||
logic StallF, StallD, StallE, StallM, StallW;
|
||||
logic FlushD, FlushE, FlushM, FlushW;
|
||||
logic RetM, TrapM;
|
||||
|
||||
// new signals that must connect through DP
|
||||
@ -73,6 +79,7 @@ module wallypipelinedhart (
|
||||
logic StoreMisalignedFaultM, StoreAccessFaultM;
|
||||
logic [`XLEN-1:0] InstrMisalignedAdrM;
|
||||
logic [`XLEN-1:0] zero = 0;
|
||||
logic ResolveBranchD;
|
||||
|
||||
logic PCSrcE;
|
||||
logic CSRWritePendingDEM;
|
||||
@ -82,26 +89,35 @@ module wallypipelinedhart (
|
||||
logic FloatRegWriteW;
|
||||
|
||||
// bus interface to dmem
|
||||
logic [1:0] MemRWAlignedM;
|
||||
logic [2:0] Funct3M;
|
||||
logic MemReadM, MemWriteM;
|
||||
logic [2:0] Funct3M;
|
||||
logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM;
|
||||
logic [`XLEN-1:0] ReadDataM, ReadDataW;
|
||||
logic [`XLEN-1:0] ReadDataW;
|
||||
logic [`XLEN-1:0] InstrPAdrF;
|
||||
logic [`XLEN-1:0] InstrRData;
|
||||
logic InstrReadF;
|
||||
logic DataStall, InstrStall;
|
||||
logic InstrAckD, MemAckW;
|
||||
|
||||
ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
|
||||
ifu ifu(.InstrInF(InstrRData), .*); // instruction fetch unit: PC, branch prediction, instruction cache
|
||||
|
||||
ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
|
||||
dmem dmem(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
|
||||
dmem dmem(.*); // data cache unit
|
||||
|
||||
ahblite ebu( // *** make IRData InstrF
|
||||
.IReadF(1'b1), .IRData(), //.IReady(),
|
||||
.DReadM(MemRWAlignedM[1]), .DWriteM(MemRWAlignedM[0]),
|
||||
.DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(),
|
||||
.UnsignedLoadM(Funct3M[2]),
|
||||
|
||||
ahblite ebu(
|
||||
//.InstrReadF(1'b0),
|
||||
//.InstrRData(InstrF), // hook up InstrF later
|
||||
.MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
|
||||
.*);
|
||||
//assign InstrF = ReadDataM[31:0];
|
||||
|
||||
// changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed.
|
||||
// Would need to insertinstruction as InstrD, not InstrF
|
||||
/*ahblite ebu(
|
||||
.InstrReadF(1'b0),
|
||||
.InstrRData(), // hook up InstrF later
|
||||
.MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
|
||||
.*); */
|
||||
|
||||
|
||||
muldiv mdu(.*); // multiply and divide unit
|
||||
|
||||
@ -64,6 +64,10 @@ module wallypipelinedsoc (
|
||||
logic InstrAccessFaultF, DataAccessFaultM;
|
||||
logic TimerIntM, SwIntM; // from CLINT
|
||||
logic ExtIntM = 0; // not yet connected
|
||||
logic [2:0] HADDRD;
|
||||
logic [3:0] HSIZED;
|
||||
logic HWRITED;
|
||||
logic [15:0] rd2; // bogus, delete when real multicycle fetch works
|
||||
|
||||
// instantiate processor and memories
|
||||
wallypipelinedhart hart(.*);
|
||||
|
||||
@ -35,7 +35,7 @@ module testbench();
|
||||
logic [`XLEN-1:0] signature[0:10000];
|
||||
logic [`XLEN-1:0] testadr;
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
logic [31:0] InstrW;
|
||||
//logic [31:0] InstrW;
|
||||
logic [`XLEN-1:0] meminit;
|
||||
string tests64m[] = '{
|
||||
"rv64m/I-MUL-01", "3000",
|
||||
@ -90,7 +90,6 @@ string tests64iNOc[] = {
|
||||
"rv64i/I-MISALIGN_JMP-01","2000"
|
||||
};
|
||||
string tests64i[] = '{
|
||||
"rv64i/I-LW-01", "4110",
|
||||
"rv64i/I-ADD-01", "3000",
|
||||
"rv64i/I-ADDI-01", "3000",
|
||||
"rv64i/I-ADDIW-01", "3000",
|
||||
@ -198,7 +197,6 @@ string tests64iNOc[] = {
|
||||
// "rv32m/I-REMU-01", "2000"
|
||||
};
|
||||
string tests32ic[] = '{
|
||||
// "rv32ic/WALLY-C-ADHOC-01", "2000",
|
||||
"rv32ic/I-C-ADD-01", "2000",
|
||||
"rv32ic/I-C-ADDI-01", "2000",
|
||||
"rv32ic/I-C-AND-01", "2000",
|
||||
@ -347,9 +345,9 @@ string tests32i[] = {
|
||||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// initialize tests
|
||||
initial
|
||||
@ -452,14 +450,16 @@ endmodule
|
||||
|
||||
module instrTrackerTB(
|
||||
input logic clk, reset, FlushE,
|
||||
input logic [31:0] InstrD,
|
||||
input logic [31:0] InstrF, InstrD,
|
||||
input logic [31:0] InstrE, InstrM,
|
||||
output logic [31:0] InstrW,
|
||||
output string InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
input logic [31:0] InstrW,
|
||||
// output logic [31:0] InstrW,
|
||||
output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// stage Instr to Writeback for visualization
|
||||
flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
|
||||
// flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
|
||||
|
||||
instrNameDecTB fdec(InstrF, InstrFName);
|
||||
instrNameDecTB ddec(InstrD, InstrDName);
|
||||
instrNameDecTB edec(InstrE, InstrEName);
|
||||
instrNameDecTB mdec(InstrM, InstrMName);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user