cvw/wally-pipelined
Ross Thompson ca546beaf8 We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
..
bin cleanup 2021-01-18 00:42:40 -05:00
config Parallel FSR's and F CTRL logic 2021-02-04 02:25:55 -06:00
regression bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
src We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. 2021-02-15 14:51:39 -06:00
testbench added branch tests 2021-02-12 22:40:08 -05:00
testgen added branch tests 2021-02-12 22:40:08 -05:00
lint-wally Reorganized src hierarchically 2021-01-30 11:50:37 -05:00