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change how testbench reads data

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we're not sure if this is a good idea, but for now, we broke things up into 3 seperate
files, each read seperately. One for pc and instructions, one for registers, and one for
memory reads. Each is scrolled through essentially independantly: new pc data is read and checked
whenever pc changes, new register data is checked whenever any register changes, and a new mem
read value is gotten whenever DataAdrM or MemRWM changes and MemRWM is not zero. I'm not super
sure about the last one. Currently it looks like things should be working, but it goes wrong after,
like, 3 instructions.
This commit is contained in:
Noah Boorstin 2021-01-22 20:27:01 -05:00
parent adfeb29b77
commit cdcacb8dbe
1 changed files with 56 additions and 14 deletions
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70
wally-pipelined/src/testbench-busybear.sv
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@ -25,12 +25,11 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
reset <= 1; # 22; reset <= 0;
end
// read instr trace file
integer data_file, scan_file;
integer read_data;
// read pc trace file
integer data_file_PC, scan_file_PC;
initial begin
data_file = $fopen("busybear-testgen/parsed.txt", "r");
if (data_file == 0) begin
data_file_PC = $fopen("busybear-testgen/parsedPC.txt", "r");
if (data_file_PC == 0) begin
$display("file couldn't be opened");
$stop;
end
@ -44,23 +43,66 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
// //end
// end
end
// read register trace file
integer data_file_rf, scan_file_rf;
initial begin
data_file_rf = $fopen("busybear-testgen/parsedRegs.txt", "r");
if (data_file_rf == 0) begin
$display("file couldn't be opened");
$stop;
end
end
// read memreads trace file
integer data_file_mem, scan_file_mem;
initial begin
data_file_mem = $fopen("busybear-testgen/parsedMemRead.txt", "r");
if (data_file_mem == 0) begin
$display("file couldn't be opened");
$stop;
end
end
logic [63:0] rfExpected[31:1];
logic [63:0] pcExpected;
// I apologize for this hack, I don't have a clue how to properly work with packed arrays
logic [64*32:64] rf;
genvar i;
generate
for(i=1; i<32; i++) begin
assign rf[i*64+63:i*64] = dut.dp.regf.rf[i];
end
endgenerate
always @(rf) begin
for(int j=1; j<32; j++) begin
// read 31 integer registers
scan_file_rf = $fscanf(data_file_rf, "%x\n", rfExpected[j]);
// check things!
if (rf[j*64+63 -: 64] != rfExpected[j]) begin
$display("rf[%i] does not equal rf expected: %x, %x", j, rf[j*64+63 -: 64], rfExpected[j]);
end
end
end
// this might need to change
always @(MemRWM or DataAdrM) begin
if (MemRWM != 0) begin
scan_file_mem = $fscanf(data_file_mem, "%x\n", ReadDataM);
end
end
always @(PCF) begin
//$display("%x", PCF);
scan_file = $fscanf(data_file, "%x\n", InstrF);
for(int i=1; i < 32; i++) begin
scan_file = $fscanf(data_file, "%x\n", rfExpected[i]);
end
scan_file = $fscanf(data_file, "%x\n", pcExpected);
// first read instruction
scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF);
// then expected PC value
scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
//check things!
if (PCF != pcExpected) begin
$display("PC does not equal PC expected: %x, %x", PCF, pcExpected);
end
//$display("%x", InstrF);
end