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WALLY-LRSC atomic test passing
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@ -27,8 +27,8 @@
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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//`define MISA (32'h00000104)
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`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12)
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//`define MISA (32'h00000105)
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`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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@ -113,6 +113,6 @@ configure wave -childrowmargin 2
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set DefaultRadix hexadecimal
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-- Run the Simulation
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#run 2000
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#run 4100
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run -all
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#quit
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@ -100,7 +100,7 @@ module dmem (
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assign lrM = MemReadM && AtomicM;
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assign scM = MemRWM[0] && AtomicM;
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assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM == ReservationPAdrW) && ReservationValidW;
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assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`XLEN-1:2] == ReservationPAdrW) && ReservationValidW;
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assign SquashSCM = scM && ~WriteAdrMatchM;
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always_comb begin // ReservationValidM (next valiue of valid reservation)
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if (lrM) ReservationValidM = 1; // set valid on load reserve
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@ -116,7 +116,7 @@ module controller(
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if (InstrD[31:27] == 5'b00010)
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ControlsD = 22'b1_000_00_10_001_0_00_0_0_0_0_0_0_1_0; // lr
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else if (InstrD[31:27] == 5'b00011)
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ControlsD = 22'b1_101_01_01_110_0_00_0_0_0_0_0_0_1_0; // sc
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ControlsD = 22'b1_101_01_01_101_0_00_0_0_0_0_0_0_1_0; // sc
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else
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ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_1_0; // other atomic; decode later
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end else
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@ -37,6 +37,9 @@ module testbench();
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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//logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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string tests64a[] = '{
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"rv64a/WALLY-LRSC", "2110"
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};
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string tests64m[] = '{
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"rv64m/I-MUL-01", "3000",
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"rv64m/I-MULH-01", "3000",
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@ -322,9 +325,11 @@ string tests32i[] = {
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initial
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if (`XLEN == 64) begin // RV64
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tests = {tests64i};
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if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic};
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else tests = {tests, tests64iNOc};
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if (`M_SUPPORTED % 2 == 1) tests = {tests, tests64m};
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if (`C_SUPPORTED) tests = {tests, tests64ic};
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else tests = {tests, tests64iNOc};
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if (`M_SUPPORTED) tests = {tests, tests64m};
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if (`A_SUPPORTED) tests = {tests64a, tests};
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// tests = {tests64a, tests};
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end else begin // RV32
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tests = {tests32i};
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if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
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@ -368,6 +373,7 @@ string tests32i[] = {
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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$display("Read memfile %s", memfilename);
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reset = 1; # 42; reset = 0;
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end
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@ -584,6 +590,30 @@ module instrNameDecTB(
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10'b1110011_101: name = "CSRRWI";
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10'b1110011_110: name = "CSRRSI";
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10'b1110011_111: name = "CSRRCI";
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10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W";
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else if (funct7[6:2] == 5'b00011) name = "SC.W";
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else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
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else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
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else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
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else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
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else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
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else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
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else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
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else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
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else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
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else name = "ILLEGAL";
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10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D";
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else if (funct7[6:2] == 5'b00011) name = "SC.D";
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else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
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else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
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else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
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else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
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else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
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else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
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else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
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else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
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else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
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else name = "ILLEGAL";
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10'b0001111_???: name = "FENCE";
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default: name = "ILLEGAL";
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endcase
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